1 /* 2 * linux/arch/arm/mach-omap2/clock24xx.h 3 * 4 * Copyright (C) 2005-2008 Texas Instruments, Inc. 5 * Copyright (C) 2004-2008 Nokia Corporation 6 * 7 * Contacts: 8 * Richard Woodruff <r-woodruff2@ti.com> 9 * Paul Walmsley 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 16 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H 17 #define __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H 18 19 #include "clock.h" 20 21 #include "prm.h" 22 #include "cm.h" 23 #include "prm-regbits-24xx.h" 24 #include "cm-regbits-24xx.h" 25 #include "sdrc.h" 26 27 static void omap2_table_mpu_recalc(struct clk *clk); 28 static int omap2_select_table_rate(struct clk *clk, unsigned long rate); 29 static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate); 30 static void omap2_sys_clk_recalc(struct clk *clk); 31 static void omap2_osc_clk_recalc(struct clk *clk); 32 static void omap2_sys_clk_recalc(struct clk *clk); 33 static void omap2_dpllcore_recalc(struct clk *clk); 34 static int omap2_clk_fixed_enable(struct clk *clk); 35 static void omap2_clk_fixed_disable(struct clk *clk); 36 static int omap2_enable_osc_ck(struct clk *clk); 37 static void omap2_disable_osc_ck(struct clk *clk); 38 static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate); 39 40 /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated. 41 * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP 42 * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM 43 */ 44 struct prcm_config { 45 unsigned long xtal_speed; /* crystal rate */ 46 unsigned long dpll_speed; /* dpll: out*xtal*M/(N-1)table_recalc */ 47 unsigned long mpu_speed; /* speed of MPU */ 48 unsigned long cm_clksel_mpu; /* mpu divider */ 49 unsigned long cm_clksel_dsp; /* dsp+iva1 div(2420), iva2.1(2430) */ 50 unsigned long cm_clksel_gfx; /* gfx dividers */ 51 unsigned long cm_clksel1_core; /* major subsystem dividers */ 52 unsigned long cm_clksel1_pll; /* m,n */ 53 unsigned long cm_clksel2_pll; /* dpllx1 or x2 out */ 54 unsigned long cm_clksel_mdm; /* modem dividers 2430 only */ 55 unsigned long base_sdrc_rfr; /* base refresh timing for a set */ 56 unsigned char flags; 57 }; 58 59 /* 60 * The OMAP2 processor can be run at several discrete 'PRCM configurations'. 61 * These configurations are characterized by voltage and speed for clocks. 62 * The device is only validated for certain combinations. One way to express 63 * these combinations is via the 'ratio's' which the clocks operate with 64 * respect to each other. These ratio sets are for a given voltage/DPLL 65 * setting. All configurations can be described by a DPLL setting and a ratio 66 * There are 3 ratio sets for the 2430 and X ratio sets for 2420. 67 * 68 * 2430 differs from 2420 in that there are no more phase synchronizers used. 69 * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs 70 * 2430 (iva2.1, NOdsp, mdm) 71 */ 72 73 /* Core fields for cm_clksel, not ratio governed */ 74 #define RX_CLKSEL_DSS1 (0x10 << 8) 75 #define RX_CLKSEL_DSS2 (0x0 << 13) 76 #define RX_CLKSEL_SSI (0x5 << 20) 77 78 /*------------------------------------------------------------------------- 79 * Voltage/DPLL ratios 80 *-------------------------------------------------------------------------*/ 81 82 /* 2430 Ratio's, 2430-Ratio Config 1 */ 83 #define R1_CLKSEL_L3 (4 << 0) 84 #define R1_CLKSEL_L4 (2 << 5) 85 #define R1_CLKSEL_USB (4 << 25) 86 #define R1_CM_CLKSEL1_CORE_VAL R1_CLKSEL_USB | RX_CLKSEL_SSI | \ 87 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \ 88 R1_CLKSEL_L4 | R1_CLKSEL_L3 89 #define R1_CLKSEL_MPU (2 << 0) 90 #define R1_CM_CLKSEL_MPU_VAL R1_CLKSEL_MPU 91 #define R1_CLKSEL_DSP (2 << 0) 92 #define R1_CLKSEL_DSP_IF (2 << 5) 93 #define R1_CM_CLKSEL_DSP_VAL R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF 94 #define R1_CLKSEL_GFX (2 << 0) 95 #define R1_CM_CLKSEL_GFX_VAL R1_CLKSEL_GFX 96 #define R1_CLKSEL_MDM (4 << 0) 97 #define R1_CM_CLKSEL_MDM_VAL R1_CLKSEL_MDM 98 99 /* 2430-Ratio Config 2 */ 100 #define R2_CLKSEL_L3 (6 << 0) 101 #define R2_CLKSEL_L4 (2 << 5) 102 #define R2_CLKSEL_USB (2 << 25) 103 #define R2_CM_CLKSEL1_CORE_VAL R2_CLKSEL_USB | RX_CLKSEL_SSI | \ 104 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \ 105 R2_CLKSEL_L4 | R2_CLKSEL_L3 106 #define R2_CLKSEL_MPU (2 << 0) 107 #define R2_CM_CLKSEL_MPU_VAL R2_CLKSEL_MPU 108 #define R2_CLKSEL_DSP (2 << 0) 109 #define R2_CLKSEL_DSP_IF (3 << 5) 110 #define R2_CM_CLKSEL_DSP_VAL R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF 111 #define R2_CLKSEL_GFX (2 << 0) 112 #define R2_CM_CLKSEL_GFX_VAL R2_CLKSEL_GFX 113 #define R2_CLKSEL_MDM (6 << 0) 114 #define R2_CM_CLKSEL_MDM_VAL R2_CLKSEL_MDM 115 116 /* 2430-Ratio Bootm (BYPASS) */ 117 #define RB_CLKSEL_L3 (1 << 0) 118 #define RB_CLKSEL_L4 (1 << 5) 119 #define RB_CLKSEL_USB (1 << 25) 120 #define RB_CM_CLKSEL1_CORE_VAL RB_CLKSEL_USB | RX_CLKSEL_SSI | \ 121 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \ 122 RB_CLKSEL_L4 | RB_CLKSEL_L3 123 #define RB_CLKSEL_MPU (1 << 0) 124 #define RB_CM_CLKSEL_MPU_VAL RB_CLKSEL_MPU 125 #define RB_CLKSEL_DSP (1 << 0) 126 #define RB_CLKSEL_DSP_IF (1 << 5) 127 #define RB_CM_CLKSEL_DSP_VAL RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF 128 #define RB_CLKSEL_GFX (1 << 0) 129 #define RB_CM_CLKSEL_GFX_VAL RB_CLKSEL_GFX 130 #define RB_CLKSEL_MDM (1 << 0) 131 #define RB_CM_CLKSEL_MDM_VAL RB_CLKSEL_MDM 132 133 /* 2420 Ratio Equivalents */ 134 #define RXX_CLKSEL_VLYNQ (0x12 << 15) 135 #define RXX_CLKSEL_SSI (0x8 << 20) 136 137 /* 2420-PRCM III 532MHz core */ 138 #define RIII_CLKSEL_L3 (4 << 0) /* 133MHz */ 139 #define RIII_CLKSEL_L4 (2 << 5) /* 66.5MHz */ 140 #define RIII_CLKSEL_USB (4 << 25) /* 33.25MHz */ 141 #define RIII_CM_CLKSEL1_CORE_VAL RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \ 142 RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \ 143 RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \ 144 RIII_CLKSEL_L3 145 #define RIII_CLKSEL_MPU (2 << 0) /* 266MHz */ 146 #define RIII_CM_CLKSEL_MPU_VAL RIII_CLKSEL_MPU 147 #define RIII_CLKSEL_DSP (3 << 0) /* c5x - 177.3MHz */ 148 #define RIII_CLKSEL_DSP_IF (2 << 5) /* c5x - 88.67MHz */ 149 #define RIII_SYNC_DSP (1 << 7) /* Enable sync */ 150 #define RIII_CLKSEL_IVA (6 << 8) /* iva1 - 88.67MHz */ 151 #define RIII_SYNC_IVA (1 << 13) /* Enable sync */ 152 #define RIII_CM_CLKSEL_DSP_VAL RIII_SYNC_IVA | RIII_CLKSEL_IVA | \ 153 RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \ 154 RIII_CLKSEL_DSP 155 #define RIII_CLKSEL_GFX (2 << 0) /* 66.5MHz */ 156 #define RIII_CM_CLKSEL_GFX_VAL RIII_CLKSEL_GFX 157 158 /* 2420-PRCM II 600MHz core */ 159 #define RII_CLKSEL_L3 (6 << 0) /* 100MHz */ 160 #define RII_CLKSEL_L4 (2 << 5) /* 50MHz */ 161 #define RII_CLKSEL_USB (2 << 25) /* 50MHz */ 162 #define RII_CM_CLKSEL1_CORE_VAL RII_CLKSEL_USB | \ 163 RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \ 164 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \ 165 RII_CLKSEL_L4 | RII_CLKSEL_L3 166 #define RII_CLKSEL_MPU (2 << 0) /* 300MHz */ 167 #define RII_CM_CLKSEL_MPU_VAL RII_CLKSEL_MPU 168 #define RII_CLKSEL_DSP (3 << 0) /* c5x - 200MHz */ 169 #define RII_CLKSEL_DSP_IF (2 << 5) /* c5x - 100MHz */ 170 #define RII_SYNC_DSP (0 << 7) /* Bypass sync */ 171 #define RII_CLKSEL_IVA (3 << 8) /* iva1 - 200MHz */ 172 #define RII_SYNC_IVA (0 << 13) /* Bypass sync */ 173 #define RII_CM_CLKSEL_DSP_VAL RII_SYNC_IVA | RII_CLKSEL_IVA | \ 174 RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \ 175 RII_CLKSEL_DSP 176 #define RII_CLKSEL_GFX (2 << 0) /* 50MHz */ 177 #define RII_CM_CLKSEL_GFX_VAL RII_CLKSEL_GFX 178 179 /* 2420-PRCM I 660MHz core */ 180 #define RI_CLKSEL_L3 (4 << 0) /* 165MHz */ 181 #define RI_CLKSEL_L4 (2 << 5) /* 82.5MHz */ 182 #define RI_CLKSEL_USB (4 << 25) /* 41.25MHz */ 183 #define RI_CM_CLKSEL1_CORE_VAL RI_CLKSEL_USB | \ 184 RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \ 185 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \ 186 RI_CLKSEL_L4 | RI_CLKSEL_L3 187 #define RI_CLKSEL_MPU (2 << 0) /* 330MHz */ 188 #define RI_CM_CLKSEL_MPU_VAL RI_CLKSEL_MPU 189 #define RI_CLKSEL_DSP (3 << 0) /* c5x - 220MHz */ 190 #define RI_CLKSEL_DSP_IF (2 << 5) /* c5x - 110MHz */ 191 #define RI_SYNC_DSP (1 << 7) /* Activate sync */ 192 #define RI_CLKSEL_IVA (4 << 8) /* iva1 - 165MHz */ 193 #define RI_SYNC_IVA (0 << 13) /* Bypass sync */ 194 #define RI_CM_CLKSEL_DSP_VAL RI_SYNC_IVA | RI_CLKSEL_IVA | \ 195 RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \ 196 RI_CLKSEL_DSP 197 #define RI_CLKSEL_GFX (1 << 0) /* 165MHz */ 198 #define RI_CM_CLKSEL_GFX_VAL RI_CLKSEL_GFX 199 200 /* 2420-PRCM VII (boot) */ 201 #define RVII_CLKSEL_L3 (1 << 0) 202 #define RVII_CLKSEL_L4 (1 << 5) 203 #define RVII_CLKSEL_DSS1 (1 << 8) 204 #define RVII_CLKSEL_DSS2 (0 << 13) 205 #define RVII_CLKSEL_VLYNQ (1 << 15) 206 #define RVII_CLKSEL_SSI (1 << 20) 207 #define RVII_CLKSEL_USB (1 << 25) 208 209 #define RVII_CM_CLKSEL1_CORE_VAL RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \ 210 RVII_CLKSEL_VLYNQ | RVII_CLKSEL_DSS2 | \ 211 RVII_CLKSEL_DSS1 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3 212 213 #define RVII_CLKSEL_MPU (1 << 0) /* all divide by 1 */ 214 #define RVII_CM_CLKSEL_MPU_VAL RVII_CLKSEL_MPU 215 216 #define RVII_CLKSEL_DSP (1 << 0) 217 #define RVII_CLKSEL_DSP_IF (1 << 5) 218 #define RVII_SYNC_DSP (0 << 7) 219 #define RVII_CLKSEL_IVA (1 << 8) 220 #define RVII_SYNC_IVA (0 << 13) 221 #define RVII_CM_CLKSEL_DSP_VAL RVII_SYNC_IVA | RVII_CLKSEL_IVA | RVII_SYNC_DSP | \ 222 RVII_CLKSEL_DSP_IF | RVII_CLKSEL_DSP 223 224 #define RVII_CLKSEL_GFX (1 << 0) 225 #define RVII_CM_CLKSEL_GFX_VAL RVII_CLKSEL_GFX 226 227 /*------------------------------------------------------------------------- 228 * 2430 Target modes: Along with each configuration the CPU has several 229 * modes which goes along with them. Modes mainly are the addition of 230 * describe DPLL combinations to go along with a ratio. 231 *-------------------------------------------------------------------------*/ 232 233 /* Hardware governed */ 234 #define MX_48M_SRC (0 << 3) 235 #define MX_54M_SRC (0 << 5) 236 #define MX_APLLS_CLIKIN_12 (3 << 23) 237 #define MX_APLLS_CLIKIN_13 (2 << 23) 238 #define MX_APLLS_CLIKIN_19_2 (0 << 23) 239 240 /* 241 * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed 242 * #5a (ratio1) baseport-target, target DPLL = 266*2 = 532MHz 243 */ 244 #define M5A_DPLL_MULT_12 (133 << 12) 245 #define M5A_DPLL_DIV_12 (5 << 8) 246 #define M5A_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \ 247 M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \ 248 MX_APLLS_CLIKIN_12 249 #define M5A_DPLL_MULT_13 (61 << 12) 250 #define M5A_DPLL_DIV_13 (2 << 8) 251 #define M5A_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \ 252 M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \ 253 MX_APLLS_CLIKIN_13 254 #define M5A_DPLL_MULT_19 (55 << 12) 255 #define M5A_DPLL_DIV_19 (3 << 8) 256 #define M5A_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \ 257 M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \ 258 MX_APLLS_CLIKIN_19_2 259 /* #5b (ratio1) target DPLL = 200*2 = 400MHz */ 260 #define M5B_DPLL_MULT_12 (50 << 12) 261 #define M5B_DPLL_DIV_12 (2 << 8) 262 #define M5B_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \ 263 M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \ 264 MX_APLLS_CLIKIN_12 265 #define M5B_DPLL_MULT_13 (200 << 12) 266 #define M5B_DPLL_DIV_13 (12 << 8) 267 268 #define M5B_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \ 269 M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \ 270 MX_APLLS_CLIKIN_13 271 #define M5B_DPLL_MULT_19 (125 << 12) 272 #define M5B_DPLL_DIV_19 (31 << 8) 273 #define M5B_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \ 274 M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \ 275 MX_APLLS_CLIKIN_19_2 276 /* 277 * #4 (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz 278 */ 279 #define M4_DPLL_MULT_12 (133 << 12) 280 #define M4_DPLL_DIV_12 (3 << 8) 281 #define M4_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \ 282 M4_DPLL_DIV_12 | M4_DPLL_MULT_12 | \ 283 MX_APLLS_CLIKIN_12 284 285 #define M4_DPLL_MULT_13 (399 << 12) 286 #define M4_DPLL_DIV_13 (12 << 8) 287 #define M4_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \ 288 M4_DPLL_DIV_13 | M4_DPLL_MULT_13 | \ 289 MX_APLLS_CLIKIN_13 290 291 #define M4_DPLL_MULT_19 (145 << 12) 292 #define M4_DPLL_DIV_19 (6 << 8) 293 #define M4_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \ 294 M4_DPLL_DIV_19 | M4_DPLL_MULT_19 | \ 295 MX_APLLS_CLIKIN_19_2 296 297 /* 298 * #3 (ratio2) baseport-target, target DPLL = 330*2 = 660MHz 299 */ 300 #define M3_DPLL_MULT_12 (55 << 12) 301 #define M3_DPLL_DIV_12 (1 << 8) 302 #define M3_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \ 303 M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \ 304 MX_APLLS_CLIKIN_12 305 #define M3_DPLL_MULT_13 (76 << 12) 306 #define M3_DPLL_DIV_13 (2 << 8) 307 #define M3_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \ 308 M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \ 309 MX_APLLS_CLIKIN_13 310 #define M3_DPLL_MULT_19 (17 << 12) 311 #define M3_DPLL_DIV_19 (0 << 8) 312 #define M3_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \ 313 M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \ 314 MX_APLLS_CLIKIN_19_2 315 316 /* 317 * #2 (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz 318 */ 319 #define M2_DPLL_MULT_12 (55 << 12) 320 #define M2_DPLL_DIV_12 (1 << 8) 321 #define M2_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \ 322 M2_DPLL_DIV_12 | M2_DPLL_MULT_12 | \ 323 MX_APLLS_CLIKIN_12 324 325 /* Speed changes - Used 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2, 326 * relock time issue */ 327 /* Core frequency changed from 330/165 to 329/164 MHz*/ 328 #define M2_DPLL_MULT_13 (76 << 12) 329 #define M2_DPLL_DIV_13 (2 << 8) 330 #define M2_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \ 331 M2_DPLL_DIV_13 | M2_DPLL_MULT_13 | \ 332 MX_APLLS_CLIKIN_13 333 334 #define M2_DPLL_MULT_19 (17 << 12) 335 #define M2_DPLL_DIV_19 (0 << 8) 336 #define M2_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \ 337 M2_DPLL_DIV_19 | M2_DPLL_MULT_19 | \ 338 MX_APLLS_CLIKIN_19_2 339 340 /* boot (boot) */ 341 #define MB_DPLL_MULT (1 << 12) 342 #define MB_DPLL_DIV (0 << 8) 343 #define MB_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\ 344 MB_DPLL_MULT | MX_APLLS_CLIKIN_12 345 346 #define MB_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\ 347 MB_DPLL_MULT | MX_APLLS_CLIKIN_13 348 349 #define MB_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\ 350 MB_DPLL_MULT | MX_APLLS_CLIKIN_19 351 352 /* 353 * 2430 - chassis (sedna) 354 * 165 (ratio1) same as above #2 355 * 150 (ratio1) 356 * 133 (ratio2) same as above #4 357 * 110 (ratio2) same as above #3 358 * 104 (ratio2) 359 * boot (boot) 360 */ 361 362 /* PRCM I target DPLL = 2*330MHz = 660MHz */ 363 #define MI_DPLL_MULT_12 (55 << 12) 364 #define MI_DPLL_DIV_12 (1 << 8) 365 #define MI_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \ 366 MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \ 367 MX_APLLS_CLIKIN_12 368 369 /* 370 * 2420 Equivalent - mode registers 371 * PRCM II , target DPLL = 2*300MHz = 600MHz 372 */ 373 #define MII_DPLL_MULT_12 (50 << 12) 374 #define MII_DPLL_DIV_12 (1 << 8) 375 #define MII_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \ 376 MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \ 377 MX_APLLS_CLIKIN_12 378 #define MII_DPLL_MULT_13 (300 << 12) 379 #define MII_DPLL_DIV_13 (12 << 8) 380 #define MII_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \ 381 MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \ 382 MX_APLLS_CLIKIN_13 383 384 /* PRCM III target DPLL = 2*266 = 532MHz*/ 385 #define MIII_DPLL_MULT_12 (133 << 12) 386 #define MIII_DPLL_DIV_12 (5 << 8) 387 #define MIII_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \ 388 MIII_DPLL_DIV_12 | MIII_DPLL_MULT_12 | \ 389 MX_APLLS_CLIKIN_12 390 #define MIII_DPLL_MULT_13 (266 << 12) 391 #define MIII_DPLL_DIV_13 (12 << 8) 392 #define MIII_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \ 393 MIII_DPLL_DIV_13 | MIII_DPLL_MULT_13 | \ 394 MX_APLLS_CLIKIN_13 395 396 /* PRCM VII (boot bypass) */ 397 #define MVII_CM_CLKSEL1_PLL_12_VAL MB_CM_CLKSEL1_PLL_12_VAL 398 #define MVII_CM_CLKSEL1_PLL_13_VAL MB_CM_CLKSEL1_PLL_13_VAL 399 400 /* High and low operation value */ 401 #define MX_CLKSEL2_PLL_2x_VAL (2 << 0) 402 #define MX_CLKSEL2_PLL_1x_VAL (1 << 0) 403 404 /* MPU speed defines */ 405 #define S12M 12000000 406 #define S13M 13000000 407 #define S19M 19200000 408 #define S26M 26000000 409 #define S100M 100000000 410 #define S133M 133000000 411 #define S150M 150000000 412 #define S164M 164000000 413 #define S165M 165000000 414 #define S199M 199000000 415 #define S200M 200000000 416 #define S266M 266000000 417 #define S300M 300000000 418 #define S329M 329000000 419 #define S330M 330000000 420 #define S399M 399000000 421 #define S400M 400000000 422 #define S532M 532000000 423 #define S600M 600000000 424 #define S658M 658000000 425 #define S660M 660000000 426 #define S798M 798000000 427 428 /*------------------------------------------------------------------------- 429 * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated. 430 * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU, 431 * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL, 432 * CM_CLKSEL2_PLL, CM_CLKSEL_MDM 433 * 434 * Filling in table based on H4 boards and 2430-SDPs variants available. 435 * There are quite a few more rates combinations which could be defined. 436 * 437 * When multiple values are defined the start up will try and choose the 438 * fastest one. If a 'fast' value is defined, then automatically, the /2 439 * one should be included as it can be used. Generally having more that 440 * one fast set does not make sense, as static timings need to be changed 441 * to change the set. The exception is the bypass setting which is 442 * availble for low power bypass. 443 * 444 * Note: This table needs to be sorted, fastest to slowest. 445 *-------------------------------------------------------------------------*/ 446 static struct prcm_config rate_table[] = { 447 /* PRCM I - FAST */ 448 {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */ 449 RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL, 450 RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL, 451 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_165MHz, 452 RATE_IN_242X}, 453 454 /* PRCM II - FAST */ 455 {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */ 456 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL, 457 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL, 458 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz, 459 RATE_IN_242X}, 460 461 {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */ 462 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL, 463 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL, 464 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz, 465 RATE_IN_242X}, 466 467 /* PRCM III - FAST */ 468 {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */ 469 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL, 470 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL, 471 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz, 472 RATE_IN_242X}, 473 474 {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */ 475 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL, 476 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL, 477 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz, 478 RATE_IN_242X}, 479 480 /* PRCM II - SLOW */ 481 {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */ 482 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL, 483 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL, 484 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz, 485 RATE_IN_242X}, 486 487 {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */ 488 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL, 489 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL, 490 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz, 491 RATE_IN_242X}, 492 493 /* PRCM III - SLOW */ 494 {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */ 495 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL, 496 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL, 497 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz, 498 RATE_IN_242X}, 499 500 {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */ 501 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL, 502 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL, 503 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz, 504 RATE_IN_242X}, 505 506 /* PRCM-VII (boot-bypass) */ 507 {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL, /* 12MHz ARM*/ 508 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL, 509 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL, 510 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS, 511 RATE_IN_242X}, 512 513 /* PRCM-VII (boot-bypass) */ 514 {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL, /* 13MHz ARM */ 515 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL, 516 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL, 517 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS, 518 RATE_IN_242X}, 519 520 /* PRCM #4 - ratio2 (ES2.1) - FAST */ 521 {S13M, S798M, S399M, R2_CM_CLKSEL_MPU_VAL, /* 399MHz ARM */ 522 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL, 523 R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL, 524 MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL, 525 SDRC_RFR_CTRL_133MHz, 526 RATE_IN_243X}, 527 528 /* PRCM #2 - ratio1 (ES2) - FAST */ 529 {S13M, S658M, S329M, R1_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */ 530 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, 531 R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL, 532 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL, 533 SDRC_RFR_CTRL_165MHz, 534 RATE_IN_243X}, 535 536 /* PRCM #5a - ratio1 - FAST */ 537 {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */ 538 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, 539 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL, 540 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL, 541 SDRC_RFR_CTRL_133MHz, 542 RATE_IN_243X}, 543 544 /* PRCM #5b - ratio1 - FAST */ 545 {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */ 546 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, 547 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL, 548 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL, 549 SDRC_RFR_CTRL_100MHz, 550 RATE_IN_243X}, 551 552 /* PRCM #4 - ratio1 (ES2.1) - SLOW */ 553 {S13M, S399M, S199M, R2_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */ 554 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL, 555 R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL, 556 MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL, 557 SDRC_RFR_CTRL_133MHz, 558 RATE_IN_243X}, 559 560 /* PRCM #2 - ratio1 (ES2) - SLOW */ 561 {S13M, S329M, S164M, R1_CM_CLKSEL_MPU_VAL, /* 165MHz ARM */ 562 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, 563 R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL, 564 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL, 565 SDRC_RFR_CTRL_165MHz, 566 RATE_IN_243X}, 567 568 /* PRCM #5a - ratio1 - SLOW */ 569 {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */ 570 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, 571 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL, 572 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL, 573 SDRC_RFR_CTRL_133MHz, 574 RATE_IN_243X}, 575 576 /* PRCM #5b - ratio1 - SLOW*/ 577 {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL, /* 100MHz ARM */ 578 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, 579 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL, 580 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL, 581 SDRC_RFR_CTRL_100MHz, 582 RATE_IN_243X}, 583 584 /* PRCM-boot/bypass */ 585 {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL, /* 13Mhz */ 586 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL, 587 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL, 588 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL, 589 SDRC_RFR_CTRL_BYPASS, 590 RATE_IN_243X}, 591 592 /* PRCM-boot/bypass */ 593 {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL, /* 12Mhz */ 594 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL, 595 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL, 596 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL, 597 SDRC_RFR_CTRL_BYPASS, 598 RATE_IN_243X}, 599 600 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 601 }; 602 603 /*------------------------------------------------------------------------- 604 * 24xx clock tree. 605 * 606 * NOTE:In many cases here we are assigning a 'default' parent. In many 607 * cases the parent is selectable. The get/set parent calls will also 608 * switch sources. 609 * 610 * Many some clocks say always_enabled, but they can be auto idled for 611 * power savings. They will always be available upon clock request. 612 * 613 * Several sources are given initial rates which may be wrong, this will 614 * be fixed up in the init func. 615 * 616 * Things are broadly separated below by clock domains. It is 617 * noteworthy that most periferals have dependencies on multiple clock 618 * domains. Many get their interface clocks from the L4 domain, but get 619 * functional clocks from fixed sources or other core domain derived 620 * clocks. 621 *-------------------------------------------------------------------------*/ 622 623 /* Base external input clocks */ 624 static struct clk func_32k_ck = { 625 .name = "func_32k_ck", 626 .rate = 32000, 627 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 628 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES, 629 .clkdm_name = "wkup_clkdm", 630 .recalc = &propagate_rate, 631 }; 632 633 /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */ 634 static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */ 635 .name = "osc_ck", 636 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 637 RATE_PROPAGATES, 638 .clkdm_name = "wkup_clkdm", 639 .enable = &omap2_enable_osc_ck, 640 .disable = &omap2_disable_osc_ck, 641 .recalc = &omap2_osc_clk_recalc, 642 }; 643 644 /* Without modem likely 12MHz, with modem likely 13MHz */ 645 static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */ 646 .name = "sys_ck", /* ~ ref_clk also */ 647 .parent = &osc_ck, 648 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 649 ALWAYS_ENABLED | RATE_PROPAGATES, 650 .clkdm_name = "wkup_clkdm", 651 .recalc = &omap2_sys_clk_recalc, 652 }; 653 654 static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */ 655 .name = "alt_ck", 656 .rate = 54000000, 657 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 658 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES, 659 .clkdm_name = "wkup_clkdm", 660 .recalc = &propagate_rate, 661 }; 662 663 /* 664 * Analog domain root source clocks 665 */ 666 667 /* dpll_ck, is broken out in to special cases through clksel */ 668 /* REVISIT: Rate changes on dpll_ck trigger a full set change. ... 669 * deal with this 670 */ 671 672 static struct dpll_data dpll_dd = { 673 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), 674 .mult_mask = OMAP24XX_DPLL_MULT_MASK, 675 .div1_mask = OMAP24XX_DPLL_DIV_MASK, 676 .max_multiplier = 1024, 677 .max_divider = 16, 678 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE 679 }; 680 681 /* 682 * XXX Cannot add round_rate here yet, as this is still a composite clock, 683 * not just a DPLL 684 */ 685 static struct clk dpll_ck = { 686 .name = "dpll_ck", 687 .parent = &sys_ck, /* Can be func_32k also */ 688 .dpll_data = &dpll_dd, 689 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 690 RATE_PROPAGATES | ALWAYS_ENABLED, 691 .clkdm_name = "wkup_clkdm", 692 .recalc = &omap2_dpllcore_recalc, 693 .set_rate = &omap2_reprogram_dpllcore, 694 }; 695 696 static struct clk apll96_ck = { 697 .name = "apll96_ck", 698 .parent = &sys_ck, 699 .rate = 96000000, 700 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 701 RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT, 702 .clkdm_name = "wkup_clkdm", 703 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 704 .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT, 705 .enable = &omap2_clk_fixed_enable, 706 .disable = &omap2_clk_fixed_disable, 707 .recalc = &propagate_rate, 708 }; 709 710 static struct clk apll54_ck = { 711 .name = "apll54_ck", 712 .parent = &sys_ck, 713 .rate = 54000000, 714 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 715 RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT, 716 .clkdm_name = "wkup_clkdm", 717 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 718 .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT, 719 .enable = &omap2_clk_fixed_enable, 720 .disable = &omap2_clk_fixed_disable, 721 .recalc = &propagate_rate, 722 }; 723 724 /* 725 * PRCM digital base sources 726 */ 727 728 /* func_54m_ck */ 729 730 static const struct clksel_rate func_54m_apll54_rates[] = { 731 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, 732 { .div = 0 }, 733 }; 734 735 static const struct clksel_rate func_54m_alt_rates[] = { 736 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, 737 { .div = 0 }, 738 }; 739 740 static const struct clksel func_54m_clksel[] = { 741 { .parent = &apll54_ck, .rates = func_54m_apll54_rates, }, 742 { .parent = &alt_ck, .rates = func_54m_alt_rates, }, 743 { .parent = NULL }, 744 }; 745 746 static struct clk func_54m_ck = { 747 .name = "func_54m_ck", 748 .parent = &apll54_ck, /* can also be alt_clk */ 749 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 750 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, 751 .clkdm_name = "wkup_clkdm", 752 .init = &omap2_init_clksel_parent, 753 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), 754 .clksel_mask = OMAP24XX_54M_SOURCE, 755 .clksel = func_54m_clksel, 756 .recalc = &omap2_clksel_recalc, 757 }; 758 759 static struct clk core_ck = { 760 .name = "core_ck", 761 .parent = &dpll_ck, /* can also be 32k */ 762 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 763 ALWAYS_ENABLED | RATE_PROPAGATES, 764 .clkdm_name = "wkup_clkdm", 765 .recalc = &followparent_recalc, 766 }; 767 768 /* func_96m_ck */ 769 static const struct clksel_rate func_96m_apll96_rates[] = { 770 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, 771 { .div = 0 }, 772 }; 773 774 static const struct clksel_rate func_96m_alt_rates[] = { 775 { .div = 1, .val = 1, .flags = RATE_IN_243X | DEFAULT_RATE }, 776 { .div = 0 }, 777 }; 778 779 static const struct clksel func_96m_clksel[] = { 780 { .parent = &apll96_ck, .rates = func_96m_apll96_rates }, 781 { .parent = &alt_ck, .rates = func_96m_alt_rates }, 782 { .parent = NULL } 783 }; 784 785 /* The parent of this clock is not selectable on 2420. */ 786 static struct clk func_96m_ck = { 787 .name = "func_96m_ck", 788 .parent = &apll96_ck, 789 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 790 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, 791 .clkdm_name = "wkup_clkdm", 792 .init = &omap2_init_clksel_parent, 793 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), 794 .clksel_mask = OMAP2430_96M_SOURCE, 795 .clksel = func_96m_clksel, 796 .recalc = &omap2_clksel_recalc, 797 .round_rate = &omap2_clksel_round_rate, 798 .set_rate = &omap2_clksel_set_rate 799 }; 800 801 /* func_48m_ck */ 802 803 static const struct clksel_rate func_48m_apll96_rates[] = { 804 { .div = 2, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, 805 { .div = 0 }, 806 }; 807 808 static const struct clksel_rate func_48m_alt_rates[] = { 809 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, 810 { .div = 0 }, 811 }; 812 813 static const struct clksel func_48m_clksel[] = { 814 { .parent = &apll96_ck, .rates = func_48m_apll96_rates }, 815 { .parent = &alt_ck, .rates = func_48m_alt_rates }, 816 { .parent = NULL } 817 }; 818 819 static struct clk func_48m_ck = { 820 .name = "func_48m_ck", 821 .parent = &apll96_ck, /* 96M or Alt */ 822 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 823 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, 824 .clkdm_name = "wkup_clkdm", 825 .init = &omap2_init_clksel_parent, 826 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), 827 .clksel_mask = OMAP24XX_48M_SOURCE, 828 .clksel = func_48m_clksel, 829 .recalc = &omap2_clksel_recalc, 830 .round_rate = &omap2_clksel_round_rate, 831 .set_rate = &omap2_clksel_set_rate 832 }; 833 834 static struct clk func_12m_ck = { 835 .name = "func_12m_ck", 836 .parent = &func_48m_ck, 837 .fixed_div = 4, 838 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 839 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, 840 .clkdm_name = "wkup_clkdm", 841 .recalc = &omap2_fixed_divisor_recalc, 842 }; 843 844 /* Secure timer, only available in secure mode */ 845 static struct clk wdt1_osc_ck = { 846 .name = "ck_wdt1_osc", 847 .parent = &osc_ck, 848 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 849 .recalc = &followparent_recalc, 850 }; 851 852 /* 853 * The common_clkout* clksel_rate structs are common to 854 * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src. 855 * sys_clkout2_* are 2420-only, so the 856 * clksel_rate flags fields are inaccurate for those clocks. This is 857 * harmless since access to those clocks are gated by the struct clk 858 * flags fields, which mark them as 2420-only. 859 */ 860 static const struct clksel_rate common_clkout_src_core_rates[] = { 861 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, 862 { .div = 0 } 863 }; 864 865 static const struct clksel_rate common_clkout_src_sys_rates[] = { 866 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, 867 { .div = 0 } 868 }; 869 870 static const struct clksel_rate common_clkout_src_96m_rates[] = { 871 { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE }, 872 { .div = 0 } 873 }; 874 875 static const struct clksel_rate common_clkout_src_54m_rates[] = { 876 { .div = 1, .val = 3, .flags = RATE_IN_24XX | DEFAULT_RATE }, 877 { .div = 0 } 878 }; 879 880 static const struct clksel common_clkout_src_clksel[] = { 881 { .parent = &core_ck, .rates = common_clkout_src_core_rates }, 882 { .parent = &sys_ck, .rates = common_clkout_src_sys_rates }, 883 { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates }, 884 { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates }, 885 { .parent = NULL } 886 }; 887 888 static struct clk sys_clkout_src = { 889 .name = "sys_clkout_src", 890 .parent = &func_54m_ck, 891 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 892 RATE_PROPAGATES, 893 .clkdm_name = "wkup_clkdm", 894 .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL, 895 .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT, 896 .init = &omap2_init_clksel_parent, 897 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL, 898 .clksel_mask = OMAP24XX_CLKOUT_SOURCE_MASK, 899 .clksel = common_clkout_src_clksel, 900 .recalc = &omap2_clksel_recalc, 901 .round_rate = &omap2_clksel_round_rate, 902 .set_rate = &omap2_clksel_set_rate 903 }; 904 905 static const struct clksel_rate common_clkout_rates[] = { 906 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, 907 { .div = 2, .val = 1, .flags = RATE_IN_24XX }, 908 { .div = 4, .val = 2, .flags = RATE_IN_24XX }, 909 { .div = 8, .val = 3, .flags = RATE_IN_24XX }, 910 { .div = 16, .val = 4, .flags = RATE_IN_24XX }, 911 { .div = 0 }, 912 }; 913 914 static const struct clksel sys_clkout_clksel[] = { 915 { .parent = &sys_clkout_src, .rates = common_clkout_rates }, 916 { .parent = NULL } 917 }; 918 919 static struct clk sys_clkout = { 920 .name = "sys_clkout", 921 .parent = &sys_clkout_src, 922 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 923 PARENT_CONTROLS_CLOCK, 924 .clkdm_name = "wkup_clkdm", 925 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL, 926 .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK, 927 .clksel = sys_clkout_clksel, 928 .recalc = &omap2_clksel_recalc, 929 .round_rate = &omap2_clksel_round_rate, 930 .set_rate = &omap2_clksel_set_rate 931 }; 932 933 /* In 2430, new in 2420 ES2 */ 934 static struct clk sys_clkout2_src = { 935 .name = "sys_clkout2_src", 936 .parent = &func_54m_ck, 937 .flags = CLOCK_IN_OMAP242X | RATE_PROPAGATES, 938 .clkdm_name = "wkup_clkdm", 939 .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL, 940 .enable_bit = OMAP2420_CLKOUT2_EN_SHIFT, 941 .init = &omap2_init_clksel_parent, 942 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL, 943 .clksel_mask = OMAP2420_CLKOUT2_SOURCE_MASK, 944 .clksel = common_clkout_src_clksel, 945 .recalc = &omap2_clksel_recalc, 946 .round_rate = &omap2_clksel_round_rate, 947 .set_rate = &omap2_clksel_set_rate 948 }; 949 950 static const struct clksel sys_clkout2_clksel[] = { 951 { .parent = &sys_clkout2_src, .rates = common_clkout_rates }, 952 { .parent = NULL } 953 }; 954 955 /* In 2430, new in 2420 ES2 */ 956 static struct clk sys_clkout2 = { 957 .name = "sys_clkout2", 958 .parent = &sys_clkout2_src, 959 .flags = CLOCK_IN_OMAP242X | PARENT_CONTROLS_CLOCK, 960 .clkdm_name = "wkup_clkdm", 961 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL, 962 .clksel_mask = OMAP2420_CLKOUT2_DIV_MASK, 963 .clksel = sys_clkout2_clksel, 964 .recalc = &omap2_clksel_recalc, 965 .round_rate = &omap2_clksel_round_rate, 966 .set_rate = &omap2_clksel_set_rate 967 }; 968 969 static struct clk emul_ck = { 970 .name = "emul_ck", 971 .parent = &func_54m_ck, 972 .flags = CLOCK_IN_OMAP242X, 973 .clkdm_name = "wkup_clkdm", 974 .enable_reg = OMAP24XX_PRCM_CLKEMUL_CTRL, 975 .enable_bit = OMAP24XX_EMULATION_EN_SHIFT, 976 .recalc = &followparent_recalc, 977 978 }; 979 980 /* 981 * MPU clock domain 982 * Clocks: 983 * MPU_FCLK, MPU_ICLK 984 * INT_M_FCLK, INT_M_I_CLK 985 * 986 * - Individual clocks are hardware managed. 987 * - Base divider comes from: CM_CLKSEL_MPU 988 * 989 */ 990 static const struct clksel_rate mpu_core_rates[] = { 991 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, 992 { .div = 2, .val = 2, .flags = RATE_IN_24XX }, 993 { .div = 4, .val = 4, .flags = RATE_IN_242X }, 994 { .div = 6, .val = 6, .flags = RATE_IN_242X }, 995 { .div = 8, .val = 8, .flags = RATE_IN_242X }, 996 { .div = 0 }, 997 }; 998 999 static const struct clksel mpu_clksel[] = { 1000 { .parent = &core_ck, .rates = mpu_core_rates }, 1001 { .parent = NULL } 1002 }; 1003 1004 static struct clk mpu_ck = { /* Control cpu */ 1005 .name = "mpu_ck", 1006 .parent = &core_ck, 1007 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1008 ALWAYS_ENABLED | DELAYED_APP | 1009 CONFIG_PARTICIPANT | RATE_PROPAGATES, 1010 .clkdm_name = "mpu_clkdm", 1011 .init = &omap2_init_clksel_parent, 1012 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL), 1013 .clksel_mask = OMAP24XX_CLKSEL_MPU_MASK, 1014 .clksel = mpu_clksel, 1015 .recalc = &omap2_clksel_recalc, 1016 .round_rate = &omap2_clksel_round_rate, 1017 .set_rate = &omap2_clksel_set_rate 1018 }; 1019 1020 /* 1021 * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain 1022 * Clocks: 1023 * 2430: IVA2.1_FCLK (really just DSP_FCLK), IVA2.1_ICLK 1024 * 2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP 1025 * 1026 * Won't be too specific here. The core clock comes into this block 1027 * it is divided then tee'ed. One branch goes directly to xyz enable 1028 * controls. The other branch gets further divided by 2 then possibly 1029 * routed into a synchronizer and out of clocks abc. 1030 */ 1031 static const struct clksel_rate dsp_fck_core_rates[] = { 1032 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, 1033 { .div = 2, .val = 2, .flags = RATE_IN_24XX }, 1034 { .div = 3, .val = 3, .flags = RATE_IN_24XX }, 1035 { .div = 4, .val = 4, .flags = RATE_IN_24XX }, 1036 { .div = 6, .val = 6, .flags = RATE_IN_242X }, 1037 { .div = 8, .val = 8, .flags = RATE_IN_242X }, 1038 { .div = 12, .val = 12, .flags = RATE_IN_242X }, 1039 { .div = 0 }, 1040 }; 1041 1042 static const struct clksel dsp_fck_clksel[] = { 1043 { .parent = &core_ck, .rates = dsp_fck_core_rates }, 1044 { .parent = NULL } 1045 }; 1046 1047 static struct clk dsp_fck = { 1048 .name = "dsp_fck", 1049 .parent = &core_ck, 1050 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP | 1051 CONFIG_PARTICIPANT | RATE_PROPAGATES, 1052 .clkdm_name = "dsp_clkdm", 1053 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), 1054 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, 1055 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), 1056 .clksel_mask = OMAP24XX_CLKSEL_DSP_MASK, 1057 .clksel = dsp_fck_clksel, 1058 .recalc = &omap2_clksel_recalc, 1059 .round_rate = &omap2_clksel_round_rate, 1060 .set_rate = &omap2_clksel_set_rate 1061 }; 1062 1063 /* DSP interface clock */ 1064 static const struct clksel_rate dsp_irate_ick_rates[] = { 1065 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, 1066 { .div = 2, .val = 2, .flags = RATE_IN_24XX }, 1067 { .div = 3, .val = 3, .flags = RATE_IN_243X }, 1068 { .div = 0 }, 1069 }; 1070 1071 static const struct clksel dsp_irate_ick_clksel[] = { 1072 { .parent = &dsp_fck, .rates = dsp_irate_ick_rates }, 1073 { .parent = NULL } 1074 }; 1075 1076 /* This clock does not exist as such in the TRM. */ 1077 static struct clk dsp_irate_ick = { 1078 .name = "dsp_irate_ick", 1079 .parent = &dsp_fck, 1080 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP | 1081 CONFIG_PARTICIPANT | PARENT_CONTROLS_CLOCK, 1082 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), 1083 .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK, 1084 .clksel = dsp_irate_ick_clksel, 1085 .recalc = &omap2_clksel_recalc, 1086 .round_rate = &omap2_clksel_round_rate, 1087 .set_rate = &omap2_clksel_set_rate 1088 }; 1089 1090 /* 2420 only */ 1091 static struct clk dsp_ick = { 1092 .name = "dsp_ick", /* apparently ipi and isp */ 1093 .parent = &dsp_irate_ick, 1094 .flags = CLOCK_IN_OMAP242X | DELAYED_APP | CONFIG_PARTICIPANT, 1095 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN), 1096 .enable_bit = OMAP2420_EN_DSP_IPI_SHIFT, /* for ipi */ 1097 }; 1098 1099 /* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */ 1100 static struct clk iva2_1_ick = { 1101 .name = "iva2_1_ick", 1102 .parent = &dsp_irate_ick, 1103 .flags = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT, 1104 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), 1105 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, 1106 }; 1107 1108 /* 1109 * The IVA1 is an ARM7 core on the 2420 that has nothing to do with 1110 * the C54x, but which is contained in the DSP powerdomain. Does not 1111 * exist on later OMAPs. 1112 */ 1113 static struct clk iva1_ifck = { 1114 .name = "iva1_ifck", 1115 .parent = &core_ck, 1116 .flags = CLOCK_IN_OMAP242X | CONFIG_PARTICIPANT | 1117 RATE_PROPAGATES | DELAYED_APP, 1118 .clkdm_name = "iva1_clkdm", 1119 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), 1120 .enable_bit = OMAP2420_EN_IVA_COP_SHIFT, 1121 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), 1122 .clksel_mask = OMAP2420_CLKSEL_IVA_MASK, 1123 .clksel = dsp_fck_clksel, 1124 .recalc = &omap2_clksel_recalc, 1125 .round_rate = &omap2_clksel_round_rate, 1126 .set_rate = &omap2_clksel_set_rate 1127 }; 1128 1129 /* IVA1 mpu/int/i/f clocks are /2 of parent */ 1130 static struct clk iva1_mpu_int_ifck = { 1131 .name = "iva1_mpu_int_ifck", 1132 .parent = &iva1_ifck, 1133 .flags = CLOCK_IN_OMAP242X, 1134 .clkdm_name = "iva1_clkdm", 1135 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), 1136 .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT, 1137 .fixed_div = 2, 1138 .recalc = &omap2_fixed_divisor_recalc, 1139 }; 1140 1141 /* 1142 * L3 clock domain 1143 * L3 clocks are used for both interface and functional clocks to 1144 * multiple entities. Some of these clocks are completely managed 1145 * by hardware, and some others allow software control. Hardware 1146 * managed ones general are based on directly CLK_REQ signals and 1147 * various auto idle settings. The functional spec sets many of these 1148 * as 'tie-high' for their enables. 1149 * 1150 * I-CLOCKS: 1151 * L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA 1152 * CAM, HS-USB. 1153 * F-CLOCK 1154 * SSI. 1155 * 1156 * GPMC memories and SDRC have timing and clock sensitive registers which 1157 * may very well need notification when the clock changes. Currently for low 1158 * operating points, these are taken care of in sleep.S. 1159 */ 1160 static const struct clksel_rate core_l3_core_rates[] = { 1161 { .div = 1, .val = 1, .flags = RATE_IN_24XX }, 1162 { .div = 2, .val = 2, .flags = RATE_IN_242X }, 1163 { .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE }, 1164 { .div = 6, .val = 6, .flags = RATE_IN_24XX }, 1165 { .div = 8, .val = 8, .flags = RATE_IN_242X }, 1166 { .div = 12, .val = 12, .flags = RATE_IN_242X }, 1167 { .div = 16, .val = 16, .flags = RATE_IN_242X }, 1168 { .div = 0 } 1169 }; 1170 1171 static const struct clksel core_l3_clksel[] = { 1172 { .parent = &core_ck, .rates = core_l3_core_rates }, 1173 { .parent = NULL } 1174 }; 1175 1176 static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */ 1177 .name = "core_l3_ck", 1178 .parent = &core_ck, 1179 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1180 ALWAYS_ENABLED | DELAYED_APP | 1181 CONFIG_PARTICIPANT | RATE_PROPAGATES, 1182 .clkdm_name = "core_l3_clkdm", 1183 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), 1184 .clksel_mask = OMAP24XX_CLKSEL_L3_MASK, 1185 .clksel = core_l3_clksel, 1186 .recalc = &omap2_clksel_recalc, 1187 .round_rate = &omap2_clksel_round_rate, 1188 .set_rate = &omap2_clksel_set_rate 1189 }; 1190 1191 /* usb_l4_ick */ 1192 static const struct clksel_rate usb_l4_ick_core_l3_rates[] = { 1193 { .div = 1, .val = 1, .flags = RATE_IN_24XX }, 1194 { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE }, 1195 { .div = 4, .val = 4, .flags = RATE_IN_24XX }, 1196 { .div = 0 } 1197 }; 1198 1199 static const struct clksel usb_l4_ick_clksel[] = { 1200 { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates }, 1201 { .parent = NULL }, 1202 }; 1203 1204 /* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */ 1205 static struct clk usb_l4_ick = { /* FS-USB interface clock */ 1206 .name = "usb_l4_ick", 1207 .parent = &core_l3_ck, 1208 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1209 DELAYED_APP | CONFIG_PARTICIPANT, 1210 .clkdm_name = "core_l4_clkdm", 1211 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1212 .enable_bit = OMAP24XX_EN_USB_SHIFT, 1213 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), 1214 .clksel_mask = OMAP24XX_CLKSEL_USB_MASK, 1215 .clksel = usb_l4_ick_clksel, 1216 .recalc = &omap2_clksel_recalc, 1217 .round_rate = &omap2_clksel_round_rate, 1218 .set_rate = &omap2_clksel_set_rate 1219 }; 1220 1221 /* 1222 * L4 clock management domain 1223 * 1224 * This domain contains lots of interface clocks from the L4 interface, some 1225 * functional clocks. Fixed APLL functional source clocks are managed in 1226 * this domain. 1227 */ 1228 static const struct clksel_rate l4_core_l3_rates[] = { 1229 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, 1230 { .div = 2, .val = 2, .flags = RATE_IN_24XX }, 1231 { .div = 0 } 1232 }; 1233 1234 static const struct clksel l4_clksel[] = { 1235 { .parent = &core_l3_ck, .rates = l4_core_l3_rates }, 1236 { .parent = NULL } 1237 }; 1238 1239 static struct clk l4_ck = { /* used both as an ick and fck */ 1240 .name = "l4_ck", 1241 .parent = &core_l3_ck, 1242 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1243 ALWAYS_ENABLED | DELAYED_APP | RATE_PROPAGATES, 1244 .clkdm_name = "core_l4_clkdm", 1245 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), 1246 .clksel_mask = OMAP24XX_CLKSEL_L4_MASK, 1247 .clksel = l4_clksel, 1248 .recalc = &omap2_clksel_recalc, 1249 .round_rate = &omap2_clksel_round_rate, 1250 .set_rate = &omap2_clksel_set_rate 1251 }; 1252 1253 /* 1254 * SSI is in L3 management domain, its direct parent is core not l3, 1255 * many core power domain entities are grouped into the L3 clock 1256 * domain. 1257 * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_ICLK 1258 * 1259 * ssr = core/1/2/3/4/5, sst = 1/2 ssr. 1260 */ 1261 static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = { 1262 { .div = 1, .val = 1, .flags = RATE_IN_24XX }, 1263 { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE }, 1264 { .div = 3, .val = 3, .flags = RATE_IN_24XX }, 1265 { .div = 4, .val = 4, .flags = RATE_IN_24XX }, 1266 { .div = 5, .val = 5, .flags = RATE_IN_243X }, 1267 { .div = 6, .val = 6, .flags = RATE_IN_242X }, 1268 { .div = 8, .val = 8, .flags = RATE_IN_242X }, 1269 { .div = 0 } 1270 }; 1271 1272 static const struct clksel ssi_ssr_sst_fck_clksel[] = { 1273 { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates }, 1274 { .parent = NULL } 1275 }; 1276 1277 static struct clk ssi_ssr_sst_fck = { 1278 .name = "ssi_fck", 1279 .parent = &core_ck, 1280 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1281 DELAYED_APP, 1282 .clkdm_name = "core_l3_clkdm", 1283 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 1284 .enable_bit = OMAP24XX_EN_SSI_SHIFT, 1285 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), 1286 .clksel_mask = OMAP24XX_CLKSEL_SSI_MASK, 1287 .clksel = ssi_ssr_sst_fck_clksel, 1288 .recalc = &omap2_clksel_recalc, 1289 .round_rate = &omap2_clksel_round_rate, 1290 .set_rate = &omap2_clksel_set_rate 1291 }; 1292 1293 1294 /* 1295 * GFX clock domain 1296 * Clocks: 1297 * GFX_FCLK, GFX_ICLK 1298 * GFX_CG1(2d), GFX_CG2(3d) 1299 * 1300 * GFX_FCLK runs from L3, and is divided by (1,2,3,4) 1301 * The 2d and 3d clocks run at a hardware determined 1302 * divided value of fclk. 1303 * 1304 */ 1305 /* XXX REVISIT: GFX clock is part of CONFIG_PARTICIPANT, no? doublecheck. */ 1306 1307 /* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */ 1308 static const struct clksel gfx_fck_clksel[] = { 1309 { .parent = &core_l3_ck, .rates = gfx_l3_rates }, 1310 { .parent = NULL }, 1311 }; 1312 1313 static struct clk gfx_3d_fck = { 1314 .name = "gfx_3d_fck", 1315 .parent = &core_l3_ck, 1316 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1317 .clkdm_name = "gfx_clkdm", 1318 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), 1319 .enable_bit = OMAP24XX_EN_3D_SHIFT, 1320 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), 1321 .clksel_mask = OMAP_CLKSEL_GFX_MASK, 1322 .clksel = gfx_fck_clksel, 1323 .recalc = &omap2_clksel_recalc, 1324 .round_rate = &omap2_clksel_round_rate, 1325 .set_rate = &omap2_clksel_set_rate 1326 }; 1327 1328 static struct clk gfx_2d_fck = { 1329 .name = "gfx_2d_fck", 1330 .parent = &core_l3_ck, 1331 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1332 .clkdm_name = "gfx_clkdm", 1333 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), 1334 .enable_bit = OMAP24XX_EN_2D_SHIFT, 1335 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), 1336 .clksel_mask = OMAP_CLKSEL_GFX_MASK, 1337 .clksel = gfx_fck_clksel, 1338 .recalc = &omap2_clksel_recalc, 1339 .round_rate = &omap2_clksel_round_rate, 1340 .set_rate = &omap2_clksel_set_rate 1341 }; 1342 1343 static struct clk gfx_ick = { 1344 .name = "gfx_ick", /* From l3 */ 1345 .parent = &core_l3_ck, 1346 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1347 .clkdm_name = "gfx_clkdm", 1348 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), 1349 .enable_bit = OMAP_EN_GFX_SHIFT, 1350 .recalc = &followparent_recalc, 1351 }; 1352 1353 /* 1354 * Modem clock domain (2430) 1355 * CLOCKS: 1356 * MDM_OSC_CLK 1357 * MDM_ICLK 1358 * These clocks are usable in chassis mode only. 1359 */ 1360 static const struct clksel_rate mdm_ick_core_rates[] = { 1361 { .div = 1, .val = 1, .flags = RATE_IN_243X }, 1362 { .div = 4, .val = 4, .flags = RATE_IN_243X | DEFAULT_RATE }, 1363 { .div = 6, .val = 6, .flags = RATE_IN_243X }, 1364 { .div = 9, .val = 9, .flags = RATE_IN_243X }, 1365 { .div = 0 } 1366 }; 1367 1368 static const struct clksel mdm_ick_clksel[] = { 1369 { .parent = &core_ck, .rates = mdm_ick_core_rates }, 1370 { .parent = NULL } 1371 }; 1372 1373 static struct clk mdm_ick = { /* used both as a ick and fck */ 1374 .name = "mdm_ick", 1375 .parent = &core_ck, 1376 .flags = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT, 1377 .clkdm_name = "mdm_clkdm", 1378 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN), 1379 .enable_bit = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT, 1380 .clksel_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL), 1381 .clksel_mask = OMAP2430_CLKSEL_MDM_MASK, 1382 .clksel = mdm_ick_clksel, 1383 .recalc = &omap2_clksel_recalc, 1384 .round_rate = &omap2_clksel_round_rate, 1385 .set_rate = &omap2_clksel_set_rate 1386 }; 1387 1388 static struct clk mdm_osc_ck = { 1389 .name = "mdm_osc_ck", 1390 .parent = &osc_ck, 1391 .flags = CLOCK_IN_OMAP243X, 1392 .clkdm_name = "mdm_clkdm", 1393 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN), 1394 .enable_bit = OMAP2430_EN_OSC_SHIFT, 1395 .recalc = &followparent_recalc, 1396 }; 1397 1398 /* 1399 * DSS clock domain 1400 * CLOCKs: 1401 * DSS_L4_ICLK, DSS_L3_ICLK, 1402 * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK 1403 * 1404 * DSS is both initiator and target. 1405 */ 1406 /* XXX Add RATE_NOT_VALIDATED */ 1407 1408 static const struct clksel_rate dss1_fck_sys_rates[] = { 1409 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, 1410 { .div = 0 } 1411 }; 1412 1413 static const struct clksel_rate dss1_fck_core_rates[] = { 1414 { .div = 1, .val = 1, .flags = RATE_IN_24XX }, 1415 { .div = 2, .val = 2, .flags = RATE_IN_24XX }, 1416 { .div = 3, .val = 3, .flags = RATE_IN_24XX }, 1417 { .div = 4, .val = 4, .flags = RATE_IN_24XX }, 1418 { .div = 5, .val = 5, .flags = RATE_IN_24XX }, 1419 { .div = 6, .val = 6, .flags = RATE_IN_24XX }, 1420 { .div = 8, .val = 8, .flags = RATE_IN_24XX }, 1421 { .div = 9, .val = 9, .flags = RATE_IN_24XX }, 1422 { .div = 12, .val = 12, .flags = RATE_IN_24XX }, 1423 { .div = 16, .val = 16, .flags = RATE_IN_24XX | DEFAULT_RATE }, 1424 { .div = 0 } 1425 }; 1426 1427 static const struct clksel dss1_fck_clksel[] = { 1428 { .parent = &sys_ck, .rates = dss1_fck_sys_rates }, 1429 { .parent = &core_ck, .rates = dss1_fck_core_rates }, 1430 { .parent = NULL }, 1431 }; 1432 1433 static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */ 1434 .name = "dss_ick", 1435 .parent = &l4_ck, /* really both l3 and l4 */ 1436 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1437 .clkdm_name = "dss_clkdm", 1438 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1439 .enable_bit = OMAP24XX_EN_DSS1_SHIFT, 1440 .recalc = &followparent_recalc, 1441 }; 1442 1443 static struct clk dss1_fck = { 1444 .name = "dss1_fck", 1445 .parent = &core_ck, /* Core or sys */ 1446 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1447 DELAYED_APP, 1448 .clkdm_name = "dss_clkdm", 1449 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1450 .enable_bit = OMAP24XX_EN_DSS1_SHIFT, 1451 .init = &omap2_init_clksel_parent, 1452 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), 1453 .clksel_mask = OMAP24XX_CLKSEL_DSS1_MASK, 1454 .clksel = dss1_fck_clksel, 1455 .recalc = &omap2_clksel_recalc, 1456 .round_rate = &omap2_clksel_round_rate, 1457 .set_rate = &omap2_clksel_set_rate 1458 }; 1459 1460 static const struct clksel_rate dss2_fck_sys_rates[] = { 1461 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, 1462 { .div = 0 } 1463 }; 1464 1465 static const struct clksel_rate dss2_fck_48m_rates[] = { 1466 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, 1467 { .div = 0 } 1468 }; 1469 1470 static const struct clksel dss2_fck_clksel[] = { 1471 { .parent = &sys_ck, .rates = dss2_fck_sys_rates }, 1472 { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates }, 1473 { .parent = NULL } 1474 }; 1475 1476 static struct clk dss2_fck = { /* Alt clk used in power management */ 1477 .name = "dss2_fck", 1478 .parent = &sys_ck, /* fixed at sys_ck or 48MHz */ 1479 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1480 DELAYED_APP, 1481 .clkdm_name = "dss_clkdm", 1482 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1483 .enable_bit = OMAP24XX_EN_DSS2_SHIFT, 1484 .init = &omap2_init_clksel_parent, 1485 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), 1486 .clksel_mask = OMAP24XX_CLKSEL_DSS2_MASK, 1487 .clksel = dss2_fck_clksel, 1488 .recalc = &followparent_recalc, 1489 }; 1490 1491 static struct clk dss_54m_fck = { /* Alt clk used in power management */ 1492 .name = "dss_54m_fck", /* 54m tv clk */ 1493 .parent = &func_54m_ck, 1494 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1495 .clkdm_name = "dss_clkdm", 1496 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1497 .enable_bit = OMAP24XX_EN_TV_SHIFT, 1498 .recalc = &followparent_recalc, 1499 }; 1500 1501 /* 1502 * CORE power domain ICLK & FCLK defines. 1503 * Many of the these can have more than one possible parent. Entries 1504 * here will likely have an L4 interface parent, and may have multiple 1505 * functional clock parents. 1506 */ 1507 static const struct clksel_rate gpt_alt_rates[] = { 1508 { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE }, 1509 { .div = 0 } 1510 }; 1511 1512 static const struct clksel omap24xx_gpt_clksel[] = { 1513 { .parent = &func_32k_ck, .rates = gpt_32k_rates }, 1514 { .parent = &sys_ck, .rates = gpt_sys_rates }, 1515 { .parent = &alt_ck, .rates = gpt_alt_rates }, 1516 { .parent = NULL }, 1517 }; 1518 1519 static struct clk gpt1_ick = { 1520 .name = "gpt1_ick", 1521 .parent = &l4_ck, 1522 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1523 .clkdm_name = "core_l4_clkdm", 1524 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 1525 .enable_bit = OMAP24XX_EN_GPT1_SHIFT, 1526 .recalc = &followparent_recalc, 1527 }; 1528 1529 static struct clk gpt1_fck = { 1530 .name = "gpt1_fck", 1531 .parent = &func_32k_ck, 1532 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1533 .clkdm_name = "core_l4_clkdm", 1534 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), 1535 .enable_bit = OMAP24XX_EN_GPT1_SHIFT, 1536 .init = &omap2_init_clksel_parent, 1537 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1), 1538 .clksel_mask = OMAP24XX_CLKSEL_GPT1_MASK, 1539 .clksel = omap24xx_gpt_clksel, 1540 .recalc = &omap2_clksel_recalc, 1541 .round_rate = &omap2_clksel_round_rate, 1542 .set_rate = &omap2_clksel_set_rate 1543 }; 1544 1545 static struct clk gpt2_ick = { 1546 .name = "gpt2_ick", 1547 .parent = &l4_ck, 1548 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1549 .clkdm_name = "core_l4_clkdm", 1550 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1551 .enable_bit = OMAP24XX_EN_GPT2_SHIFT, 1552 .recalc = &followparent_recalc, 1553 }; 1554 1555 static struct clk gpt2_fck = { 1556 .name = "gpt2_fck", 1557 .parent = &func_32k_ck, 1558 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1559 .clkdm_name = "core_l4_clkdm", 1560 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1561 .enable_bit = OMAP24XX_EN_GPT2_SHIFT, 1562 .init = &omap2_init_clksel_parent, 1563 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), 1564 .clksel_mask = OMAP24XX_CLKSEL_GPT2_MASK, 1565 .clksel = omap24xx_gpt_clksel, 1566 .recalc = &omap2_clksel_recalc, 1567 }; 1568 1569 static struct clk gpt3_ick = { 1570 .name = "gpt3_ick", 1571 .parent = &l4_ck, 1572 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1573 .clkdm_name = "core_l4_clkdm", 1574 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1575 .enable_bit = OMAP24XX_EN_GPT3_SHIFT, 1576 .recalc = &followparent_recalc, 1577 }; 1578 1579 static struct clk gpt3_fck = { 1580 .name = "gpt3_fck", 1581 .parent = &func_32k_ck, 1582 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1583 .clkdm_name = "core_l4_clkdm", 1584 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1585 .enable_bit = OMAP24XX_EN_GPT3_SHIFT, 1586 .init = &omap2_init_clksel_parent, 1587 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), 1588 .clksel_mask = OMAP24XX_CLKSEL_GPT3_MASK, 1589 .clksel = omap24xx_gpt_clksel, 1590 .recalc = &omap2_clksel_recalc, 1591 }; 1592 1593 static struct clk gpt4_ick = { 1594 .name = "gpt4_ick", 1595 .parent = &l4_ck, 1596 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1597 .clkdm_name = "core_l4_clkdm", 1598 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1599 .enable_bit = OMAP24XX_EN_GPT4_SHIFT, 1600 .recalc = &followparent_recalc, 1601 }; 1602 1603 static struct clk gpt4_fck = { 1604 .name = "gpt4_fck", 1605 .parent = &func_32k_ck, 1606 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1607 .clkdm_name = "core_l4_clkdm", 1608 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1609 .enable_bit = OMAP24XX_EN_GPT4_SHIFT, 1610 .init = &omap2_init_clksel_parent, 1611 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), 1612 .clksel_mask = OMAP24XX_CLKSEL_GPT4_MASK, 1613 .clksel = omap24xx_gpt_clksel, 1614 .recalc = &omap2_clksel_recalc, 1615 }; 1616 1617 static struct clk gpt5_ick = { 1618 .name = "gpt5_ick", 1619 .parent = &l4_ck, 1620 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1621 .clkdm_name = "core_l4_clkdm", 1622 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1623 .enable_bit = OMAP24XX_EN_GPT5_SHIFT, 1624 .recalc = &followparent_recalc, 1625 }; 1626 1627 static struct clk gpt5_fck = { 1628 .name = "gpt5_fck", 1629 .parent = &func_32k_ck, 1630 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1631 .clkdm_name = "core_l4_clkdm", 1632 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1633 .enable_bit = OMAP24XX_EN_GPT5_SHIFT, 1634 .init = &omap2_init_clksel_parent, 1635 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), 1636 .clksel_mask = OMAP24XX_CLKSEL_GPT5_MASK, 1637 .clksel = omap24xx_gpt_clksel, 1638 .recalc = &omap2_clksel_recalc, 1639 }; 1640 1641 static struct clk gpt6_ick = { 1642 .name = "gpt6_ick", 1643 .parent = &l4_ck, 1644 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1645 .clkdm_name = "core_l4_clkdm", 1646 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1647 .enable_bit = OMAP24XX_EN_GPT6_SHIFT, 1648 .recalc = &followparent_recalc, 1649 }; 1650 1651 static struct clk gpt6_fck = { 1652 .name = "gpt6_fck", 1653 .parent = &func_32k_ck, 1654 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1655 .clkdm_name = "core_l4_clkdm", 1656 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1657 .enable_bit = OMAP24XX_EN_GPT6_SHIFT, 1658 .init = &omap2_init_clksel_parent, 1659 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), 1660 .clksel_mask = OMAP24XX_CLKSEL_GPT6_MASK, 1661 .clksel = omap24xx_gpt_clksel, 1662 .recalc = &omap2_clksel_recalc, 1663 }; 1664 1665 static struct clk gpt7_ick = { 1666 .name = "gpt7_ick", 1667 .parent = &l4_ck, 1668 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1669 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1670 .enable_bit = OMAP24XX_EN_GPT7_SHIFT, 1671 .recalc = &followparent_recalc, 1672 }; 1673 1674 static struct clk gpt7_fck = { 1675 .name = "gpt7_fck", 1676 .parent = &func_32k_ck, 1677 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1678 .clkdm_name = "core_l4_clkdm", 1679 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1680 .enable_bit = OMAP24XX_EN_GPT7_SHIFT, 1681 .init = &omap2_init_clksel_parent, 1682 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), 1683 .clksel_mask = OMAP24XX_CLKSEL_GPT7_MASK, 1684 .clksel = omap24xx_gpt_clksel, 1685 .recalc = &omap2_clksel_recalc, 1686 }; 1687 1688 static struct clk gpt8_ick = { 1689 .name = "gpt8_ick", 1690 .parent = &l4_ck, 1691 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1692 .clkdm_name = "core_l4_clkdm", 1693 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1694 .enable_bit = OMAP24XX_EN_GPT8_SHIFT, 1695 .recalc = &followparent_recalc, 1696 }; 1697 1698 static struct clk gpt8_fck = { 1699 .name = "gpt8_fck", 1700 .parent = &func_32k_ck, 1701 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1702 .clkdm_name = "core_l4_clkdm", 1703 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1704 .enable_bit = OMAP24XX_EN_GPT8_SHIFT, 1705 .init = &omap2_init_clksel_parent, 1706 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), 1707 .clksel_mask = OMAP24XX_CLKSEL_GPT8_MASK, 1708 .clksel = omap24xx_gpt_clksel, 1709 .recalc = &omap2_clksel_recalc, 1710 }; 1711 1712 static struct clk gpt9_ick = { 1713 .name = "gpt9_ick", 1714 .parent = &l4_ck, 1715 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1716 .clkdm_name = "core_l4_clkdm", 1717 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1718 .enable_bit = OMAP24XX_EN_GPT9_SHIFT, 1719 .recalc = &followparent_recalc, 1720 }; 1721 1722 static struct clk gpt9_fck = { 1723 .name = "gpt9_fck", 1724 .parent = &func_32k_ck, 1725 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1726 .clkdm_name = "core_l4_clkdm", 1727 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1728 .enable_bit = OMAP24XX_EN_GPT9_SHIFT, 1729 .init = &omap2_init_clksel_parent, 1730 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), 1731 .clksel_mask = OMAP24XX_CLKSEL_GPT9_MASK, 1732 .clksel = omap24xx_gpt_clksel, 1733 .recalc = &omap2_clksel_recalc, 1734 }; 1735 1736 static struct clk gpt10_ick = { 1737 .name = "gpt10_ick", 1738 .parent = &l4_ck, 1739 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1740 .clkdm_name = "core_l4_clkdm", 1741 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1742 .enable_bit = OMAP24XX_EN_GPT10_SHIFT, 1743 .recalc = &followparent_recalc, 1744 }; 1745 1746 static struct clk gpt10_fck = { 1747 .name = "gpt10_fck", 1748 .parent = &func_32k_ck, 1749 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1750 .clkdm_name = "core_l4_clkdm", 1751 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1752 .enable_bit = OMAP24XX_EN_GPT10_SHIFT, 1753 .init = &omap2_init_clksel_parent, 1754 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), 1755 .clksel_mask = OMAP24XX_CLKSEL_GPT10_MASK, 1756 .clksel = omap24xx_gpt_clksel, 1757 .recalc = &omap2_clksel_recalc, 1758 }; 1759 1760 static struct clk gpt11_ick = { 1761 .name = "gpt11_ick", 1762 .parent = &l4_ck, 1763 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1764 .clkdm_name = "core_l4_clkdm", 1765 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1766 .enable_bit = OMAP24XX_EN_GPT11_SHIFT, 1767 .recalc = &followparent_recalc, 1768 }; 1769 1770 static struct clk gpt11_fck = { 1771 .name = "gpt11_fck", 1772 .parent = &func_32k_ck, 1773 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1774 .clkdm_name = "core_l4_clkdm", 1775 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1776 .enable_bit = OMAP24XX_EN_GPT11_SHIFT, 1777 .init = &omap2_init_clksel_parent, 1778 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), 1779 .clksel_mask = OMAP24XX_CLKSEL_GPT11_MASK, 1780 .clksel = omap24xx_gpt_clksel, 1781 .recalc = &omap2_clksel_recalc, 1782 }; 1783 1784 static struct clk gpt12_ick = { 1785 .name = "gpt12_ick", 1786 .parent = &l4_ck, 1787 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1788 .clkdm_name = "core_l4_clkdm", 1789 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1790 .enable_bit = OMAP24XX_EN_GPT12_SHIFT, 1791 .recalc = &followparent_recalc, 1792 }; 1793 1794 static struct clk gpt12_fck = { 1795 .name = "gpt12_fck", 1796 .parent = &func_32k_ck, 1797 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1798 .clkdm_name = "core_l4_clkdm", 1799 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1800 .enable_bit = OMAP24XX_EN_GPT12_SHIFT, 1801 .init = &omap2_init_clksel_parent, 1802 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), 1803 .clksel_mask = OMAP24XX_CLKSEL_GPT12_MASK, 1804 .clksel = omap24xx_gpt_clksel, 1805 .recalc = &omap2_clksel_recalc, 1806 }; 1807 1808 static struct clk mcbsp1_ick = { 1809 .name = "mcbsp_ick", 1810 .id = 1, 1811 .parent = &l4_ck, 1812 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1813 .clkdm_name = "core_l4_clkdm", 1814 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1815 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, 1816 .recalc = &followparent_recalc, 1817 }; 1818 1819 static struct clk mcbsp1_fck = { 1820 .name = "mcbsp_fck", 1821 .id = 1, 1822 .parent = &func_96m_ck, 1823 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1824 .clkdm_name = "core_l4_clkdm", 1825 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1826 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, 1827 .recalc = &followparent_recalc, 1828 }; 1829 1830 static struct clk mcbsp2_ick = { 1831 .name = "mcbsp_ick", 1832 .id = 2, 1833 .parent = &l4_ck, 1834 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1835 .clkdm_name = "core_l4_clkdm", 1836 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1837 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, 1838 .recalc = &followparent_recalc, 1839 }; 1840 1841 static struct clk mcbsp2_fck = { 1842 .name = "mcbsp_fck", 1843 .id = 2, 1844 .parent = &func_96m_ck, 1845 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1846 .clkdm_name = "core_l4_clkdm", 1847 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1848 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, 1849 .recalc = &followparent_recalc, 1850 }; 1851 1852 static struct clk mcbsp3_ick = { 1853 .name = "mcbsp_ick", 1854 .id = 3, 1855 .parent = &l4_ck, 1856 .flags = CLOCK_IN_OMAP243X, 1857 .clkdm_name = "core_l4_clkdm", 1858 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1859 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT, 1860 .recalc = &followparent_recalc, 1861 }; 1862 1863 static struct clk mcbsp3_fck = { 1864 .name = "mcbsp_fck", 1865 .id = 3, 1866 .parent = &func_96m_ck, 1867 .flags = CLOCK_IN_OMAP243X, 1868 .clkdm_name = "core_l4_clkdm", 1869 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 1870 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT, 1871 .recalc = &followparent_recalc, 1872 }; 1873 1874 static struct clk mcbsp4_ick = { 1875 .name = "mcbsp_ick", 1876 .id = 4, 1877 .parent = &l4_ck, 1878 .flags = CLOCK_IN_OMAP243X, 1879 .clkdm_name = "core_l4_clkdm", 1880 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1881 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT, 1882 .recalc = &followparent_recalc, 1883 }; 1884 1885 static struct clk mcbsp4_fck = { 1886 .name = "mcbsp_fck", 1887 .id = 4, 1888 .parent = &func_96m_ck, 1889 .flags = CLOCK_IN_OMAP243X, 1890 .clkdm_name = "core_l4_clkdm", 1891 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 1892 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT, 1893 .recalc = &followparent_recalc, 1894 }; 1895 1896 static struct clk mcbsp5_ick = { 1897 .name = "mcbsp_ick", 1898 .id = 5, 1899 .parent = &l4_ck, 1900 .flags = CLOCK_IN_OMAP243X, 1901 .clkdm_name = "core_l4_clkdm", 1902 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1903 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT, 1904 .recalc = &followparent_recalc, 1905 }; 1906 1907 static struct clk mcbsp5_fck = { 1908 .name = "mcbsp_fck", 1909 .id = 5, 1910 .parent = &func_96m_ck, 1911 .flags = CLOCK_IN_OMAP243X, 1912 .clkdm_name = "core_l4_clkdm", 1913 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 1914 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT, 1915 .recalc = &followparent_recalc, 1916 }; 1917 1918 static struct clk mcspi1_ick = { 1919 .name = "mcspi_ick", 1920 .id = 1, 1921 .parent = &l4_ck, 1922 .clkdm_name = "core_l4_clkdm", 1923 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1924 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1925 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, 1926 .recalc = &followparent_recalc, 1927 }; 1928 1929 static struct clk mcspi1_fck = { 1930 .name = "mcspi_fck", 1931 .id = 1, 1932 .parent = &func_48m_ck, 1933 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1934 .clkdm_name = "core_l4_clkdm", 1935 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1936 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, 1937 .recalc = &followparent_recalc, 1938 }; 1939 1940 static struct clk mcspi2_ick = { 1941 .name = "mcspi_ick", 1942 .id = 2, 1943 .parent = &l4_ck, 1944 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1945 .clkdm_name = "core_l4_clkdm", 1946 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1947 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, 1948 .recalc = &followparent_recalc, 1949 }; 1950 1951 static struct clk mcspi2_fck = { 1952 .name = "mcspi_fck", 1953 .id = 2, 1954 .parent = &func_48m_ck, 1955 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1956 .clkdm_name = "core_l4_clkdm", 1957 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1958 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, 1959 .recalc = &followparent_recalc, 1960 }; 1961 1962 static struct clk mcspi3_ick = { 1963 .name = "mcspi_ick", 1964 .id = 3, 1965 .parent = &l4_ck, 1966 .flags = CLOCK_IN_OMAP243X, 1967 .clkdm_name = "core_l4_clkdm", 1968 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1969 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT, 1970 .recalc = &followparent_recalc, 1971 }; 1972 1973 static struct clk mcspi3_fck = { 1974 .name = "mcspi_fck", 1975 .id = 3, 1976 .parent = &func_48m_ck, 1977 .flags = CLOCK_IN_OMAP243X, 1978 .clkdm_name = "core_l4_clkdm", 1979 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 1980 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT, 1981 .recalc = &followparent_recalc, 1982 }; 1983 1984 static struct clk uart1_ick = { 1985 .name = "uart1_ick", 1986 .parent = &l4_ck, 1987 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1988 .clkdm_name = "core_l4_clkdm", 1989 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1990 .enable_bit = OMAP24XX_EN_UART1_SHIFT, 1991 .recalc = &followparent_recalc, 1992 }; 1993 1994 static struct clk uart1_fck = { 1995 .name = "uart1_fck", 1996 .parent = &func_48m_ck, 1997 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1998 .clkdm_name = "core_l4_clkdm", 1999 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2000 .enable_bit = OMAP24XX_EN_UART1_SHIFT, 2001 .recalc = &followparent_recalc, 2002 }; 2003 2004 static struct clk uart2_ick = { 2005 .name = "uart2_ick", 2006 .parent = &l4_ck, 2007 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2008 .clkdm_name = "core_l4_clkdm", 2009 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2010 .enable_bit = OMAP24XX_EN_UART2_SHIFT, 2011 .recalc = &followparent_recalc, 2012 }; 2013 2014 static struct clk uart2_fck = { 2015 .name = "uart2_fck", 2016 .parent = &func_48m_ck, 2017 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2018 .clkdm_name = "core_l4_clkdm", 2019 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2020 .enable_bit = OMAP24XX_EN_UART2_SHIFT, 2021 .recalc = &followparent_recalc, 2022 }; 2023 2024 static struct clk uart3_ick = { 2025 .name = "uart3_ick", 2026 .parent = &l4_ck, 2027 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2028 .clkdm_name = "core_l4_clkdm", 2029 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 2030 .enable_bit = OMAP24XX_EN_UART3_SHIFT, 2031 .recalc = &followparent_recalc, 2032 }; 2033 2034 static struct clk uart3_fck = { 2035 .name = "uart3_fck", 2036 .parent = &func_48m_ck, 2037 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2038 .clkdm_name = "core_l4_clkdm", 2039 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 2040 .enable_bit = OMAP24XX_EN_UART3_SHIFT, 2041 .recalc = &followparent_recalc, 2042 }; 2043 2044 static struct clk gpios_ick = { 2045 .name = "gpios_ick", 2046 .parent = &l4_ck, 2047 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2048 .clkdm_name = "core_l4_clkdm", 2049 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2050 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, 2051 .recalc = &followparent_recalc, 2052 }; 2053 2054 static struct clk gpios_fck = { 2055 .name = "gpios_fck", 2056 .parent = &func_32k_ck, 2057 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2058 .clkdm_name = "wkup_clkdm", 2059 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), 2060 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, 2061 .recalc = &followparent_recalc, 2062 }; 2063 2064 static struct clk mpu_wdt_ick = { 2065 .name = "mpu_wdt_ick", 2066 .parent = &l4_ck, 2067 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2068 .clkdm_name = "core_l4_clkdm", 2069 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2070 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, 2071 .recalc = &followparent_recalc, 2072 }; 2073 2074 static struct clk mpu_wdt_fck = { 2075 .name = "mpu_wdt_fck", 2076 .parent = &func_32k_ck, 2077 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2078 .clkdm_name = "wkup_clkdm", 2079 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), 2080 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, 2081 .recalc = &followparent_recalc, 2082 }; 2083 2084 static struct clk sync_32k_ick = { 2085 .name = "sync_32k_ick", 2086 .parent = &l4_ck, 2087 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 2088 ENABLE_ON_INIT, 2089 .clkdm_name = "core_l4_clkdm", 2090 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2091 .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT, 2092 .recalc = &followparent_recalc, 2093 }; 2094 2095 static struct clk wdt1_ick = { 2096 .name = "wdt1_ick", 2097 .parent = &l4_ck, 2098 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2099 .clkdm_name = "core_l4_clkdm", 2100 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2101 .enable_bit = OMAP24XX_EN_WDT1_SHIFT, 2102 .recalc = &followparent_recalc, 2103 }; 2104 2105 static struct clk omapctrl_ick = { 2106 .name = "omapctrl_ick", 2107 .parent = &l4_ck, 2108 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 2109 ENABLE_ON_INIT, 2110 .clkdm_name = "core_l4_clkdm", 2111 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2112 .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT, 2113 .recalc = &followparent_recalc, 2114 }; 2115 2116 static struct clk icr_ick = { 2117 .name = "icr_ick", 2118 .parent = &l4_ck, 2119 .flags = CLOCK_IN_OMAP243X, 2120 .clkdm_name = "core_l4_clkdm", 2121 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2122 .enable_bit = OMAP2430_EN_ICR_SHIFT, 2123 .recalc = &followparent_recalc, 2124 }; 2125 2126 static struct clk cam_ick = { 2127 .name = "cam_ick", 2128 .parent = &l4_ck, 2129 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2130 .clkdm_name = "core_l4_clkdm", 2131 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2132 .enable_bit = OMAP24XX_EN_CAM_SHIFT, 2133 .recalc = &followparent_recalc, 2134 }; 2135 2136 /* 2137 * cam_fck controls both CAM_MCLK and CAM_FCLK. It should probably be 2138 * split into two separate clocks, since the parent clocks are different 2139 * and the clockdomains are also different. 2140 */ 2141 static struct clk cam_fck = { 2142 .name = "cam_fck", 2143 .parent = &func_96m_ck, 2144 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2145 .clkdm_name = "core_l3_clkdm", 2146 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2147 .enable_bit = OMAP24XX_EN_CAM_SHIFT, 2148 .recalc = &followparent_recalc, 2149 }; 2150 2151 static struct clk mailboxes_ick = { 2152 .name = "mailboxes_ick", 2153 .parent = &l4_ck, 2154 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2155 .clkdm_name = "core_l4_clkdm", 2156 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2157 .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT, 2158 .recalc = &followparent_recalc, 2159 }; 2160 2161 static struct clk wdt4_ick = { 2162 .name = "wdt4_ick", 2163 .parent = &l4_ck, 2164 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2165 .clkdm_name = "core_l4_clkdm", 2166 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2167 .enable_bit = OMAP24XX_EN_WDT4_SHIFT, 2168 .recalc = &followparent_recalc, 2169 }; 2170 2171 static struct clk wdt4_fck = { 2172 .name = "wdt4_fck", 2173 .parent = &func_32k_ck, 2174 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2175 .clkdm_name = "core_l4_clkdm", 2176 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2177 .enable_bit = OMAP24XX_EN_WDT4_SHIFT, 2178 .recalc = &followparent_recalc, 2179 }; 2180 2181 static struct clk wdt3_ick = { 2182 .name = "wdt3_ick", 2183 .parent = &l4_ck, 2184 .flags = CLOCK_IN_OMAP242X, 2185 .clkdm_name = "core_l4_clkdm", 2186 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2187 .enable_bit = OMAP2420_EN_WDT3_SHIFT, 2188 .recalc = &followparent_recalc, 2189 }; 2190 2191 static struct clk wdt3_fck = { 2192 .name = "wdt3_fck", 2193 .parent = &func_32k_ck, 2194 .flags = CLOCK_IN_OMAP242X, 2195 .clkdm_name = "core_l4_clkdm", 2196 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2197 .enable_bit = OMAP2420_EN_WDT3_SHIFT, 2198 .recalc = &followparent_recalc, 2199 }; 2200 2201 static struct clk mspro_ick = { 2202 .name = "mspro_ick", 2203 .parent = &l4_ck, 2204 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2205 .clkdm_name = "core_l4_clkdm", 2206 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2207 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, 2208 .recalc = &followparent_recalc, 2209 }; 2210 2211 static struct clk mspro_fck = { 2212 .name = "mspro_fck", 2213 .parent = &func_96m_ck, 2214 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2215 .clkdm_name = "core_l4_clkdm", 2216 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2217 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, 2218 .recalc = &followparent_recalc, 2219 }; 2220 2221 static struct clk mmc_ick = { 2222 .name = "mmc_ick", 2223 .parent = &l4_ck, 2224 .flags = CLOCK_IN_OMAP242X, 2225 .clkdm_name = "core_l4_clkdm", 2226 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2227 .enable_bit = OMAP2420_EN_MMC_SHIFT, 2228 .recalc = &followparent_recalc, 2229 }; 2230 2231 static struct clk mmc_fck = { 2232 .name = "mmc_fck", 2233 .parent = &func_96m_ck, 2234 .flags = CLOCK_IN_OMAP242X, 2235 .clkdm_name = "core_l4_clkdm", 2236 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2237 .enable_bit = OMAP2420_EN_MMC_SHIFT, 2238 .recalc = &followparent_recalc, 2239 }; 2240 2241 static struct clk fac_ick = { 2242 .name = "fac_ick", 2243 .parent = &l4_ck, 2244 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2245 .clkdm_name = "core_l4_clkdm", 2246 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2247 .enable_bit = OMAP24XX_EN_FAC_SHIFT, 2248 .recalc = &followparent_recalc, 2249 }; 2250 2251 static struct clk fac_fck = { 2252 .name = "fac_fck", 2253 .parent = &func_12m_ck, 2254 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2255 .clkdm_name = "core_l4_clkdm", 2256 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2257 .enable_bit = OMAP24XX_EN_FAC_SHIFT, 2258 .recalc = &followparent_recalc, 2259 }; 2260 2261 static struct clk eac_ick = { 2262 .name = "eac_ick", 2263 .parent = &l4_ck, 2264 .flags = CLOCK_IN_OMAP242X, 2265 .clkdm_name = "core_l4_clkdm", 2266 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2267 .enable_bit = OMAP2420_EN_EAC_SHIFT, 2268 .recalc = &followparent_recalc, 2269 }; 2270 2271 static struct clk eac_fck = { 2272 .name = "eac_fck", 2273 .parent = &func_96m_ck, 2274 .flags = CLOCK_IN_OMAP242X, 2275 .clkdm_name = "core_l4_clkdm", 2276 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2277 .enable_bit = OMAP2420_EN_EAC_SHIFT, 2278 .recalc = &followparent_recalc, 2279 }; 2280 2281 static struct clk hdq_ick = { 2282 .name = "hdq_ick", 2283 .parent = &l4_ck, 2284 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2285 .clkdm_name = "core_l4_clkdm", 2286 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2287 .enable_bit = OMAP24XX_EN_HDQ_SHIFT, 2288 .recalc = &followparent_recalc, 2289 }; 2290 2291 static struct clk hdq_fck = { 2292 .name = "hdq_fck", 2293 .parent = &func_12m_ck, 2294 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2295 .clkdm_name = "core_l4_clkdm", 2296 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2297 .enable_bit = OMAP24XX_EN_HDQ_SHIFT, 2298 .recalc = &followparent_recalc, 2299 }; 2300 2301 static struct clk i2c2_ick = { 2302 .name = "i2c_ick", 2303 .id = 2, 2304 .parent = &l4_ck, 2305 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2306 .clkdm_name = "core_l4_clkdm", 2307 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2308 .enable_bit = OMAP2420_EN_I2C2_SHIFT, 2309 .recalc = &followparent_recalc, 2310 }; 2311 2312 static struct clk i2c2_fck = { 2313 .name = "i2c_fck", 2314 .id = 2, 2315 .parent = &func_12m_ck, 2316 .flags = CLOCK_IN_OMAP242X, 2317 .clkdm_name = "core_l4_clkdm", 2318 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2319 .enable_bit = OMAP2420_EN_I2C2_SHIFT, 2320 .recalc = &followparent_recalc, 2321 }; 2322 2323 static struct clk i2chs2_fck = { 2324 .name = "i2c_fck", 2325 .id = 2, 2326 .parent = &func_96m_ck, 2327 .flags = CLOCK_IN_OMAP243X, 2328 .clkdm_name = "core_l4_clkdm", 2329 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 2330 .enable_bit = OMAP2430_EN_I2CHS2_SHIFT, 2331 .recalc = &followparent_recalc, 2332 }; 2333 2334 static struct clk i2c1_ick = { 2335 .name = "i2c_ick", 2336 .id = 1, 2337 .parent = &l4_ck, 2338 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2339 .clkdm_name = "core_l4_clkdm", 2340 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2341 .enable_bit = OMAP2420_EN_I2C1_SHIFT, 2342 .recalc = &followparent_recalc, 2343 }; 2344 2345 static struct clk i2c1_fck = { 2346 .name = "i2c_fck", 2347 .id = 1, 2348 .parent = &func_12m_ck, 2349 .flags = CLOCK_IN_OMAP242X, 2350 .clkdm_name = "core_l4_clkdm", 2351 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2352 .enable_bit = OMAP2420_EN_I2C1_SHIFT, 2353 .recalc = &followparent_recalc, 2354 }; 2355 2356 static struct clk i2chs1_fck = { 2357 .name = "i2c_fck", 2358 .id = 1, 2359 .parent = &func_96m_ck, 2360 .flags = CLOCK_IN_OMAP243X, 2361 .clkdm_name = "core_l4_clkdm", 2362 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 2363 .enable_bit = OMAP2430_EN_I2CHS1_SHIFT, 2364 .recalc = &followparent_recalc, 2365 }; 2366 2367 static struct clk gpmc_fck = { 2368 .name = "gpmc_fck", 2369 .parent = &core_l3_ck, 2370 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 2371 ENABLE_ON_INIT, 2372 .clkdm_name = "core_l3_clkdm", 2373 .recalc = &followparent_recalc, 2374 }; 2375 2376 static struct clk sdma_fck = { 2377 .name = "sdma_fck", 2378 .parent = &core_l3_ck, 2379 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2380 .clkdm_name = "core_l3_clkdm", 2381 .recalc = &followparent_recalc, 2382 }; 2383 2384 static struct clk sdma_ick = { 2385 .name = "sdma_ick", 2386 .parent = &l4_ck, 2387 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2388 .clkdm_name = "core_l3_clkdm", 2389 .recalc = &followparent_recalc, 2390 }; 2391 2392 static struct clk vlynq_ick = { 2393 .name = "vlynq_ick", 2394 .parent = &core_l3_ck, 2395 .flags = CLOCK_IN_OMAP242X, 2396 .clkdm_name = "core_l3_clkdm", 2397 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2398 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT, 2399 .recalc = &followparent_recalc, 2400 }; 2401 2402 static const struct clksel_rate vlynq_fck_96m_rates[] = { 2403 { .div = 1, .val = 0, .flags = RATE_IN_242X | DEFAULT_RATE }, 2404 { .div = 0 } 2405 }; 2406 2407 static const struct clksel_rate vlynq_fck_core_rates[] = { 2408 { .div = 1, .val = 1, .flags = RATE_IN_242X }, 2409 { .div = 2, .val = 2, .flags = RATE_IN_242X }, 2410 { .div = 3, .val = 3, .flags = RATE_IN_242X }, 2411 { .div = 4, .val = 4, .flags = RATE_IN_242X }, 2412 { .div = 6, .val = 6, .flags = RATE_IN_242X }, 2413 { .div = 8, .val = 8, .flags = RATE_IN_242X }, 2414 { .div = 9, .val = 9, .flags = RATE_IN_242X }, 2415 { .div = 12, .val = 12, .flags = RATE_IN_242X }, 2416 { .div = 16, .val = 16, .flags = RATE_IN_242X | DEFAULT_RATE }, 2417 { .div = 18, .val = 18, .flags = RATE_IN_242X }, 2418 { .div = 0 } 2419 }; 2420 2421 static const struct clksel vlynq_fck_clksel[] = { 2422 { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates }, 2423 { .parent = &core_ck, .rates = vlynq_fck_core_rates }, 2424 { .parent = NULL } 2425 }; 2426 2427 static struct clk vlynq_fck = { 2428 .name = "vlynq_fck", 2429 .parent = &func_96m_ck, 2430 .flags = CLOCK_IN_OMAP242X | DELAYED_APP, 2431 .clkdm_name = "core_l3_clkdm", 2432 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2433 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT, 2434 .init = &omap2_init_clksel_parent, 2435 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), 2436 .clksel_mask = OMAP2420_CLKSEL_VLYNQ_MASK, 2437 .clksel = vlynq_fck_clksel, 2438 .recalc = &omap2_clksel_recalc, 2439 .round_rate = &omap2_clksel_round_rate, 2440 .set_rate = &omap2_clksel_set_rate 2441 }; 2442 2443 static struct clk sdrc_ick = { 2444 .name = "sdrc_ick", 2445 .parent = &l4_ck, 2446 .flags = CLOCK_IN_OMAP243X | ENABLE_ON_INIT, 2447 .clkdm_name = "core_l4_clkdm", 2448 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), 2449 .enable_bit = OMAP2430_EN_SDRC_SHIFT, 2450 .recalc = &followparent_recalc, 2451 }; 2452 2453 static struct clk des_ick = { 2454 .name = "des_ick", 2455 .parent = &l4_ck, 2456 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, 2457 .clkdm_name = "core_l4_clkdm", 2458 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), 2459 .enable_bit = OMAP24XX_EN_DES_SHIFT, 2460 .recalc = &followparent_recalc, 2461 }; 2462 2463 static struct clk sha_ick = { 2464 .name = "sha_ick", 2465 .parent = &l4_ck, 2466 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, 2467 .clkdm_name = "core_l4_clkdm", 2468 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), 2469 .enable_bit = OMAP24XX_EN_SHA_SHIFT, 2470 .recalc = &followparent_recalc, 2471 }; 2472 2473 static struct clk rng_ick = { 2474 .name = "rng_ick", 2475 .parent = &l4_ck, 2476 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, 2477 .clkdm_name = "core_l4_clkdm", 2478 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), 2479 .enable_bit = OMAP24XX_EN_RNG_SHIFT, 2480 .recalc = &followparent_recalc, 2481 }; 2482 2483 static struct clk aes_ick = { 2484 .name = "aes_ick", 2485 .parent = &l4_ck, 2486 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, 2487 .clkdm_name = "core_l4_clkdm", 2488 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), 2489 .enable_bit = OMAP24XX_EN_AES_SHIFT, 2490 .recalc = &followparent_recalc, 2491 }; 2492 2493 static struct clk pka_ick = { 2494 .name = "pka_ick", 2495 .parent = &l4_ck, 2496 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, 2497 .clkdm_name = "core_l4_clkdm", 2498 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), 2499 .enable_bit = OMAP24XX_EN_PKA_SHIFT, 2500 .recalc = &followparent_recalc, 2501 }; 2502 2503 static struct clk usb_fck = { 2504 .name = "usb_fck", 2505 .parent = &func_48m_ck, 2506 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, 2507 .clkdm_name = "core_l3_clkdm", 2508 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 2509 .enable_bit = OMAP24XX_EN_USB_SHIFT, 2510 .recalc = &followparent_recalc, 2511 }; 2512 2513 static struct clk usbhs_ick = { 2514 .name = "usbhs_ick", 2515 .parent = &core_l3_ck, 2516 .flags = CLOCK_IN_OMAP243X, 2517 .clkdm_name = "core_l3_clkdm", 2518 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 2519 .enable_bit = OMAP2430_EN_USBHS_SHIFT, 2520 .recalc = &followparent_recalc, 2521 }; 2522 2523 static struct clk mmchs1_ick = { 2524 .name = "mmchs_ick", 2525 .parent = &l4_ck, 2526 .flags = CLOCK_IN_OMAP243X, 2527 .clkdm_name = "core_l4_clkdm", 2528 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 2529 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT, 2530 .recalc = &followparent_recalc, 2531 }; 2532 2533 static struct clk mmchs1_fck = { 2534 .name = "mmchs_fck", 2535 .parent = &func_96m_ck, 2536 .flags = CLOCK_IN_OMAP243X, 2537 .clkdm_name = "core_l3_clkdm", 2538 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 2539 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT, 2540 .recalc = &followparent_recalc, 2541 }; 2542 2543 static struct clk mmchs2_ick = { 2544 .name = "mmchs_ick", 2545 .id = 1, 2546 .parent = &l4_ck, 2547 .flags = CLOCK_IN_OMAP243X, 2548 .clkdm_name = "core_l4_clkdm", 2549 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 2550 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, 2551 .recalc = &followparent_recalc, 2552 }; 2553 2554 static struct clk mmchs2_fck = { 2555 .name = "mmchs_fck", 2556 .id = 1, 2557 .parent = &func_96m_ck, 2558 .flags = CLOCK_IN_OMAP243X, 2559 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 2560 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, 2561 .recalc = &followparent_recalc, 2562 }; 2563 2564 static struct clk gpio5_ick = { 2565 .name = "gpio5_ick", 2566 .parent = &l4_ck, 2567 .flags = CLOCK_IN_OMAP243X, 2568 .clkdm_name = "core_l4_clkdm", 2569 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 2570 .enable_bit = OMAP2430_EN_GPIO5_SHIFT, 2571 .recalc = &followparent_recalc, 2572 }; 2573 2574 static struct clk gpio5_fck = { 2575 .name = "gpio5_fck", 2576 .parent = &func_32k_ck, 2577 .flags = CLOCK_IN_OMAP243X, 2578 .clkdm_name = "core_l4_clkdm", 2579 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 2580 .enable_bit = OMAP2430_EN_GPIO5_SHIFT, 2581 .recalc = &followparent_recalc, 2582 }; 2583 2584 static struct clk mdm_intc_ick = { 2585 .name = "mdm_intc_ick", 2586 .parent = &l4_ck, 2587 .flags = CLOCK_IN_OMAP243X, 2588 .clkdm_name = "core_l4_clkdm", 2589 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 2590 .enable_bit = OMAP2430_EN_MDM_INTC_SHIFT, 2591 .recalc = &followparent_recalc, 2592 }; 2593 2594 static struct clk mmchsdb1_fck = { 2595 .name = "mmchsdb_fck", 2596 .parent = &func_32k_ck, 2597 .flags = CLOCK_IN_OMAP243X, 2598 .clkdm_name = "core_l4_clkdm", 2599 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 2600 .enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT, 2601 .recalc = &followparent_recalc, 2602 }; 2603 2604 static struct clk mmchsdb2_fck = { 2605 .name = "mmchsdb_fck", 2606 .id = 1, 2607 .parent = &func_32k_ck, 2608 .flags = CLOCK_IN_OMAP243X, 2609 .clkdm_name = "core_l4_clkdm", 2610 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 2611 .enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT, 2612 .recalc = &followparent_recalc, 2613 }; 2614 2615 /* 2616 * This clock is a composite clock which does entire set changes then 2617 * forces a rebalance. It keys on the MPU speed, but it really could 2618 * be any key speed part of a set in the rate table. 2619 * 2620 * to really change a set, you need memory table sets which get changed 2621 * in sram, pre-notifiers & post notifiers, changing the top set, without 2622 * having low level display recalc's won't work... this is why dpm notifiers 2623 * work, isr's off, walk a list of clocks already _off_ and not messing with 2624 * the bus. 2625 * 2626 * This clock should have no parent. It embodies the entire upper level 2627 * active set. A parent will mess up some of the init also. 2628 */ 2629 static struct clk virt_prcm_set = { 2630 .name = "virt_prcm_set", 2631 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 2632 VIRTUAL_CLOCK | ALWAYS_ENABLED | DELAYED_APP, 2633 .parent = &mpu_ck, /* Indexed by mpu speed, no parent */ 2634 .recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */ 2635 .set_rate = &omap2_select_table_rate, 2636 .round_rate = &omap2_round_to_table_rate, 2637 }; 2638 2639 static struct clk *onchip_24xx_clks[] __initdata = { 2640 /* external root sources */ 2641 &func_32k_ck, 2642 &osc_ck, 2643 &sys_ck, 2644 &alt_ck, 2645 /* internal analog sources */ 2646 &dpll_ck, 2647 &apll96_ck, 2648 &apll54_ck, 2649 /* internal prcm root sources */ 2650 &func_54m_ck, 2651 &core_ck, 2652 &func_96m_ck, 2653 &func_48m_ck, 2654 &func_12m_ck, 2655 &wdt1_osc_ck, 2656 &sys_clkout_src, 2657 &sys_clkout, 2658 &sys_clkout2_src, 2659 &sys_clkout2, 2660 &emul_ck, 2661 /* mpu domain clocks */ 2662 &mpu_ck, 2663 /* dsp domain clocks */ 2664 &dsp_fck, 2665 &dsp_irate_ick, 2666 &dsp_ick, /* 242x */ 2667 &iva2_1_ick, /* 243x */ 2668 &iva1_ifck, /* 242x */ 2669 &iva1_mpu_int_ifck, /* 242x */ 2670 /* GFX domain clocks */ 2671 &gfx_3d_fck, 2672 &gfx_2d_fck, 2673 &gfx_ick, 2674 /* Modem domain clocks */ 2675 &mdm_ick, 2676 &mdm_osc_ck, 2677 /* DSS domain clocks */ 2678 &dss_ick, 2679 &dss1_fck, 2680 &dss2_fck, 2681 &dss_54m_fck, 2682 /* L3 domain clocks */ 2683 &core_l3_ck, 2684 &ssi_ssr_sst_fck, 2685 &usb_l4_ick, 2686 /* L4 domain clocks */ 2687 &l4_ck, /* used as both core_l4 and wu_l4 */ 2688 /* virtual meta-group clock */ 2689 &virt_prcm_set, 2690 /* general l4 interface ck, multi-parent functional clk */ 2691 &gpt1_ick, 2692 &gpt1_fck, 2693 &gpt2_ick, 2694 &gpt2_fck, 2695 &gpt3_ick, 2696 &gpt3_fck, 2697 &gpt4_ick, 2698 &gpt4_fck, 2699 &gpt5_ick, 2700 &gpt5_fck, 2701 &gpt6_ick, 2702 &gpt6_fck, 2703 &gpt7_ick, 2704 &gpt7_fck, 2705 &gpt8_ick, 2706 &gpt8_fck, 2707 &gpt9_ick, 2708 &gpt9_fck, 2709 &gpt10_ick, 2710 &gpt10_fck, 2711 &gpt11_ick, 2712 &gpt11_fck, 2713 &gpt12_ick, 2714 &gpt12_fck, 2715 &mcbsp1_ick, 2716 &mcbsp1_fck, 2717 &mcbsp2_ick, 2718 &mcbsp2_fck, 2719 &mcbsp3_ick, 2720 &mcbsp3_fck, 2721 &mcbsp4_ick, 2722 &mcbsp4_fck, 2723 &mcbsp5_ick, 2724 &mcbsp5_fck, 2725 &mcspi1_ick, 2726 &mcspi1_fck, 2727 &mcspi2_ick, 2728 &mcspi2_fck, 2729 &mcspi3_ick, 2730 &mcspi3_fck, 2731 &uart1_ick, 2732 &uart1_fck, 2733 &uart2_ick, 2734 &uart2_fck, 2735 &uart3_ick, 2736 &uart3_fck, 2737 &gpios_ick, 2738 &gpios_fck, 2739 &mpu_wdt_ick, 2740 &mpu_wdt_fck, 2741 &sync_32k_ick, 2742 &wdt1_ick, 2743 &omapctrl_ick, 2744 &icr_ick, 2745 &cam_fck, 2746 &cam_ick, 2747 &mailboxes_ick, 2748 &wdt4_ick, 2749 &wdt4_fck, 2750 &wdt3_ick, 2751 &wdt3_fck, 2752 &mspro_ick, 2753 &mspro_fck, 2754 &mmc_ick, 2755 &mmc_fck, 2756 &fac_ick, 2757 &fac_fck, 2758 &eac_ick, 2759 &eac_fck, 2760 &hdq_ick, 2761 &hdq_fck, 2762 &i2c1_ick, 2763 &i2c1_fck, 2764 &i2chs1_fck, 2765 &i2c2_ick, 2766 &i2c2_fck, 2767 &i2chs2_fck, 2768 &gpmc_fck, 2769 &sdma_fck, 2770 &sdma_ick, 2771 &vlynq_ick, 2772 &vlynq_fck, 2773 &sdrc_ick, 2774 &des_ick, 2775 &sha_ick, 2776 &rng_ick, 2777 &aes_ick, 2778 &pka_ick, 2779 &usb_fck, 2780 &usbhs_ick, 2781 &mmchs1_ick, 2782 &mmchs1_fck, 2783 &mmchs2_ick, 2784 &mmchs2_fck, 2785 &gpio5_ick, 2786 &gpio5_fck, 2787 &mdm_intc_ick, 2788 &mmchsdb1_fck, 2789 &mmchsdb2_fck, 2790 }; 2791 2792 #endif 2793 2794