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Searched refs:stw (Results 1 – 25 of 77) sorted by relevance

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/arch/powerpc/kvm/
Dbooke_interrupts.S61 stw r5, VCPU_GPR(r5)(r4)
62 stw r6, VCPU_GPR(r6)(r4)
65 stw r5, VCPU_CTR(r4)
100 stw r3, VCPU_GPR(r3)(r4)
102 stw r3, VCPU_CR(r4)
103 stw r7, VCPU_GPR(r7)(r4)
104 stw r8, VCPU_GPR(r8)(r4)
105 stw r9, VCPU_GPR(r9)(r4)
118 stw r8, VCPU_TIMING_EXIT_TBL(r4)
119 stw r9, VCPU_TIMING_EXIT_TBU(r4)
[all …]
/arch/powerpc/platforms/83xx/
Dsuspend-asm.S51 stw r3, immrbase@l(r4)
69 stw r5, SS_MEMSAVE+0(r3)
70 stw r6, SS_MEMSAVE+4(r3)
76 stw r5, SS_HID+0(r3)
77 stw r6, SS_HID+4(r3)
78 stw r7, SS_HID+8(r3)
87 stw r4, SS_IABR+0(r3)
88 stw r5, SS_IABR+4(r3)
89 stw r6, SS_IBCR(r3)
90 stw r7, SS_DABR+0(r3)
[all …]
/arch/powerpc/lib/
Dcrtsavres.S53 stw 14,-72(11) /* save gp registers */
56 stw 15,-68(11)
59 stw 16,-64(11)
62 stw 17,-60(11)
65 stw 18,-56(11)
68 stw 19,-52(11)
71 stw 20,-48(11)
74 stw 21,-44(11)
77 stw 22,-40(11)
80 stw 23,-36(11)
[all …]
Dcopy_32.S21 stw r7,4(r6); \
22 stw r8,8(r6); \
23 stw r9,12(r6); \
36 stw r7,4(r6); \
38 stw r8,8(r6); \
40 stw r9,12(r6); \
104 10: stw r4, 4(r6)
105 stw r4, 8(r6)
106 stw r4, 12(r6)
107 stw r4, 16(r6)
[all …]
/arch/powerpc/boot/
Dcrtsavres.S57 stw 14,-72(11) /* save gp registers */
60 stw 15,-68(11)
63 stw 16,-64(11)
66 stw 17,-60(11)
69 stw 18,-56(11)
72 stw 19,-52(11)
75 stw 20,-48(11)
78 stw 21,-44(11)
81 stw 22,-40(11)
84 stw 23,-36(11)
[all …]
/arch/powerpc/kernel/
Dswsusp_32.S49 stw r0,SL_LR(r11)
51 stw r0,SL_CR(r11)
52 stw r1,SL_SP(r11)
53 stw r2,SL_R2(r11)
58 stw r4,SL_MSR(r11)
60 stw r4,SL_SDR1(r11)
64 stw r4,SL_TB(r11)
66 stw r5,SL_TB+4(r11)
73 stw r4,SL_SPRG0(r11)
75 stw r4,SL_SPRG0+4(r11)
[all …]
Dhead_booke.h26 stw r10,_CCR(r11); /* save various registers */\
27 stw r12,GPR12(r11); \
28 stw r9,GPR9(r11); \
30 stw r10,GPR10(r11); \
32 stw r12,GPR11(r11); \
34 stw r10,_LINK(r11); \
37 stw r10,GPR1(r11); \
39 stw r10,0(r11); \
41 stw r0,GPR0(r11); \
106 stw r9,GPR9(r8); /* save various registers */\
[all …]
Dentry_32.S51 stw r0,_DSRR0(r11)
53 stw r0,_DSRR1(r11)
59 stw r0,_CSRR0(r11)
61 stw r0,_CSRR1(r11)
68 stw r0,MAS0(r11)
70 stw r0,MAS1(r11)
72 stw r0,MAS2(r11)
74 stw r0,MAS3(r11)
76 stw r0,MAS6(r11)
79 stw r0,MAS7(r11)
[all …]
Dhead_40x.S124 stw r10,_CCR(r11); /* save various registers */\
125 stw r12,GPR12(r11); \
126 stw r9,GPR9(r11); \
128 stw r10,GPR10(r11); \
130 stw r12,GPR11(r11); \
132 stw r10,_LINK(r11); \
135 stw r10,GPR1(r11); \
137 stw r10,0(r11); \
139 stw r0,GPR0(r11); \
152 stw r10,crit_r10@l(0); /* save two registers to work with */\
[all …]
Dhead_8xx.S36 stw reg, 12(r0); \
132 stw r10,_CCR(r11); /* save registers */ \
133 stw r12,GPR12(r11); \
134 stw r9,GPR9(r11); \
136 stw r10,GPR10(r11); \
138 stw r12,GPR11(r11); \
140 stw r10,_LINK(r11); \
143 stw r1,GPR1(r11); \
144 stw r1,0(r11); \
148 stw r0,GPR0(r11); \
[all …]
Dhead_32.S216 stw r3,__secondary_hold_acknowledge@l(0)
263 stw r10,_CCR(r11); /* save registers */ \
264 stw r12,GPR12(r11); \
265 stw r9,GPR9(r11); \
267 stw r10,GPR10(r11); \
269 stw r12,GPR11(r11); \
271 stw r10,_LINK(r11); \
274 stw r1,GPR1(r11); \
275 stw r1,0(r11); \
279 stw r0,GPR0(r11); \
[all …]
Dcpu_setup_6xx.S195 stw r6,CPU_SPEC_FEATURES(r5)
228 stw r6,CPU_SPEC_FEATURES(r5)
322 stw r3,CS_HID0(r5)
346 stw r4,CS_MSSCR0(r5)
348 stw r4,CS_MSSSR0(r5)
352 stw r4,CS_HID1(r5)
354 stw r4,CS_ICTRL(r5)
356 stw r4,CS_LDSTCR(r5)
358 stw r4,CS_LDSTDB(r5)
363 stw r4,CS_HID1(r5)
[all …]
Didle_e500.S27 stw r4,TI_LOCAL_FLAGS(r3) /* it will return to our caller */
43 stw r0,20(r1)
84 stw r9,_NIP(r11) /* make it do a blr */
/arch/powerpc/platforms/powermac/
Dsleep.S62 stw r0,4(r1)
65 stw r0,SL_CR(r1)
66 stw r2,SL_R2(r1)
71 stw r4,SL_MSR(r1)
73 stw r4,SL_SDR1(r1)
77 stw r4,SL_TB(r1)
79 stw r5,SL_TB+4(r1)
86 stw r4,SL_SPRG0(r1)
88 stw r4,SL_SPRG0+4(r1)
90 stw r4,SL_SPRG0+8(r1)
[all …]
/arch/powerpc/platforms/52xx/
Dmpc52xx_sleep.S23 stw r8, 0x14(r6)
28 stw r8, 0x40(r6) /* intr->main_emulate */
71 stw r8, 0x4(r4)
75 stw r8, 0x4(r4)
80 stw r8, 0x4(r4)
85 stw r8, 0x4(r4)
92 stw r8, 0x14(r5)
107 stw r8, 0x14(r5)
113 stw r8, 0x4(r4)
132 stw r8, 0(r7)
[all …]
Dlite5200_sleep.S24 stw r10, ((addr)*4)(r4);
52 stw r4, 0(r3)
65 stw r10, (0x1d*4)(r4)
83 stw r5, 0(r4)
112 stw r4, SDRAM_CTRL(r8)
116 stw r4, SDRAM_CTRL(r8)
121 stw r4, SDRAM_CTRL(r8)
134 stw r4, SDRAM_CTRL(r8)
145 stw r4, CDM_CE(r8)
244 stw r10, 0xf0(r3)
[all …]
/arch/sparc/kernel/
Dwinfixup.S71 1: stw %l0, [%g3 + TI_REG_WINDOW + 0x00]
72 stw %l1, [%g3 + TI_REG_WINDOW + 0x04]
73 stw %l2, [%g3 + TI_REG_WINDOW + 0x08]
74 stw %l3, [%g3 + TI_REG_WINDOW + 0x0c]
75 stw %l4, [%g3 + TI_REG_WINDOW + 0x10]
76 stw %l5, [%g3 + TI_REG_WINDOW + 0x14]
77 stw %l6, [%g3 + TI_REG_WINDOW + 0x18]
78 stw %l7, [%g3 + TI_REG_WINDOW + 0x1c]
79 stw %i0, [%g3 + TI_REG_WINDOW + 0x20]
80 stw %i1, [%g3 + TI_REG_WINDOW + 0x24]
[all …]
/arch/um/sys-ppc/
Dmisc.S43 1: stw r4, 0(r3)
44 stw r4, 4(r3)
45 stw r4, 8(r3)
46 stw r4, 12(r3)
65 stw r6,4(r3); \
66 stw r7,8(r3); \
67 stw r8,12(r3); \
/arch/parisc/kernel/
Dhpmc.S119 stw %r5,52(%r4)
160 stw %r4,-52(sp)
175 stw %r0,-52(sp) /* reserved */
201 stw %r4,-52(sp)
203 stw %r4,-56(sp)
205 stw %r4,-60(sp)
222 stw %r4, -52(sp)
223 stw %r0, -56(sp) /* HV */
224 stw %r0, -60(sp) /* HV */
225 stw %r0, -64(sp) /* HV */
[all …]
Dpacache.S364 stw %r19, 0(%r26)
365 stw %r20, 4(%r26)
366 stw %r21, 8(%r26)
367 stw %r22, 12(%r26)
372 stw %r19, 16(%r26)
373 stw %r20, 20(%r26)
374 stw %r21, 24(%r26)
375 stw %r22, 28(%r26)
380 stw %r19, 32(%r26)
381 stw %r20, 36(%r26)
[all …]
Dhead.S65 stw,ma %r0,4(%r3)
69 stw,ma %arg0,4(%r1)
70 stw,ma %arg1,4(%r1)
71 stw,ma %arg2,4(%r1)
72 stw,ma %arg3,4(%r1)
84 stw %r3,ASM_PGD_ENTRY*ASM_PGD_ENTRY_SIZE(%r4)
99 stw %r3,0(%r4)
140 stw %r10,0x10(%r0) /* MEM_RENDEZ */
141 stw %r0,0x28(%r0) /* MEM_RENDEZ_HI - assume addr < 4GB */
166 stw %r0,0x10(%r0) /* MEM_RENDEZ */
[all …]
/arch/sparc/lib/
Dcsum_copy.S106 EX_ST(STORE(stw, %o5, %o1 + 0x00))
109 EX_ST(STORE(stw, %g1, %o1 + 0x04))
112 EX_ST(STORE(stw, %g2, %o1 + 0x08))
115 EX_ST(STORE(stw, %o5, %o1 + 0x0c))
118 EX_ST(STORE(stw, %g1, %o1 + 0x10))
121 EX_ST(STORE(stw, %g2, %o1 + 0x14))
124 EX_ST(STORE(stw, %o5, %o1 + 0x18))
127 EX_ST(STORE(stw, %g1, %o1 + 0x1c))
130 EX_ST(STORE(stw, %g2, %o1 + 0x20))
133 EX_ST(STORE(stw, %o5, %o1 + 0x24))
[all …]
/arch/powerpc/platforms/cell/
Dbeat_hvCall.S40 stw r0,8(r1)
66 stw r0,8(r1)
93 stw r0,8(r1)
124 stw r0,8(r1)
156 stw r0,8(r1)
189 stw r0,8(r1)
223 stw r0,8(r1)
258 stw r0,8(r1)
/arch/parisc/include/asm/
Dassembly.h42 #define STREG stw
390 stw,ma %r3, CALLEE_REG_FRAME_SIZE(%r30)
392 stw %r4, -124(%r30)
393 stw %r5, -120(%r30)
394 stw %r6, -116(%r30)
395 stw %r7, -112(%r30)
396 stw %r8, -108(%r30)
397 stw %r9, -104(%r30)
398 stw %r10, -100(%r30)
399 stw %r11, -96(%r30)
[all …]
/arch/parisc/hpux/
Dgate.S86 stw %r21, -52(%r30) ;! 5th argument
87 stw %r20, -56(%r30) ;! 6th argument
88 stw %r19, -60(%r30) ;! 7th argument
89 stw %r29, -64(%r30) ;! 8th argument

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