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/arch/mips/include/asm/mach-cavium-octeon/
Dkernel-entry-init.h31 dmfc0 v0, CP0_CVMMEMCTL_REG
33 dins v0, $0, 0, 6
34 ori v0, CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE
35 dmtc0 v0, CP0_CVMMEMCTL_REG # Write the cavium mem control register
36 dmfc0 v0, CP0_CVMCTL_REG # Read the cavium control register
39 or v0, v0, 0x5001
40 xor v0, v0, 0x1001
43 or v0, v0, 0x5001
44 xor v0, v0, 0x5001
49 or v0, v0, 0x2000
[all …]
/arch/mips/lib/
Dstrnlen_user.S29 LONG_L v0, TI_ADDR_LIMIT($28) # pointer ok?
30 and v0, a0
31 bnez v0, .Lfault
34 move v0, a0
36 1: beq v0, a1, 1f # limit reached?
37 EX(lb, t0, (v0), .Lfault)
38 PTR_ADDU v0, 1
40 1: PTR_SUBU v0, a0
45 move v0, zero
Dstrlen_user.S25 LONG_L v0, TI_ADDR_LIMIT($28) # pointer ok?
26 and v0, a0
27 bnez v0, .Lfault
30 move v0, a0
31 1: EX(lb, t0, (v0), .Lfault)
32 PTR_ADDIU v0, 1
34 PTR_SUBU v0, a0
38 .Lfault: move v0, zero
Dstrncpy_user.S31 LONG_L v0, TI_ADDR_LIMIT($28) # pointer ok?
32 and v0, a1
33 bnez v0, .Lfault
36 move v0, zero
44 PTR_ADDIU v0, 1
47 bne v0, a2, 1b
48 2: PTR_ADDU t0, a1, v0
54 .Lfault: li v0, -EFAULT
/arch/ia64/include/asm/sn/
Dsn_sal.h185 ret_stuff.v0 = 0; in ia64_sn_get_console_nasid()
194 return ret_stuff.v0; in ia64_sn_get_console_nasid()
207 ret_stuff.v0 = 0; in ia64_sn_get_master_baseio_nasid()
216 return ret_stuff.v0; in ia64_sn_get_master_baseio_nasid()
225 ret_stuff.v0 = 0; in ia64_sn_get_klconfig_addr()
229 return ret_stuff.v0 ? __va(ret_stuff.v0) : NULL; in ia64_sn_get_klconfig_addr()
241 ret_stuff.v0 = 0; in ia64_sn_console_getc()
247 *ch = (int)ret_stuff.v0; in ia64_sn_console_getc()
263 ret_stuff.v0 = 0; in ia64_sn_console_readc()
269 return ret_stuff.v0; in ia64_sn_console_readc()
[all …]
/arch/mips/include/asm/mach-malta/
Dkernel-entry-init.h25 PTR_LA v0, 0x9fc00534 /* YAMON print */
26 lw v0, (v0)
29 jal v0
31 PTR_LA v0, 0x9fc00520 /* YAMON exit */
32 lw v0, (v0)
34 jal v0
/arch/alpha/lib/
Dstrlen_user.S23 lda v0, $exception-99b(zero); \
50 andnot a0, 7, v0
55 subq a0, v0, t0
63 EX( ldq t0, 8(v0) )
65 addq v0, 8, v0 # addr += 8
79 addq v0, t4, v0
80 addq v0, t2, v0
82 subq v0, a0, v0
88 subq a1, t2, v0
Dev67-strlen_user.S34 lda v0, $exception-99b(zero); \
64 andnot a0, 7, v0 # E :
70 subq a0, v0, t0 # E :
80 EX( ldq t0, 8(v0) ) # L :
86 addq v0, 8, v0 # E : addr += 8
90 addq v0, t2, v0 # E :
91 subq v0, a0, v0 # E :
104 subq a1, t2, v0
Dstrchr.S24 andnot a0, 7, v0 # .. e1 : align our loop pointer
40 $loop: ldq t0, 8(v0) # e0 :
41 addq v0, 8, v0 # .. e1 :
62 addq v0, t4, v0 # .. e1 :
63 addq v0, t2, v0 # e0 :
67 mov zero, v0 # e0 :
Dstrrchr.S28 andnot a0, 7, v0 # .. e1 : align source addr
44 ldq t0, 8(v0) # e0 : load next quadword
45 cmovne t3, v0, t6 # .. e1 : save previous comparisons match
47 addq v0, 8, v0 # .. e1 :
62 cmovne t3, v0, t6 # e0 :
79 addq t6, t0, v0 # .. e1 : add our aligned base ptr to the mix
80 addq v0, t1, v0 # e0 :
84 mov zero, v0 # e0 :
Dev67-strchr.S38 andnot a0, 7, v0 # E : align our loop pointer
68 $loop: ldq t0, 8(v0) # L : Latency=3
69 addq v0, 8, v0 # E :
81 addq v0, a2, v0 # E : Add in the bit number from above
83 cmoveq t1, $31, v0 # E : Two mapping slots, latency = 2
Dev67-strrchr.S44 andnot a0, 7, v0 # E : align source addr
66 ldq t0, 8(v0) # L : load next quadword
67 cmovne t3, v0, t6 # E : save previous comparisons match
73 addq v0, 8, v0 # E :
93 cmovne t3, v0, t6 # E :
104 addq t6, t5, v0 # E : and add to quadword address
/arch/mips/include/asm/
Dstackframe.h278 LONG_L v0, PT_STATUS(sp)
280 and v0, v1
281 or v0, a0
282 mtc0 v0, CP0_STATUS
333 mfc0 v0, CP0_TCSTATUS
334 ori v0, TCSTATUS_IXMT
335 mtc0 v0, CP0_TCSTATUS
350 LONG_L v0, PT_STATUS(sp)
352 and v0, v1
353 or v0, a0
[all …]
Dregdef.h22 #define v0 $2 /* return value */ macro
61 #define v0 $2 /* return value - caller saved */ macro
/arch/mips/kernel/
Dscall32-o32.S37 subu v0, v0, __NR_O32_Linux # check syscall number
38 sltiu t0, v0, __NR_O32_Linux_syscalls + 1
43 sll t0, v0, 3
62 sltu t0, t0, v0
66 negu v0 # error
67 sw v0, PT_R0(sp) # set flag for syscall
69 1: sw v0, PT_R2(sp) # result
103 sltu t0, t0, v0
107 negu v0 # error
108 sw v0, PT_R0(sp) # set flag for syscall
[all …]
Dscall64-64.S42 dsubu t0, v0, __NR_64_Linux # check syscall number
51 dsll t0, v0, 3 # offset into table
65 sltu t0, t0, v0
69 dnegu v0 # error
70 sd v0, PT_R0(sp) # set flag for syscall
72 1: sd v0, PT_R2(sp) # result
108 sltu t0, t0, v0
112 dnegu v0 # error
113 sd v0, PT_R0(sp) # set flag for syscall restarting
114 1: sd v0, PT_R2(sp) # result
[all …]
Dentry.S84 mfc0 v0, CP0_TCSTATUS
85 ori v1, v0, TCSTATUS_IXMT
87 andi v0, TCSTATUS_IXMT
104 or v1, v0, v1
125 LONG_L v0, PT_STATUS(sp)
127 and v0, ST0_IEP
129 and v0, ST0_IE
131 beqz v0, 1f
Dscall64-o32.S36 dsubu t0, v0, __NR_O32_Linux # check syscall number
43 move a1, v0
55 dsll t0, v0, 3 # offset into table
92 sltu t0, t0, v0
96 dnegu v0 # error
97 sd v0, PT_R0(sp) # flag for syscall restarting
98 1: sd v0, PT_R2(sp) # result
141 sltu t0, t0, v0
145 dnegu v0 # error
146 sd v0, PT_R0(sp) # set flag for syscall restarting
[all …]
Dscall64-n32.S41 dsubu t0, v0, __NR_N32_Linux # check syscall number
51 dsll t0, v0, 3 # offset into table
64 sltu t0, t0, v0
68 dnegu v0 # error
69 sd v0, PT_R0(sp) # set flag for syscall restarting
70 1: sd v0, PT_R2(sp) # result
105 sltu t0, t0, v0
109 dnegu v0 # error
110 sd v0, PT_R0(sp) # set flag for syscall restarting
111 1: sd v0, PT_R2(sp) # result
/arch/ia64/include/asm/
Dpal.h780 u64 v0; member
888 features_avail->pal_bus_features_val = iprv.v0; in ia64_pal_bus_get_features()
915 conf->pcci_info_1.pcci1_data = iprv.v0; in ia64_pal_cache_config_info()
933 prot->pcp_info[0].pcpi_data = iprv.v0 & 0xffffffff; in ia64_pal_cache_prot_info()
934 prot->pcp_info[1].pcpi_data = iprv.v0 >> 32; in ia64_pal_cache_prot_info()
953 *vector = iprv.v0; in ia64_pal_cache_flush()
998 *cache_levels = iprv.v0; in ia64_pal_cache_summary()
1023 *buffer_size = iprv.v0; in ia64_pal_copy_info()
1036 *pal_proc_offset = iprv.v0; in ia64_pal_copy_pal()
1047 *inst_regs = iprv.v0; in ia64_pal_debug_info()
[all …]
/arch/ia64/kvm/
Dkvm_fw.c39 x.v0 = 0; \
47 x.v0 = 0; \
143 &result.v0); in pal_cache_flush()
181 if (result.v0 == 0) { in pal_freq_base()
183 &result.v0, in pal_freq_base()
224 result.status = ia64_pal_proc_get_features(&result.v0, &result.v1, in pal_proc_get_features()
256 vminfo1.pvi1_val = result.v0; in pal_vm_summary()
259 result.v0 = vminfo1.pvi1_val; in pal_vm_summary()
350 result.status = ia64_pal_vm_page_size(&result.v0, in kvm_pal_emul()
354 result.status = ia64_pal_rse_info(&result.v0, in kvm_pal_emul()
[all …]
/arch/ia64/sn/pci/pcibr/
Dpcibr_provider.c32 ret_stuff.v0 = 0; in sal_pcibr_slot_enable()
40 return (int)ret_stuff.v0; in sal_pcibr_slot_enable()
52 ret_stuff.v0 = 0; in sal_pcibr_slot_disable()
60 return (int)ret_stuff.v0; in sal_pcibr_slot_disable()
69 ret_stuff.v0 = 0; in sal_pcibr_error_interrupt()
77 return (int)ret_stuff.v0; in sal_pcibr_error_interrupt()
/arch/ia64/sn/kernel/
Dhuberror.c31 ret_stuff.v0 = 0; in hub_eint_handler()
39 if ((int)ret_stuff.v0) in hub_eint_handler()
50 if ((int)ret_stuff.v0) in hub_eint_handler()
Dio_init.c36 ret_stuff.v0 = 0; in sal_get_hubdev_info()
41 return ret_stuff.v0; in sal_get_hubdev_info()
51 ret_stuff.v0 = 0; in sal_get_pcibus_info()
56 return ret_stuff.v0; in sal_get_pcibus_info()
68 ret_stuff.v0 = 0; in sal_get_pcidev_info()
75 return ret_stuff.v0; in sal_get_pcidev_info()
/arch/x86/kernel/
Dbios_uv.c83 u64 v0, v1; in uv_bios_get_sn_info() local
87 (u64)(&v0), (u64)(&v1), 0, 0); in uv_bios_get_sn_info()
91 part.val = v0; in uv_bios_get_sn_info()

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