Searched refs:BIT_1 (Results 1 – 11 of 11) sorted by relevance
| /drivers/scsi/qla2xxx/ |
| D | qla_fw.h | 26 #define PDO_FORCE_ADISC BIT_1
38 #define PDF_HARD_ADDR BIT_1
404 #define CF_READ_DATA BIT_1
447 #define TMF_READ_DATA BIT_1
731 #define TCF_TARGET_RESET BIT_1
846 #define CSRX_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable. */
917 #define GPDX_DATA_INOUT (BIT_1|BIT_0)
925 #define GPEX_ENABLE (BIT_1|BIT_0)
1034 #define MDBS_ID_ACQUIRED BIT_1
1097 #define CS_VF_SET_QOS_OF_VPORTS BIT_1
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| D | qla_def.h | 55 #define BIT_1 0x2 macro
205 #define SRB_DMA_VALID BIT_1 /* Command sent to ISP */
228 #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */
246 #define NVR_SELECT BIT_1
433 #define MBX_DMA_OUT BIT_1
517 #define FO1_AE_ALL_LIP_RESET BIT_1
531 #define FO2_REV_LOOPBACK BIT_1
534 #define FO3_AE_RND_ERROR BIT_1
667 #define MBX_1 BIT_1
757 #define QLA_ZIO_MODE_6 (BIT_2 | BIT_1)
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| D | qla_init.c | 1091 swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0); in qla2x00_update_fw_options()
1095 (BIT_3 | BIT_2 | BIT_1 | BIT_0); in qla2x00_update_fw_options()
1105 ((rx_sens & (BIT_1 | BIT_0)) << 2) | in qla2x00_update_fw_options()
1106 (tx_sens & (BIT_1 | BIT_0)); in qla2x00_update_fw_options()
1111 emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0); in qla2x00_update_fw_options()
1113 (BIT_3 | BIT_2 | BIT_1 | BIT_0); in qla2x00_update_fw_options()
1123 ((rx_sens & (BIT_1 | BIT_0)) << 2) | in qla2x00_update_fw_options()
1124 (tx_sens & (BIT_1 | BIT_0)); in qla2x00_update_fw_options()
1318 mid_init_cb->options = __constant_cpu_to_le16(BIT_1); in qla2x00_init_rings()
1696 nv->firmware_options[0] = BIT_2 | BIT_1; in qla2x00_nvram_config()
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| D | qla_mbx.c | 1365 mcp->mb[1] = BIT_1; in qla2x00_lip_reset()
1491 if (opt & BIT_1) in qla24xx_login_fabric()
1549 mb[1] |= BIT_1; in qla24xx_login_fabric()
1558 mb[10] |= BIT_1; /* Class 3. */ in qla24xx_login_fabric()
2653 mcp->mb[3] = port_speed & (BIT_2|BIT_1|BIT_0); in qla2x00_set_idma_speed()
2935 rval = BIT_1; in qla2x00_send_change_request()
2938 rval = BIT_1; in qla2x00_send_change_request()
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| D | qla_mid.c | 740 options |= BIT_1; in qla25xx_create_queues()
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| D | qla_gs.c | 544 ct_req->req.rff_id.fc4_feature = BIT_1; in qla2x00_rff_id()
1110 mb, BIT_1); in qla2x00_mgmt_svr_login()
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| D | qla_dbg.c | 675 (RD_REG_WORD(®->mctr) & (BIT_1 | BIT_0)) != 0))) { in qla2100_fw_dump()
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| D | qla_os.c | 326 lspeed = pcie_lstat & (BIT_0 | BIT_1 | BIT_2 | BIT_3); in qla24xx_pci_info_str()
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| /drivers/scsi/ |
| D | qla1280.h | 27 #define BIT_1 0x2 macro
129 #define ISP_CFG0_1020A BIT_1 /* ISP1020A */
143 #define ISP_EN_INT BIT_1 /* ISP enable interrupts. */
150 #define PCI_INT BIT_1 /* PCI interrupt */
155 #define NV_SELECT BIT_1
167 #define CDMA_CONF_BENAB BIT_1 /* Bus burst enable */
184 #define DDMA_CONF_BENAB BIT_1 /* Bus burst enable */
574 #define RF_FULL BIT_1 /* Full */
972 #define OF_ENABLE_TAG BIT_1 /* Tagged queue action enable */
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| D | qla1280.c | 1154 mr = BIT_3 | BIT_2 | BIT_1 | BIT_0; in qla1280_set_target_parameters()
1665 err = qla1280_mailbox_command(ha, BIT_0 | BIT_1 | BIT_2, mb); in qla1280_load_firmware_pio()
1728 BIT_1 | BIT_0, mb); in qla1280_load_firmware_dma()
1745 BIT_1 | BIT_0, mb); in qla1280_load_firmware_dma()
1790 err = qla1280_mailbox_command(ha, BIT_1 | BIT_0, mb); in qla1280_start_firmware()
1800 err = qla1280_mailbox_command(ha, BIT_1 | BIT_0, &mb[0]); in qla1280_start_firmware()
1866 BIT_3 | BIT_2 | BIT_1 | BIT_0, in qla1280_init_rings()
1880 BIT_3 | BIT_2 | BIT_1 | BIT_0, in qla1280_init_rings()
2100 status = qla1280_mailbox_command(ha, BIT_1 | BIT_0, &mb[0]); in qla1280_config_bus()
2174 BIT_7 | BIT_3 | BIT_2 | BIT_1 | BIT_0); in qla1280_nvram_config()
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| /drivers/scsi/qla4xxx/ |
| D | ql4_def.h | 56 #define BIT_1 0x2 macro
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