Searched refs:OP_WR_E1 (Results 1 – 2 of 2) sorted by relevance
| /drivers/net/ |
| D | bnx2x_init_values.h | 83 {OP_WR_E1, TSDM_REG_CFC_RSP_START_ADDR, 0x411},
85 {OP_WR_E1, TSDM_REG_CMP_COUNTER_START_ADDR, 0x400},
87 {OP_WR_E1, TSDM_REG_Q_COUNTER_START_ADDR, 0x404},
89 {OP_WR_E1, TSDM_REG_PCK_END_MSG_START_ADDR, 0x419},
117 {OP_WR_E1, TSDM_REG_INIT_CREDIT_PXP_CTRL, 0x1},
154 {OP_WR_E1, TCM_REG_PHYS_QNUM0_0, 0xd},
155 {OP_WR_E1, TCM_REG_PHYS_QNUM0_1, 0x2d},
156 {OP_WR_E1, TCM_REG_PHYS_QNUM1_0, 0x7},
157 {OP_WR_E1, TCM_REG_PHYS_QNUM1_1, 0x27},
158 {OP_WR_E1, TCM_REG_PHYS_QNUM2_0, 0x7},
[all …]
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| D | bnx2x_init.h | 47 #define OP_WR_E1 0xb /* write single register */ macro
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