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Searched refs:WRITE_REG (Results 1 – 12 of 12) sorted by relevance

/drivers/watchdog/
Dar7_wdt.c59 #define WRITE_REG(x, v) writel((v), (void __iomem *)&(x)) macro
100 WRITE_REG(ar7_wdt->kick_lock, 0x5555); in ar7_wdt_kick()
102 WRITE_REG(ar7_wdt->kick_lock, 0xaaaa); in ar7_wdt_kick()
104 WRITE_REG(ar7_wdt->kick, value); in ar7_wdt_kick()
113 WRITE_REG(ar7_wdt->prescale_lock, 0x5a5a); in ar7_wdt_prescale()
115 WRITE_REG(ar7_wdt->prescale_lock, 0xa5a5); in ar7_wdt_prescale()
117 WRITE_REG(ar7_wdt->prescale, value); in ar7_wdt_prescale()
126 WRITE_REG(ar7_wdt->change_lock, 0x6666); in ar7_wdt_change()
128 WRITE_REG(ar7_wdt->change_lock, 0xbbbb); in ar7_wdt_change()
130 WRITE_REG(ar7_wdt->change, value); in ar7_wdt_change()
[all …]
/drivers/net/
Dtehuti.c137 do { WRITE_REG(priv, regIMR, IR_RUN); } while (0)
139 do { WRITE_REG(priv, regIMR, 0); } while (0)
175 WRITE_REG(priv, reg_CFG0, (u32) ((f->da & TX_RX_CFG0_BASE) | fsz_type)); in bdx_fifo_init()
176 WRITE_REG(priv, reg_CFG1, H32_64(f->da)); in bdx_fifo_init()
335 WRITE_REG(priv, regINIT_SEMAPHORE, 1); in bdx_fw_load()
359 WRITE_REG(priv, regUNC_MAC2_A, val); in bdx_restore_mac()
361 WRITE_REG(priv, regUNC_MAC1_A, val); in bdx_restore_mac()
363 WRITE_REG(priv, regUNC_MAC0_A, val); in bdx_restore_mac()
383 WRITE_REG(priv, regFRM_LENGTH, 0X3FE0); in bdx_hw_start()
384 WRITE_REG(priv, regPAUSE_QUANT, 0x96); in bdx_hw_start()
[all …]
Dtehuti.h98 #define WRITE_REG(pp, reg, val) writel(val, pp->pBdxRegs + reg) macro
/drivers/staging/sxg/
Dsxg.c281 WRITE_REG(HwRegs->Reset, 0xDEAD, FLUSH); in sxg_download_microcode()
304 WRITE_REG(HwRegs->UcodeDataLow, *Instruction, FLUSH); in sxg_download_microcode()
306 WRITE_REG(HwRegs->UcodeDataMiddle, *(Instruction + 1), in sxg_download_microcode()
309 WRITE_REG(HwRegs->UcodeDataHigh, *(Instruction + 2), in sxg_download_microcode()
312 WRITE_REG(HwRegs->UcodeAddr, in sxg_download_microcode()
320 WRITE_REG(HwRegs->UcodeDataLow, *Instruction, TRUE); in sxg_download_microcode()
343 WRITE_REG(HwRegs->UcodeAddr, in sxg_download_microcode()
379 WRITE_REG(HwRegs->UcodeAddr, MICROCODE_ADDRESS_GO, FLUSH); in sxg_download_microcode()
400 WRITE_REG(adapter->UcodeRegs[0].LoadSync, 0, FLUSH); in sxg_download_microcode()
884 WRITE_REG(adapter->UcodeRegs[0].Icr, SXG_ICR(0, SXG_ICR_DISABLE), TRUE); in sxg_disable_interrupt()
[all …]
Dsxg_os.h143 #define WRITE_REG(reg,value,flush) sxg_reg32_write((&reg), (value), (flush)) macro
/drivers/staging/slicoss/
Dslicoss.c669 WRITE_REG(slic_regs->slic_icr, ICR_INT_OFF, FLUSH); in slic_entry_halt()
681 WRITE_REG(slic_regs->slic_reset_iface, 0, FLUSH); in slic_entry_halt()
1018 WRITE_REG(adapter->slic_regs->slic_cbar, in slic_xmit_start()
1270 WRITE_REG(adapter->slic_regs->slic_icr, ICR_INT_MASK, FLUSH); in slic_interrupt()
1362 WRITE_REG(adapter->slic_regs->slic_isr, 0, FLUSH); in slic_interrupt()
1652 WRITE_REG(slic_regs->slic_mcastlow, 0xFFFFFFFF, FLUSH); in slic_mcast_set_mask()
1653 WRITE_REG(slic_regs->slic_mcasthigh, 0xFFFFFFFF, FLUSH); in slic_mcast_set_mask()
1665 WRITE_REG(slic_regs->slic_mcastlow, in slic_mcast_set_mask()
1667 WRITE_REG(slic_regs->slic_mcasthigh, in slic_mcast_set_mask()
1807 WRITE_REG(slic_regs->slic_icr, ICR_INT_OFF, FLUSH); in slic_if_init()
[all …]
Dslic_os.h52 #define WRITE_REG(reg, value, flush) \ macro
77 #define WRITE_REG(reg, value, flush) \ macro
/drivers/parisc/
Dsba_iommu.c134 #define WRITE_REG(value, addr) WRITE_REG64(value, addr) macro
137 #define WRITE_REG(value, addr) WRITE_REG32(value, addr) macro
663 WRITE_REG( SBA_IOVA(ioc, iovp, 0, 0), ioc->ioc_hpa+IOC_PCOM); in sba_mark_invalid()
1304 WRITE_REG(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE); in sba_ioc_init_pluto()
1317 WRITE_REG(ioc->imask, ioc->ioc_hpa + IOC_IMASK); in sba_ioc_init_pluto()
1338 WRITE_REG(tcnfg, ioc->ioc_hpa + IOC_TCNFG); in sba_ioc_init_pluto()
1344 WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa + IOC_IBASE); in sba_ioc_init_pluto()
1350 WRITE_REG(ioc->ibase | 31, ioc->ioc_hpa + IOC_PCOM); in sba_ioc_init_pluto()
1466 WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa+IOC_IBASE); in sba_ioc_init()
1467 WRITE_REG(ioc->imask, ioc->ioc_hpa+IOC_IMASK); in sba_ioc_init()
[all …]
Dlba_pci.c894 WRITE_REG##size(val, astro_iop_base + addr); \
952 WRITE_REG##size(val, where); \
/drivers/ide/
Dopti621.c95 #define WRITE_REG 1 /* index of Write cycle timing register */ macro
186 write_reg(tim, WRITE_REG); in opti621_set_pio_mode()
/drivers/ata/
Dpata_opti.c40 WRITE_REG = 1, /* index of Write cycle timing register */ enumerator
144 opti_write_reg(ap, data_rec_timing[clock][pio], WRITE_REG); in opti_set_piomode()
Dpata_optidma.c39 WRITE_REG = 1, /* index of Write cycle timing register */ enumerator
170 iowrite8(data_rec_timing[pci_clock][pio], regio + WRITE_REG); in optidma_mode_setup()
173 iowrite8(dma_data_rec_timing[pci_clock][dma], regio + WRITE_REG); in optidma_mode_setup()