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Searched refs:csr (Results 1 – 25 of 87) sorted by relevance

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/drivers/ieee1394/
Dcsr.c115 host->csr.state &= 0x300; in host_reset()
117 host->csr.bus_manager_id = 0x3f; in host_reset()
118 host->csr.bandwidth_available = 4915; in host_reset()
119 host->csr.channels_available_hi = 0xfffffffe; /* pre-alloc ch 31 per 1394a-2000 */ in host_reset()
120 host->csr.channels_available_lo = ~0; in host_reset()
121 host->csr.broadcast_channel = 0x80000000 | 31; in host_reset()
129 host->csr.node_ids = host->node_id << 16; in host_reset()
133 host->csr.state &= ~0x100; in host_reset()
136 be32_add_cpu(&host->csr.topology_map[1], 1); in host_reset()
137 host->csr.topology_map[2] = cpu_to_be32(host->node_count << 16 in host_reset()
[all …]
Dcsr1212.c166 struct csr1212_csr *csr; in csr1212_create_csr() local
168 csr = CSR1212_MALLOC(sizeof(*csr)); in csr1212_create_csr()
169 if (!csr) in csr1212_create_csr()
172 csr->cache_head = in csr1212_create_csr()
175 if (!csr->cache_head) { in csr1212_create_csr()
176 CSR1212_FREE(csr); in csr1212_create_csr()
183 csr->root_kv = csr1212_new_directory(CSR1212_KV_ID_VENDOR); in csr1212_create_csr()
184 if (!csr->root_kv) { in csr1212_create_csr()
185 CSR1212_FREE(csr->cache_head); in csr1212_create_csr()
186 CSR1212_FREE(csr); in csr1212_create_csr()
[all …]
Dhosts.c37 u8 generation = host->csr.generation + 1; in delayed_reset_bus()
44 csr_set_bus_info_generation(host->csr.rom, generation); in delayed_reset_bus()
45 if (csr1212_generate_csr_image(host->csr.rom) != CSR1212_SUCCESS) { in delayed_reset_bus()
48 csr_set_bus_info_generation(host->csr.rom, in delayed_reset_bus()
49 host->csr.generation); in delayed_reset_bus()
53 host->csr.generation = generation; in delayed_reset_bus()
58 host->csr.rom->bus_info_data); in delayed_reset_bus()
60 host->csr.gen_timestamp[host->csr.generation] = jiffies; in delayed_reset_bus()
124 h->csr.rom = csr1212_create_csr(&csr_bus_ops, CSR_BUS_INFO_SIZE, h); in hpsb_alloc_host()
125 if (!h->csr.rom) in hpsb_alloc_host()
[all …]
Dconfig_roms.c46 root = host->csr.rom->root_kv; in hpsb_default_host_entry()
48 vend_id = csr1212_new_immediate(CSR1212_KV_ID_VENDOR, host->csr.guid_hi >> 8); in hpsb_default_host_entry()
56 csr1212_destroy_csr(host->csr.rom); in hpsb_default_host_entry()
65 csr1212_destroy_csr(host->csr.rom); in hpsb_default_host_entry()
139 if (csr1212_attach_keyval_to_directory(host->csr.rom->root_kv, in hpsb_config_rom_ip1394_add()
151 csr1212_detach_keyval_from_directory(host->csr.rom->root_kv, ip1394_ud); in hpsb_config_rom_ip1394_remove()
Dnodemgr.c88 static int nodemgr_bus_read(struct csr1212_csr *csr, u64 addr, in nodemgr_bus_read() argument
221 csr1212_destroy_csr(host->csr.rom); in nodemgr_release_host()
778 quadlet_t busoptions = be32_to_cpu(ne->csr->bus_info_data[2]); in nodemgr_update_bus_options()
802 struct csr1212_csr *csr, struct hpsb_host *host, in nodemgr_create_node() argument
818 ne->csr = csr; in nodemgr_create_node()
977 csr1212_for_each_dir_entry(ne->csr, kv, ud_kv, dentry) { in nodemgr_process_unit_directory()
1113 csr1212_for_each_dir_entry(ne->csr, kv, ne->csr->root_kv, dentry) { in nodemgr_process_root_directory()
1239 static void nodemgr_update_node(struct node_entry *ne, struct csr1212_csr *csr, in nodemgr_update_node() argument
1249 if (ne->busopt.generation != ((be32_to_cpu(csr->bus_info_data[2]) >> 4) & 0xf)) { in nodemgr_update_node()
1250 kfree(ne->csr->private); in nodemgr_update_node()
[all …]
Dcsr1212.h202 int (*bus_read) (struct csr1212_csr *csr, u64 addr,
259 extern void csr1212_init_local_csr(struct csr1212_csr *csr,
264 extern void csr1212_destroy_csr(struct csr1212_csr *csr);
297 extern int csr1212_generate_csr_image(struct csr1212_csr *csr);
302 extern int csr1212_read(struct csr1212_csr *csr, u32 offset, void *buffer,
311 extern int csr1212_parse_csr(struct csr1212_csr *csr);
342 csr1212_get_keyval(struct csr1212_csr *csr, struct csr1212_keyval *kv);
/drivers/usb/musb/
Dmusb_gadget.c258 u16 fifo_count = 0, csr; in txstate() local
270 csr = musb_readw(epio, MUSB_TXCSR); in txstate()
276 if (csr & MUSB_TXCSR_TXPKTRDY) { in txstate()
278 musb_ep->end_point.name, csr); in txstate()
282 if (csr & MUSB_TXCSR_P_SENDSTALL) { in txstate()
284 musb_ep->end_point.name, csr); in txstate()
290 csr); in txstate()
319 csr &= ~(MUSB_TXCSR_AUTOSET | in txstate()
321 csr |= (MUSB_TXCSR_DMAENAB | in txstate()
325 csr |= (MUSB_TXCSR_AUTOSET in txstate()
[all …]
Dmusb_host.c114 u16 csr; in musb_h_tx_flush_fifo() local
118 csr = musb_readw(epio, MUSB_TXCSR); in musb_h_tx_flush_fifo()
119 while (csr & MUSB_TXCSR_FIFONOTEMPTY) { in musb_h_tx_flush_fifo()
120 if (csr != lastcsr) in musb_h_tx_flush_fifo()
121 DBG(3, "Host TX FIFONOTEMPTY csr: %02x\n", csr); in musb_h_tx_flush_fifo()
122 lastcsr = csr; in musb_h_tx_flush_fifo()
123 csr |= MUSB_TXCSR_FLUSHFIFO; in musb_h_tx_flush_fifo()
124 musb_writew(epio, MUSB_TXCSR, csr); in musb_h_tx_flush_fifo()
125 csr = musb_readw(epio, MUSB_TXCSR); in musb_h_tx_flush_fifo()
128 ep->epnum, csr)) in musb_h_tx_flush_fifo()
[all …]
Dmusb_gadget_ep0.c373 u16 csr; in service_zero_data_request() local
393 csr = musb_readw(regs, in service_zero_data_request()
395 if (csr & MUSB_TXCSR_FIFONOTEMPTY) in service_zero_data_request()
396 csr |= MUSB_TXCSR_FLUSHFIFO; in service_zero_data_request()
397 csr |= MUSB_TXCSR_P_SENDSTALL in service_zero_data_request()
401 csr); in service_zero_data_request()
403 csr = musb_readw(regs, in service_zero_data_request()
405 csr |= MUSB_RXCSR_P_SENDSTALL in service_zero_data_request()
410 csr); in service_zero_data_request()
440 u16 count, csr; in ep0_rxstate() local
[all …]
Dmusbhsdma.c126 u16 csr = 0; in configure_channel() local
132 csr |= 1 << MUSB_HSDMA_MODE1_SHIFT; in configure_channel()
136 csr |= MUSB_HSDMA_BURSTMODE_INCR16 in configure_channel()
139 csr |= MUSB_HSDMA_BURSTMODE_INCR8 in configure_channel()
142 csr |= MUSB_HSDMA_BURSTMODE_INCR4 in configure_channel()
147 csr |= (musb_channel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT) in configure_channel()
161 csr); in configure_channel()
198 u16 csr; in dma_channel_abort() local
203 csr = musb_readw(mbase, in dma_channel_abort()
206 csr &= ~(MUSB_TXCSR_AUTOSET | in dma_channel_abort()
[all …]
Dtusb6010_omap.c205 u16 csr; in tusb_omap_dma_cb() local
210 csr = musb_readw(hw_ep->regs, MUSB_TXCSR); in tusb_omap_dma_cb()
211 csr |= MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY in tusb_omap_dma_cb()
213 musb_writew(hw_ep->regs, MUSB_TXCSR, csr); in tusb_omap_dma_cb()
233 u16 csr; in tusb_omap_dma_program() local
382 csr = musb_readw(hw_ep->regs, MUSB_TXCSR); in tusb_omap_dma_program()
383 csr |= (MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB in tusb_omap_dma_program()
385 csr &= ~MUSB_TXCSR_P_UNDERRUN; in tusb_omap_dma_program()
386 musb_writew(hw_ep->regs, MUSB_TXCSR, csr); in tusb_omap_dma_program()
389 csr = musb_readw(hw_ep->regs, MUSB_RXCSR); in tusb_omap_dma_program()
[all …]
Dcppi_dma.c1094 int csr; in cppi_rx_scan() local
1108 csr = musb_readw(regs, MUSB_RXCSR); in cppi_rx_scan()
1109 if (csr & MUSB_RXCSR_DMAENAB) { in cppi_rx_scan()
1117 csr); in cppi_rx_scan()
1122 int csr; in cppi_rx_scan() local
1129 csr = musb_readw(rx->hw_ep->regs, MUSB_RXCSR); in cppi_rx_scan()
1132 && !(csr & MUSB_RXCSR_H_REQPKT)) { in cppi_rx_scan()
1133 csr |= MUSB_RXCSR_H_REQPKT; in cppi_rx_scan()
1135 MUSB_RXCSR_H_WZC_BITS | csr); in cppi_rx_scan()
1136 csr = musb_readw(rx->hw_ep->regs, MUSB_RXCSR); in cppi_rx_scan()
[all …]
/drivers/scsi/
Dsun3_scsi_vme.c196 oldcsr = dregs->csr; in sun3scsi_detect()
197 dregs->csr = 0; in sun3scsi_detect()
199 if(dregs->csr == 0x1400) in sun3scsi_detect()
202 dregs->csr = oldcsr; in sun3scsi_detect()
257 dregs->csr = 0; in sun3scsi_detect()
259 dregs->csr = CSR_SCSI | CSR_FIFO | CSR_INTR; in sun3scsi_detect()
344 unsigned short csr = dregs->csr; in scsi_sun3_intr() local
347 dregs->csr &= ~CSR_DMA_ENABLE; in scsi_sun3_intr()
351 printk("scsi_intr csr %x\n", csr); in scsi_sun3_intr()
354 if(csr & ~CSR_GOOD) { in scsi_sun3_intr()
[all …]
Dsun3_scsi.c295 dregs->csr = 0; in sun3scsi_detect()
297 dregs->csr = CSR_SCSI | CSR_FIFO | CSR_INTR; in sun3scsi_detect()
375 unsigned short csr = dregs->csr; in scsi_sun3_intr() local
378 if(csr & ~CSR_GOOD) { in scsi_sun3_intr()
379 if(csr & CSR_DMA_BUSERR) { in scsi_sun3_intr()
383 if(csr & CSR_DMA_CONFLICT) { in scsi_sun3_intr()
389 if(csr & (CSR_SDB_INT | CSR_DMA_INT)) { in scsi_sun3_intr()
444 dregs->csr &= ~CSR_FIFO; in sun3scsi_dma_setup()
445 dregs->csr |= CSR_FIFO; in sun3scsi_dma_setup()
449 dregs->csr |= CSR_SEND; in sun3scsi_dma_setup()
[all …]
Dsun3x_esp.c108 u32 csr; in sun3x_esp_dma_drain() local
111 csr = dma_read32(DMA_CSR); in sun3x_esp_dma_drain()
112 if (!(csr & DMA_FIFO_ISDRAIN)) in sun3x_esp_dma_drain()
115 dma_write32(csr | DMA_FIFO_STDRAIN, DMA_CSR); in sun3x_esp_dma_drain()
153 u32 csr; in sun3x_esp_send_dma_cmd() local
159 csr = dma_read32(DMA_CSR); in sun3x_esp_send_dma_cmd()
160 csr |= DMA_ENABLE; in sun3x_esp_send_dma_cmd()
162 csr |= DMA_ST_WRITE; in sun3x_esp_send_dma_cmd()
164 csr &= ~DMA_ST_WRITE; in sun3x_esp_send_dma_cmd()
165 dma_write32(csr, DMA_CSR); in sun3x_esp_send_dma_cmd()
[all …]
Dsun_esp.c356 u32 csr; in sbus_esp_dma_drain() local
362 csr = dma_read32(DMA_CSR); in sbus_esp_dma_drain()
363 if (!(csr & DMA_FIFO_ISDRAIN)) in sbus_esp_dma_drain()
367 dma_write32(csr | DMA_FIFO_STDRAIN, DMA_CSR); in sbus_esp_dma_drain()
422 u32 csr; in sbus_esp_send_dma_cmd() local
434 csr = esp->prev_hme_dmacsr; in sbus_esp_send_dma_cmd()
435 csr |= DMA_SCSI_DISAB | DMA_ENABLE; in sbus_esp_send_dma_cmd()
437 csr |= DMA_ST_WRITE; in sbus_esp_send_dma_cmd()
439 csr &= ~DMA_ST_WRITE; in sbus_esp_send_dma_cmd()
440 esp->prev_hme_dmacsr = csr; in sbus_esp_send_dma_cmd()
[all …]
/drivers/usb/gadget/
Dat91_udc.c102 u32 csr; in proc_ep_show() local
108 csr = __raw_readl(ep->creg); in proc_ep_show()
122 csr, in proc_ep_show()
123 (csr & 0x07ff0000) >> 16, in proc_ep_show()
124 (csr & (1 << 15)) ? "enabled" : "disabled", in proc_ep_show()
125 (csr & (1 << 11)) ? "DATA1" : "DATA0", in proc_ep_show()
126 types[(csr & 0x700) >> 8], in proc_ep_show()
129 (!(csr & 0x700)) in proc_ep_show()
130 ? ((csr & (1 << 7)) ? " IN" : " OUT") in proc_ep_show()
132 (csr & (1 << 6)) ? " rxdatabk1" : "", in proc_ep_show()
[all …]
Dlh7a40x_udc.c349 u32 csr; in udc_enable() local
372 csr = usb_read(ep_reg->csr1); in udc_enable()
373 usb_write(csr, ep_reg->csr1); in udc_enable()
497 u32 csr; in write_fifo() local
501 csr = usb_read(ep->csr1); in write_fifo()
502 DEBUG("CSR: %x %d\n", csr, csr & USB_IN_CSR1_FIFO_NOT_EMPTY); in write_fifo()
504 if (!(csr & USB_IN_CSR1_FIFO_NOT_EMPTY)) { in write_fifo()
550 u32 csr; in read_fifo() local
556 csr = usb_read(ep->csr1); in read_fifo()
557 if (!(csr & USB_OUT_CSR1_OUT_PKT_RDY)) { in read_fifo()
[all …]
/drivers/watchdog/
Dshwdt.c89 __u8 csr; in sh_wdt_start() local
97 csr = sh_wdt_read_csr(); in sh_wdt_start()
98 csr |= WTCSR_WT | clock_division_ratio; in sh_wdt_start()
99 sh_wdt_write_csr(csr); in sh_wdt_start()
111 csr = sh_wdt_read_csr(); in sh_wdt_start()
112 csr |= WTCSR_TME; in sh_wdt_start()
113 csr &= ~WTCSR_RSTS; in sh_wdt_start()
114 sh_wdt_write_csr(csr); in sh_wdt_start()
126 csr = sh_wdt_read_rstcsr(); in sh_wdt_start()
127 csr &= ~RSTCSR_RSTS; in sh_wdt_start()
[all …]
/drivers/media/video/
Domap24xxcam-dma.c43 u32 csr; in omap24xxcam_dmahw_ack_all() local
47 csr = omap24xxcam_reg_in(base, CAMDMA_CSR(i)); in omap24xxcam_dmahw_ack_all()
49 omap24xxcam_reg_out(base, CAMDMA_CSR(i), csr); in omap24xxcam_dmahw_ack_all()
57 u32 csr; in omap24xxcam_dmahw_ack_ch() local
59 csr = omap24xxcam_reg_in(base, CAMDMA_CSR(dmach)); in omap24xxcam_dmahw_ack_ch()
61 omap24xxcam_reg_out(base, CAMDMA_CSR(dmach), csr); in omap24xxcam_dmahw_ack_ch()
65 return csr; in omap24xxcam_dmahw_ack_ch()
244 static void omap24xxcam_dma_abort(struct omap24xxcam_dma *dma, u32 csr) in omap24xxcam_dma_abort() argument
276 (*callback) (dma, csr, arg); in omap24xxcam_dma_abort()
290 static void omap24xxcam_dma_stop(struct omap24xxcam_dma *dma, u32 csr) in omap24xxcam_dma_stop() argument
[all …]
/drivers/pcmcia/
Dpxa2xx_sharpsl.c90 unsigned short cpr, csr; in sharpsl_pcmcia_socket_state() local
98 csr = read_scoop_reg(scoop, SCOOP_CSR); in sharpsl_pcmcia_socket_state()
99 if (csr & 0x0004) { in sharpsl_pcmcia_socket_state()
107 csr |= SCOOP_DEV[skt->nr].keep_vs; in sharpsl_pcmcia_socket_state()
112 SCOOP_DEV[skt->nr].keep_vs = (csr & 0x00C0); in sharpsl_pcmcia_socket_state()
123 state->detect = (csr & 0x0004) ? 0 : 1; in sharpsl_pcmcia_socket_state()
124 state->ready = (csr & 0x0002) ? 1 : 0; in sharpsl_pcmcia_socket_state()
125 state->bvd1 = (csr & 0x0010) ? 1 : 0; in sharpsl_pcmcia_socket_state()
126 state->bvd2 = (csr & 0x0020) ? 1 : 0; in sharpsl_pcmcia_socket_state()
127 state->wrprot = (csr & 0x0008) ? 1 : 0; in sharpsl_pcmcia_socket_state()
[all …]
/drivers/net/
Dewrk3.c246 csr = inb(EWRK3_CSR);\
247 csr &= ~(CSR_TXD|CSR_RXD);\
248 outb(csr, EWRK3_CSR); /* Enable the TX and/or RX */\
252 csr = (CSR_TXD|CSR_RXD);\
253 outb(csr, EWRK3_CSR); /* Disable the TX and/or RX */\
629 u_char icr, csr; in ewrk3_open() local
686 u_char csr, page; in ewrk3_init() local
727 u_char icr, csr; in ewrk3_timeout() local
880 u_char icr, cr, csr; in ewrk3_interrupt() local
886 csr = inb(EWRK3_CSR); in ewrk3_interrupt()
[all …]
/drivers/staging/et131x/
Det1310_rx.c834 RXDMA_CSR_t csr; in et131x_rx_dma_disable() local
839 writel(0x00002001, &pAdapter->CSRAddress->rxdma.csr.value); in et131x_rx_dma_disable()
840 csr.value = readl(&pAdapter->CSRAddress->rxdma.csr.value); in et131x_rx_dma_disable()
841 if (csr.bits.halt_status != 1) { in et131x_rx_dma_disable()
843 csr.value = readl(&pAdapter->CSRAddress->rxdma.csr.value); in et131x_rx_dma_disable()
844 if (csr.bits.halt_status != 1) { in et131x_rx_dma_disable()
847 csr.value); in et131x_rx_dma_disable()
864 writel(0x1, &pAdapter->CSRAddress->rxdma.csr.value); in et131x_rx_dma_enable()
867 RXDMA_CSR_t csr = { 0 }; in et131x_rx_dma_enable() local
869 csr.bits.fbr1_enable = 1; in et131x_rx_dma_enable()
[all …]
/drivers/mtd/devices/
Dms02-nv.c200 mp->resource.csr = csr_res; in ms02nv_init_one()
267 release_resource(mp->resource.csr); in ms02nv_remove_one()
268 kfree(mp->resource.csr); in ms02nv_remove_one()
282 volatile u32 *csr; in ms02nv_init() local
289 csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR); in ms02nv_init()
290 if (*csr & KN02_CSR_BNK32M) in ms02nv_init()
295 csr = (volatile u32 *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_MCR); in ms02nv_init()
296 if (*csr & KN03_MCR_BNK32M) in ms02nv_init()
/drivers/net/wireless/rt2x00/
Drt2x00pci.h53 *value = readl(rt2x00dev->csr.base + offset); in rt2x00pci_register_read()
61 memcpy_fromio(value, rt2x00dev->csr.base + offset, length); in rt2x00pci_register_multiread()
68 writel(value, rt2x00dev->csr.base + offset); in rt2x00pci_register_write()
76 memcpy_toio(rt2x00dev->csr.base + offset, value, length); in rt2x00pci_register_multiwrite()

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