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Searched refs:divider (Results 1 – 11 of 11) sorted by relevance

/drivers/video/aty/
Dmach64_gx.c505 short divider = 0, tempA; in aty_var_to_pll_1703() local
522 divider = 0; in aty_var_to_pll_1703()
525 divider += 0x20; in aty_var_to_pll_1703()
543 divider &= ~0x1f; in aty_var_to_pll_1703()
544 divider |= tempA; in aty_var_to_pll_1703()
545 divider = in aty_var_to_pll_1703()
546 (divider & 0x00ff) + in aty_var_to_pll_1703()
554 program_bits = divider; in aty_var_to_pll_1703()
559 pll->ics2595.post_divider = divider; /* fuer nix */ in aty_var_to_pll_1703()
745 short divider = 0, tempA; in aty_var_to_pll_408() local
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Dmach64_ct.c122 u32 multiplier, divider, ras_multiplier, ras_divider, tmp; in aty_dsp_gt() local
127 divider = ((u32)pll->vclk_fb_div) * pll->xclk_ref_div; in aty_dsp_gt()
133 divider = divider * (bpp >> 2); in aty_dsp_gt()
145 divider = divider * pll->xres & ~7; in aty_dsp_gt()
153 while (((multiplier | divider) & 1) == 0) { in aty_dsp_gt()
155 divider = divider >> 1; in aty_dsp_gt()
159 tmp = ((multiplier * pll->fifo_size) << vshift) / divider; in aty_dsp_gt()
172 dsp_off = ((multiplier * (pll->fifo_size - 1)) << vshift) / divider - in aty_dsp_gt()
179 dsp_on = ((multiplier << vshift) + divider) / divider; in aty_dsp_gt()
191 dsp_on = dsp_off - (multiplier << vshift) / divider; in aty_dsp_gt()
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Dradeon_base.c1421 int divider; in radeon_calc_pll_regs() member
1492 for (post_div = &post_divs[0]; post_div->divider; ++post_div) { in radeon_calc_pll_regs()
1493 pll_output_freq = post_div->divider * freq; in radeon_calc_pll_regs()
1497 if (uses_dvo && (post_div->divider & 1)) in radeon_calc_pll_regs()
1506 if ( !post_div->divider ) { in radeon_calc_pll_regs()
1508 pll_output_freq = post_div->divider * freq; in radeon_calc_pll_regs()
1516 if ( !post_div->divider ) { in radeon_calc_pll_regs()
1518 pll_output_freq = post_div->divider * freq; in radeon_calc_pll_regs()
/drivers/mfd/
Dsm501.c399 int divider; member
418 int divider; in sm501_calc_clock() local
425 for (divider = 1; divider <= max_div; divider += 2) { in sm501_calc_clock()
429 diff = sm501fb_round_div(mclk, divider << shift) - freq; in sm501_calc_clock()
438 clock->divider = divider; in sm501_calc_clock()
483 return clock->mclk / (clock->divider << clock->shift); in sm501_calc_pll()
506 return clock->mclk / (clock->divider << clock->shift); in sm501_select_clock()
544 if (to.divider == 3) in sm501_set_clock()
546 else if (to.divider == 5) in sm501_set_clock()
554 if (to.divider == 3) in sm501_set_clock()
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/drivers/mmc/host/
Dmxcmmc.c557 unsigned int divider; in mxcmci_set_clk_rate() local
562 for (divider = 1; divider <= 0xF; divider++) { in mxcmci_set_clk_rate()
565 x = (clk_in / (divider + 1)); in mxcmci_set_clk_rate()
573 if (divider < 0x10) in mxcmci_set_clk_rate()
582 writew((prescaler << 4) | divider, host->base + MMC_REG_CLK_RATE); in mxcmci_set_clk_rate()
585 prescaler, divider, clk_in, clk_ios); in mxcmci_set_clk_rate()
/drivers/video/matrox/
Dmatroxfb_misc.c191 unsigned int divider; in matroxfb_vgaHWinit() local
243 divider = ACCESS_FBINFO(curr.final_bppShift); in matroxfb_vgaHWinit()
244 while (divider & 3) { in matroxfb_vgaHWinit()
249 divider <<= 1; in matroxfb_vgaHWinit()
251 divider = divider / 4; in matroxfb_vgaHWinit()
253 while (divider > 8) { in matroxfb_vgaHWinit()
258 divider >>= 1; in matroxfb_vgaHWinit()
297 hw->CRTCEXT[3] = (divider - 1) | 0x80; in matroxfb_vgaHWinit()
/drivers/net/wan/
Ddscc4.c1264 u32 n = 0, m = 0, divider; in dscc4_set_clock() local
1272 divider = xtal / *bps; in dscc4_set_clock()
1273 if (divider > BRR_DIVIDER_MAX) { in dscc4_set_clock()
1274 divider >>= 4; in dscc4_set_clock()
1278 if (divider >> 22) { in dscc4_set_clock()
1281 } else if (divider) { in dscc4_set_clock()
1284 while (0xffffffc0 & divider) { in dscc4_set_clock()
1286 divider >>= 1; in dscc4_set_clock()
1288 n = divider; in dscc4_set_clock()
1291 divider = n << m; in dscc4_set_clock()
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/drivers/video/
Dau1200fb.c657 unsigned int hi1, divider; in set_brightness() local
663 divider = (lcd->pwmdiv & 0x3FFFF) + 1; in set_brightness()
665 hi1 = (((brightness & 0xFF) + 1) * divider >> 8); in set_brightness()
1285 unsigned int hi1, divider; in set_global() local
1298 divider = (lcd->pwmdiv & 0x3FFFF) + 1; in set_global()
1300 hi1 = (((pdata->brightness & 0xFF)+1) * divider >> 8); in set_global()
1315 unsigned int hi1, divider; in get_global() local
1326 divider = (lcd->pwmdiv & 0x3FFFF) + 1; in get_global()
1327 pdata->brightness = ((hi1 << 8) / divider) - 1; in get_global()
Dw100fb.c1419 unsigned long rot=0, divider, offset=0; in w100_set_dispregs() local
1428 divider = par->mode->pixclk_divider; in w100_set_dispregs()
1437 divider = par->mode->pixclk_divider_rotated; in w100_set_dispregs()
1496 w100_pwr_state.pclk_cntl.f.pclk_post_div = divider; in w100_set_dispregs()
/drivers/staging/comedi/drivers/
Drtd520.c2098 int divider; in rtd_ns_to_timer_base() local
2103 divider = (*nanosec + base / 2) / base; in rtd_ns_to_timer_base()
2106 divider = (*nanosec) / base; in rtd_ns_to_timer_base()
2109 divider = (*nanosec + base - 1) / base; in rtd_ns_to_timer_base()
2112 if (divider < 2) in rtd_ns_to_timer_base()
2113 divider = 2; /* min is divide by 2 */ in rtd_ns_to_timer_base()
2118 *nanosec = base * divider; in rtd_ns_to_timer_base()
2119 return divider - 1; /* countdown is divisor+1 */ in rtd_ns_to_timer_base()
Ds626.c2011 int divider, base; in s626_ns_to_timer() local
2018 divider = (*nanosec + base / 2) / base; in s626_ns_to_timer()
2021 divider = (*nanosec) / base; in s626_ns_to_timer()
2024 divider = (*nanosec + base - 1) / base; in s626_ns_to_timer()
2028 *nanosec = base * divider; in s626_ns_to_timer()
2029 return divider - 1; in s626_ns_to_timer()