1 /*
2 * drivers/net/wan/dscc4/dscc4.c: a DSCC4 HDLC driver for Linux
3 *
4 * This software may be used and distributed according to the terms of the
5 * GNU General Public License.
6 *
7 * The author may be reached as romieu@cogenit.fr.
8 * Specific bug reports/asian food will be welcome.
9 *
10 * Special thanks to the nice people at CS-Telecom for the hardware and the
11 * access to the test/measure tools.
12 *
13 *
14 * Theory of Operation
15 *
16 * I. Board Compatibility
17 *
18 * This device driver is designed for the Siemens PEB20534 4 ports serial
19 * controller as found on Etinc PCISYNC cards. The documentation for the
20 * chipset is available at http://www.infineon.com:
21 * - Data Sheet "DSCC4, DMA Supported Serial Communication Controller with
22 * 4 Channels, PEB 20534 Version 2.1, PEF 20534 Version 2.1";
23 * - Application Hint "Management of DSCC4 on-chip FIFO resources".
24 * - Errata sheet DS5 (courtesy of Michael Skerritt).
25 * Jens David has built an adapter based on the same chipset. Take a look
26 * at http://www.afthd.tu-darmstadt.de/~dg1kjd/pciscc4 for a specific
27 * driver.
28 * Sample code (2 revisions) is available at Infineon.
29 *
30 * II. Board-specific settings
31 *
32 * Pcisync can transmit some clock signal to the outside world on the
33 * *first two* ports provided you put a quartz and a line driver on it and
34 * remove the jumpers. The operation is described on Etinc web site. If you
35 * go DCE on these ports, don't forget to use an adequate cable.
36 *
37 * Sharing of the PCI interrupt line for this board is possible.
38 *
39 * III. Driver operation
40 *
41 * The rx/tx operations are based on a linked list of descriptors. The driver
42 * doesn't use HOLD mode any more. HOLD mode is definitely buggy and the more
43 * I tried to fix it, the more it started to look like (convoluted) software
44 * mutation of LxDA method. Errata sheet DS5 suggests to use LxDA: consider
45 * this a rfc2119 MUST.
46 *
47 * Tx direction
48 * When the tx ring is full, the xmit routine issues a call to netdev_stop.
49 * The device is supposed to be enabled again during an ALLS irq (we could
50 * use HI but as it's easy to lose events, it's fscked).
51 *
52 * Rx direction
53 * The received frames aren't supposed to span over multiple receiving areas.
54 * I may implement it some day but it isn't the highest ranked item.
55 *
56 * IV. Notes
57 * The current error (XDU, RFO) recovery code is untested.
58 * So far, RDO takes his RX channel down and the right sequence to enable it
59 * again is still a mistery. If RDO happens, plan a reboot. More details
60 * in the code (NB: as this happens, TX still works).
61 * Don't mess the cables during operation, especially on DTE ports. I don't
62 * suggest it for DCE either but at least one can get some messages instead
63 * of a complete instant freeze.
64 * Tests are done on Rev. 20 of the silicium. The RDO handling changes with
65 * the documentation/chipset releases.
66 *
67 * TODO:
68 * - test X25.
69 * - use polling at high irq/s,
70 * - performance analysis,
71 * - endianness.
72 *
73 * 2001/12/10 Daniela Squassoni <daniela@cyclades.com>
74 * - Contribution to support the new generic HDLC layer.
75 *
76 * 2002/01 Ueimor
77 * - old style interface removal
78 * - dscc4_release_ring fix (related to DMA mapping)
79 * - hard_start_xmit fix (hint: TxSizeMax)
80 * - misc crapectomy.
81 */
82
83 #include <linux/module.h>
84 #include <linux/types.h>
85 #include <linux/errno.h>
86 #include <linux/list.h>
87 #include <linux/ioport.h>
88 #include <linux/pci.h>
89 #include <linux/kernel.h>
90 #include <linux/mm.h>
91
92 #include <asm/system.h>
93 #include <asm/cache.h>
94 #include <asm/byteorder.h>
95 #include <asm/uaccess.h>
96 #include <asm/io.h>
97 #include <asm/irq.h>
98
99 #include <linux/init.h>
100 #include <linux/string.h>
101
102 #include <linux/if_arp.h>
103 #include <linux/netdevice.h>
104 #include <linux/skbuff.h>
105 #include <linux/delay.h>
106 #include <linux/hdlc.h>
107 #include <linux/mutex.h>
108
109 /* Version */
110 static const char version[] = "$Id: dscc4.c,v 1.173 2003/09/20 23:55:34 romieu Exp $ for Linux\n";
111 static int debug;
112 static int quartz;
113
114 #ifdef CONFIG_DSCC4_PCI_RST
115 static DEFINE_MUTEX(dscc4_mutex);
116 static u32 dscc4_pci_config_store[16];
117 #endif
118
119 #define DRV_NAME "dscc4"
120
121 #undef DSCC4_POLLING
122
123 /* Module parameters */
124
125 MODULE_AUTHOR("Maintainer: Francois Romieu <romieu@cogenit.fr>");
126 MODULE_DESCRIPTION("Siemens PEB20534 PCI Controler");
127 MODULE_LICENSE("GPL");
128 module_param(debug, int, 0);
129 MODULE_PARM_DESC(debug,"Enable/disable extra messages");
130 module_param(quartz, int, 0);
131 MODULE_PARM_DESC(quartz,"If present, on-board quartz frequency (Hz)");
132
133 /* Structures */
134
135 struct thingie {
136 int define;
137 u32 bits;
138 };
139
140 struct TxFD {
141 __le32 state;
142 __le32 next;
143 __le32 data;
144 __le32 complete;
145 u32 jiffies; /* Allows sizeof(TxFD) == sizeof(RxFD) + extra hack */
146 /* FWIW, datasheet calls that "dummy" and says that card
147 * never looks at it; neither does the driver */
148 };
149
150 struct RxFD {
151 __le32 state1;
152 __le32 next;
153 __le32 data;
154 __le32 state2;
155 __le32 end;
156 };
157
158 #define DUMMY_SKB_SIZE 64
159 #define TX_LOW 8
160 #define TX_RING_SIZE 32
161 #define RX_RING_SIZE 32
162 #define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct TxFD)
163 #define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct RxFD)
164 #define IRQ_RING_SIZE 64 /* Keep it a multiple of 32 */
165 #define TX_TIMEOUT (HZ/10)
166 #define DSCC4_HZ_MAX 33000000
167 #define BRR_DIVIDER_MAX 64*0x00004000 /* Cf errata DS5 p.10 */
168 #define dev_per_card 4
169 #define SCC_REGISTERS_MAX 23 /* Cf errata DS5 p.4 */
170
171 #define SOURCE_ID(flags) (((flags) >> 28) & 0x03)
172 #define TO_SIZE(state) (((state) >> 16) & 0x1fff)
173
174 /*
175 * Given the operating range of Linux HDLC, the 2 defines below could be
176 * made simpler. However they are a fine reminder for the limitations of
177 * the driver: it's better to stay < TxSizeMax and < RxSizeMax.
178 */
179 #define TO_STATE_TX(len) cpu_to_le32(((len) & TxSizeMax) << 16)
180 #define TO_STATE_RX(len) cpu_to_le32((RX_MAX(len) % RxSizeMax) << 16)
181 #define RX_MAX(len) ((((len) >> 5) + 1) << 5) /* Cf RLCR */
182 #define SCC_REG_START(dpriv) (SCC_START+(dpriv->dev_id)*SCC_OFFSET)
183
184 struct dscc4_pci_priv {
185 __le32 *iqcfg;
186 int cfg_cur;
187 spinlock_t lock;
188 struct pci_dev *pdev;
189
190 struct dscc4_dev_priv *root;
191 dma_addr_t iqcfg_dma;
192 u32 xtal_hz;
193 };
194
195 struct dscc4_dev_priv {
196 struct sk_buff *rx_skbuff[RX_RING_SIZE];
197 struct sk_buff *tx_skbuff[TX_RING_SIZE];
198
199 struct RxFD *rx_fd;
200 struct TxFD *tx_fd;
201 __le32 *iqrx;
202 __le32 *iqtx;
203
204 /* FIXME: check all the volatile are required */
205 volatile u32 tx_current;
206 u32 rx_current;
207 u32 iqtx_current;
208 u32 iqrx_current;
209
210 volatile u32 tx_dirty;
211 volatile u32 ltda;
212 u32 rx_dirty;
213 u32 lrda;
214
215 dma_addr_t tx_fd_dma;
216 dma_addr_t rx_fd_dma;
217 dma_addr_t iqtx_dma;
218 dma_addr_t iqrx_dma;
219
220 u32 scc_regs[SCC_REGISTERS_MAX]; /* Cf errata DS5 p.4 */
221
222 struct timer_list timer;
223
224 struct dscc4_pci_priv *pci_priv;
225 spinlock_t lock;
226
227 int dev_id;
228 volatile u32 flags;
229 u32 timer_help;
230
231 unsigned short encoding;
232 unsigned short parity;
233 struct net_device *dev;
234 sync_serial_settings settings;
235 void __iomem *base_addr;
236 u32 __pad __attribute__ ((aligned (4)));
237 };
238
239 /* GLOBAL registers definitions */
240 #define GCMDR 0x00
241 #define GSTAR 0x04
242 #define GMODE 0x08
243 #define IQLENR0 0x0C
244 #define IQLENR1 0x10
245 #define IQRX0 0x14
246 #define IQTX0 0x24
247 #define IQCFG 0x3c
248 #define FIFOCR1 0x44
249 #define FIFOCR2 0x48
250 #define FIFOCR3 0x4c
251 #define FIFOCR4 0x34
252 #define CH0CFG 0x50
253 #define CH0BRDA 0x54
254 #define CH0BTDA 0x58
255 #define CH0FRDA 0x98
256 #define CH0FTDA 0xb0
257 #define CH0LRDA 0xc8
258 #define CH0LTDA 0xe0
259
260 /* SCC registers definitions */
261 #define SCC_START 0x0100
262 #define SCC_OFFSET 0x80
263 #define CMDR 0x00
264 #define STAR 0x04
265 #define CCR0 0x08
266 #define CCR1 0x0c
267 #define CCR2 0x10
268 #define BRR 0x2C
269 #define RLCR 0x40
270 #define IMR 0x54
271 #define ISR 0x58
272
273 #define GPDIR 0x0400
274 #define GPDATA 0x0404
275 #define GPIM 0x0408
276
277 /* Bit masks */
278 #define EncodingMask 0x00700000
279 #define CrcMask 0x00000003
280
281 #define IntRxScc0 0x10000000
282 #define IntTxScc0 0x01000000
283
284 #define TxPollCmd 0x00000400
285 #define RxActivate 0x08000000
286 #define MTFi 0x04000000
287 #define Rdr 0x00400000
288 #define Rdt 0x00200000
289 #define Idr 0x00100000
290 #define Idt 0x00080000
291 #define TxSccRes 0x01000000
292 #define RxSccRes 0x00010000
293 #define TxSizeMax 0x1fff /* Datasheet DS1 - 11.1.1.1 */
294 #define RxSizeMax 0x1ffc /* Datasheet DS1 - 11.1.2.1 */
295
296 #define Ccr0ClockMask 0x0000003f
297 #define Ccr1LoopMask 0x00000200
298 #define IsrMask 0x000fffff
299 #define BrrExpMask 0x00000f00
300 #define BrrMultMask 0x0000003f
301 #define EncodingMask 0x00700000
302 #define Hold cpu_to_le32(0x40000000)
303 #define SccBusy 0x10000000
304 #define PowerUp 0x80000000
305 #define Vis 0x00001000
306 #define FrameOk (FrameVfr | FrameCrc)
307 #define FrameVfr 0x80
308 #define FrameRdo 0x40
309 #define FrameCrc 0x20
310 #define FrameRab 0x10
311 #define FrameAborted cpu_to_le32(0x00000200)
312 #define FrameEnd cpu_to_le32(0x80000000)
313 #define DataComplete cpu_to_le32(0x40000000)
314 #define LengthCheck 0x00008000
315 #define SccEvt 0x02000000
316 #define NoAck 0x00000200
317 #define Action 0x00000001
318 #define HiDesc cpu_to_le32(0x20000000)
319
320 /* SCC events */
321 #define RxEvt 0xf0000000
322 #define TxEvt 0x0f000000
323 #define Alls 0x00040000
324 #define Xdu 0x00010000
325 #define Cts 0x00004000
326 #define Xmr 0x00002000
327 #define Xpr 0x00001000
328 #define Rdo 0x00000080
329 #define Rfs 0x00000040
330 #define Cd 0x00000004
331 #define Rfo 0x00000002
332 #define Flex 0x00000001
333
334 /* DMA core events */
335 #define Cfg 0x00200000
336 #define Hi 0x00040000
337 #define Fi 0x00020000
338 #define Err 0x00010000
339 #define Arf 0x00000002
340 #define ArAck 0x00000001
341
342 /* State flags */
343 #define Ready 0x00000000
344 #define NeedIDR 0x00000001
345 #define NeedIDT 0x00000002
346 #define RdoSet 0x00000004
347 #define FakeReset 0x00000008
348
349 /* Don't mask RDO. Ever. */
350 #ifdef DSCC4_POLLING
351 #define EventsMask 0xfffeef7f
352 #else
353 #define EventsMask 0xfffa8f7a
354 #endif
355
356 /* Functions prototypes */
357 static void dscc4_rx_irq(struct dscc4_pci_priv *, struct dscc4_dev_priv *);
358 static void dscc4_tx_irq(struct dscc4_pci_priv *, struct dscc4_dev_priv *);
359 static int dscc4_found1(struct pci_dev *, void __iomem *ioaddr);
360 static int dscc4_init_one(struct pci_dev *, const struct pci_device_id *ent);
361 static int dscc4_open(struct net_device *);
362 static int dscc4_start_xmit(struct sk_buff *, struct net_device *);
363 static int dscc4_close(struct net_device *);
364 static int dscc4_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
365 static int dscc4_init_ring(struct net_device *);
366 static void dscc4_release_ring(struct dscc4_dev_priv *);
367 static void dscc4_timer(unsigned long);
368 static void dscc4_tx_timeout(struct net_device *);
369 static irqreturn_t dscc4_irq(int irq, void *dev_id);
370 static int dscc4_hdlc_attach(struct net_device *, unsigned short, unsigned short);
371 static int dscc4_set_iface(struct dscc4_dev_priv *, struct net_device *);
372 #ifdef DSCC4_POLLING
373 static int dscc4_tx_poll(struct dscc4_dev_priv *, struct net_device *);
374 #endif
375
dscc4_priv(struct net_device * dev)376 static inline struct dscc4_dev_priv *dscc4_priv(struct net_device *dev)
377 {
378 return dev_to_hdlc(dev)->priv;
379 }
380
dscc4_to_dev(struct dscc4_dev_priv * p)381 static inline struct net_device *dscc4_to_dev(struct dscc4_dev_priv *p)
382 {
383 return p->dev;
384 }
385
scc_patchl(u32 mask,u32 value,struct dscc4_dev_priv * dpriv,struct net_device * dev,int offset)386 static void scc_patchl(u32 mask, u32 value, struct dscc4_dev_priv *dpriv,
387 struct net_device *dev, int offset)
388 {
389 u32 state;
390
391 /* Cf scc_writel for concern regarding thread-safety */
392 state = dpriv->scc_regs[offset >> 2];
393 state &= ~mask;
394 state |= value;
395 dpriv->scc_regs[offset >> 2] = state;
396 writel(state, dpriv->base_addr + SCC_REG_START(dpriv) + offset);
397 }
398
scc_writel(u32 bits,struct dscc4_dev_priv * dpriv,struct net_device * dev,int offset)399 static void scc_writel(u32 bits, struct dscc4_dev_priv *dpriv,
400 struct net_device *dev, int offset)
401 {
402 /*
403 * Thread-UNsafe.
404 * As of 2002/02/16, there are no thread racing for access.
405 */
406 dpriv->scc_regs[offset >> 2] = bits;
407 writel(bits, dpriv->base_addr + SCC_REG_START(dpriv) + offset);
408 }
409
scc_readl(struct dscc4_dev_priv * dpriv,int offset)410 static inline u32 scc_readl(struct dscc4_dev_priv *dpriv, int offset)
411 {
412 return dpriv->scc_regs[offset >> 2];
413 }
414
scc_readl_star(struct dscc4_dev_priv * dpriv,struct net_device * dev)415 static u32 scc_readl_star(struct dscc4_dev_priv *dpriv, struct net_device *dev)
416 {
417 /* Cf errata DS5 p.4 */
418 readl(dpriv->base_addr + SCC_REG_START(dpriv) + STAR);
419 return readl(dpriv->base_addr + SCC_REG_START(dpriv) + STAR);
420 }
421
dscc4_do_tx(struct dscc4_dev_priv * dpriv,struct net_device * dev)422 static inline void dscc4_do_tx(struct dscc4_dev_priv *dpriv,
423 struct net_device *dev)
424 {
425 dpriv->ltda = dpriv->tx_fd_dma +
426 ((dpriv->tx_current-1)%TX_RING_SIZE)*sizeof(struct TxFD);
427 writel(dpriv->ltda, dpriv->base_addr + CH0LTDA + dpriv->dev_id*4);
428 /* Flush posted writes *NOW* */
429 readl(dpriv->base_addr + CH0LTDA + dpriv->dev_id*4);
430 }
431
dscc4_rx_update(struct dscc4_dev_priv * dpriv,struct net_device * dev)432 static inline void dscc4_rx_update(struct dscc4_dev_priv *dpriv,
433 struct net_device *dev)
434 {
435 dpriv->lrda = dpriv->rx_fd_dma +
436 ((dpriv->rx_dirty - 1)%RX_RING_SIZE)*sizeof(struct RxFD);
437 writel(dpriv->lrda, dpriv->base_addr + CH0LRDA + dpriv->dev_id*4);
438 }
439
dscc4_tx_done(struct dscc4_dev_priv * dpriv)440 static inline unsigned int dscc4_tx_done(struct dscc4_dev_priv *dpriv)
441 {
442 return dpriv->tx_current == dpriv->tx_dirty;
443 }
444
dscc4_tx_quiescent(struct dscc4_dev_priv * dpriv,struct net_device * dev)445 static inline unsigned int dscc4_tx_quiescent(struct dscc4_dev_priv *dpriv,
446 struct net_device *dev)
447 {
448 return readl(dpriv->base_addr + CH0FTDA + dpriv->dev_id*4) == dpriv->ltda;
449 }
450
state_check(u32 state,struct dscc4_dev_priv * dpriv,struct net_device * dev,const char * msg)451 static int state_check(u32 state, struct dscc4_dev_priv *dpriv,
452 struct net_device *dev, const char *msg)
453 {
454 int ret = 0;
455
456 if (debug > 1) {
457 if (SOURCE_ID(state) != dpriv->dev_id) {
458 printk(KERN_DEBUG "%s (%s): Source Id=%d, state=%08x\n",
459 dev->name, msg, SOURCE_ID(state), state );
460 ret = -1;
461 }
462 if (state & 0x0df80c00) {
463 printk(KERN_DEBUG "%s (%s): state=%08x (UFO alert)\n",
464 dev->name, msg, state);
465 ret = -1;
466 }
467 }
468 return ret;
469 }
470
dscc4_tx_print(struct net_device * dev,struct dscc4_dev_priv * dpriv,char * msg)471 static void dscc4_tx_print(struct net_device *dev,
472 struct dscc4_dev_priv *dpriv,
473 char *msg)
474 {
475 printk(KERN_DEBUG "%s: tx_current=%02d tx_dirty=%02d (%s)\n",
476 dev->name, dpriv->tx_current, dpriv->tx_dirty, msg);
477 }
478
dscc4_release_ring(struct dscc4_dev_priv * dpriv)479 static void dscc4_release_ring(struct dscc4_dev_priv *dpriv)
480 {
481 struct pci_dev *pdev = dpriv->pci_priv->pdev;
482 struct TxFD *tx_fd = dpriv->tx_fd;
483 struct RxFD *rx_fd = dpriv->rx_fd;
484 struct sk_buff **skbuff;
485 int i;
486
487 pci_free_consistent(pdev, TX_TOTAL_SIZE, tx_fd, dpriv->tx_fd_dma);
488 pci_free_consistent(pdev, RX_TOTAL_SIZE, rx_fd, dpriv->rx_fd_dma);
489
490 skbuff = dpriv->tx_skbuff;
491 for (i = 0; i < TX_RING_SIZE; i++) {
492 if (*skbuff) {
493 pci_unmap_single(pdev, le32_to_cpu(tx_fd->data),
494 (*skbuff)->len, PCI_DMA_TODEVICE);
495 dev_kfree_skb(*skbuff);
496 }
497 skbuff++;
498 tx_fd++;
499 }
500
501 skbuff = dpriv->rx_skbuff;
502 for (i = 0; i < RX_RING_SIZE; i++) {
503 if (*skbuff) {
504 pci_unmap_single(pdev, le32_to_cpu(rx_fd->data),
505 RX_MAX(HDLC_MAX_MRU), PCI_DMA_FROMDEVICE);
506 dev_kfree_skb(*skbuff);
507 }
508 skbuff++;
509 rx_fd++;
510 }
511 }
512
try_get_rx_skb(struct dscc4_dev_priv * dpriv,struct net_device * dev)513 static inline int try_get_rx_skb(struct dscc4_dev_priv *dpriv,
514 struct net_device *dev)
515 {
516 unsigned int dirty = dpriv->rx_dirty%RX_RING_SIZE;
517 struct RxFD *rx_fd = dpriv->rx_fd + dirty;
518 const int len = RX_MAX(HDLC_MAX_MRU);
519 struct sk_buff *skb;
520 int ret = 0;
521
522 skb = dev_alloc_skb(len);
523 dpriv->rx_skbuff[dirty] = skb;
524 if (skb) {
525 skb->protocol = hdlc_type_trans(skb, dev);
526 rx_fd->data = cpu_to_le32(pci_map_single(dpriv->pci_priv->pdev,
527 skb->data, len, PCI_DMA_FROMDEVICE));
528 } else {
529 rx_fd->data = 0;
530 ret = -1;
531 }
532 return ret;
533 }
534
535 /*
536 * IRQ/thread/whatever safe
537 */
dscc4_wait_ack_cec(struct dscc4_dev_priv * dpriv,struct net_device * dev,char * msg)538 static int dscc4_wait_ack_cec(struct dscc4_dev_priv *dpriv,
539 struct net_device *dev, char *msg)
540 {
541 s8 i = 0;
542
543 do {
544 if (!(scc_readl_star(dpriv, dev) & SccBusy)) {
545 printk(KERN_DEBUG "%s: %s ack (%d try)\n", dev->name,
546 msg, i);
547 goto done;
548 }
549 schedule_timeout_uninterruptible(10);
550 rmb();
551 } while (++i > 0);
552 printk(KERN_ERR "%s: %s timeout\n", dev->name, msg);
553 done:
554 return (i >= 0) ? i : -EAGAIN;
555 }
556
dscc4_do_action(struct net_device * dev,char * msg)557 static int dscc4_do_action(struct net_device *dev, char *msg)
558 {
559 void __iomem *ioaddr = dscc4_priv(dev)->base_addr;
560 s16 i = 0;
561
562 writel(Action, ioaddr + GCMDR);
563 ioaddr += GSTAR;
564 do {
565 u32 state = readl(ioaddr);
566
567 if (state & ArAck) {
568 printk(KERN_DEBUG "%s: %s ack\n", dev->name, msg);
569 writel(ArAck, ioaddr);
570 goto done;
571 } else if (state & Arf) {
572 printk(KERN_ERR "%s: %s failed\n", dev->name, msg);
573 writel(Arf, ioaddr);
574 i = -1;
575 goto done;
576 }
577 rmb();
578 } while (++i > 0);
579 printk(KERN_ERR "%s: %s timeout\n", dev->name, msg);
580 done:
581 return i;
582 }
583
dscc4_xpr_ack(struct dscc4_dev_priv * dpriv)584 static inline int dscc4_xpr_ack(struct dscc4_dev_priv *dpriv)
585 {
586 int cur = dpriv->iqtx_current%IRQ_RING_SIZE;
587 s8 i = 0;
588
589 do {
590 if (!(dpriv->flags & (NeedIDR | NeedIDT)) ||
591 (dpriv->iqtx[cur] & cpu_to_le32(Xpr)))
592 break;
593 smp_rmb();
594 schedule_timeout_uninterruptible(10);
595 } while (++i > 0);
596
597 return (i >= 0 ) ? i : -EAGAIN;
598 }
599
600 #if 0 /* dscc4_{rx/tx}_reset are both unreliable - more tweak needed */
601 static void dscc4_rx_reset(struct dscc4_dev_priv *dpriv, struct net_device *dev)
602 {
603 unsigned long flags;
604
605 spin_lock_irqsave(&dpriv->pci_priv->lock, flags);
606 /* Cf errata DS5 p.6 */
607 writel(0x00000000, dpriv->base_addr + CH0LRDA + dpriv->dev_id*4);
608 scc_patchl(PowerUp, 0, dpriv, dev, CCR0);
609 readl(dpriv->base_addr + CH0LRDA + dpriv->dev_id*4);
610 writel(MTFi|Rdr, dpriv->base_addr + dpriv->dev_id*0x0c + CH0CFG);
611 writel(Action, dpriv->base_addr + GCMDR);
612 spin_unlock_irqrestore(&dpriv->pci_priv->lock, flags);
613 }
614
615 #endif
616
617 #if 0
618 static void dscc4_tx_reset(struct dscc4_dev_priv *dpriv, struct net_device *dev)
619 {
620 u16 i = 0;
621
622 /* Cf errata DS5 p.7 */
623 scc_patchl(PowerUp, 0, dpriv, dev, CCR0);
624 scc_writel(0x00050000, dpriv, dev, CCR2);
625 /*
626 * Must be longer than the time required to fill the fifo.
627 */
628 while (!dscc4_tx_quiescent(dpriv, dev) && ++i) {
629 udelay(1);
630 wmb();
631 }
632
633 writel(MTFi|Rdt, dpriv->base_addr + dpriv->dev_id*0x0c + CH0CFG);
634 if (dscc4_do_action(dev, "Rdt") < 0)
635 printk(KERN_ERR "%s: Tx reset failed\n", dev->name);
636 }
637 #endif
638
639 /* TODO: (ab)use this function to refill a completely depleted RX ring. */
dscc4_rx_skb(struct dscc4_dev_priv * dpriv,struct net_device * dev)640 static inline void dscc4_rx_skb(struct dscc4_dev_priv *dpriv,
641 struct net_device *dev)
642 {
643 struct RxFD *rx_fd = dpriv->rx_fd + dpriv->rx_current%RX_RING_SIZE;
644 struct pci_dev *pdev = dpriv->pci_priv->pdev;
645 struct sk_buff *skb;
646 int pkt_len;
647
648 skb = dpriv->rx_skbuff[dpriv->rx_current++%RX_RING_SIZE];
649 if (!skb) {
650 printk(KERN_DEBUG "%s: skb=0 (%s)\n", dev->name, __func__);
651 goto refill;
652 }
653 pkt_len = TO_SIZE(le32_to_cpu(rx_fd->state2));
654 pci_unmap_single(pdev, le32_to_cpu(rx_fd->data),
655 RX_MAX(HDLC_MAX_MRU), PCI_DMA_FROMDEVICE);
656 if ((skb->data[--pkt_len] & FrameOk) == FrameOk) {
657 dev->stats.rx_packets++;
658 dev->stats.rx_bytes += pkt_len;
659 skb_put(skb, pkt_len);
660 if (netif_running(dev))
661 skb->protocol = hdlc_type_trans(skb, dev);
662 netif_rx(skb);
663 } else {
664 if (skb->data[pkt_len] & FrameRdo)
665 dev->stats.rx_fifo_errors++;
666 else if (!(skb->data[pkt_len] | ~FrameCrc))
667 dev->stats.rx_crc_errors++;
668 else if (!(skb->data[pkt_len] | ~(FrameVfr | FrameRab)))
669 dev->stats.rx_length_errors++;
670 else
671 dev->stats.rx_errors++;
672 dev_kfree_skb_irq(skb);
673 }
674 refill:
675 while ((dpriv->rx_dirty - dpriv->rx_current) % RX_RING_SIZE) {
676 if (try_get_rx_skb(dpriv, dev) < 0)
677 break;
678 dpriv->rx_dirty++;
679 }
680 dscc4_rx_update(dpriv, dev);
681 rx_fd->state2 = 0x00000000;
682 rx_fd->end = cpu_to_le32(0xbabeface);
683 }
684
dscc4_free1(struct pci_dev * pdev)685 static void dscc4_free1(struct pci_dev *pdev)
686 {
687 struct dscc4_pci_priv *ppriv;
688 struct dscc4_dev_priv *root;
689 int i;
690
691 ppriv = pci_get_drvdata(pdev);
692 root = ppriv->root;
693
694 for (i = 0; i < dev_per_card; i++)
695 unregister_hdlc_device(dscc4_to_dev(root + i));
696
697 pci_set_drvdata(pdev, NULL);
698
699 for (i = 0; i < dev_per_card; i++)
700 free_netdev(root[i].dev);
701 kfree(root);
702 kfree(ppriv);
703 }
704
dscc4_init_one(struct pci_dev * pdev,const struct pci_device_id * ent)705 static int __devinit dscc4_init_one(struct pci_dev *pdev,
706 const struct pci_device_id *ent)
707 {
708 struct dscc4_pci_priv *priv;
709 struct dscc4_dev_priv *dpriv;
710 void __iomem *ioaddr;
711 int i, rc;
712
713 printk(KERN_DEBUG "%s", version);
714
715 rc = pci_enable_device(pdev);
716 if (rc < 0)
717 goto out;
718
719 rc = pci_request_region(pdev, 0, "registers");
720 if (rc < 0) {
721 printk(KERN_ERR "%s: can't reserve MMIO region (regs)\n",
722 DRV_NAME);
723 goto err_disable_0;
724 }
725 rc = pci_request_region(pdev, 1, "LBI interface");
726 if (rc < 0) {
727 printk(KERN_ERR "%s: can't reserve MMIO region (lbi)\n",
728 DRV_NAME);
729 goto err_free_mmio_region_1;
730 }
731
732 ioaddr = pci_ioremap_bar(pdev, 0);
733 if (!ioaddr) {
734 printk(KERN_ERR "%s: cannot remap MMIO region %llx @ %llx\n",
735 DRV_NAME, (unsigned long long)pci_resource_len(pdev, 0),
736 (unsigned long long)pci_resource_start(pdev, 0));
737 rc = -EIO;
738 goto err_free_mmio_regions_2;
739 }
740 printk(KERN_DEBUG "Siemens DSCC4, MMIO at %#llx (regs), %#llx (lbi), IRQ %d\n",
741 (unsigned long long)pci_resource_start(pdev, 0),
742 (unsigned long long)pci_resource_start(pdev, 1), pdev->irq);
743
744 /* Cf errata DS5 p.2 */
745 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xf8);
746 pci_set_master(pdev);
747
748 rc = dscc4_found1(pdev, ioaddr);
749 if (rc < 0)
750 goto err_iounmap_3;
751
752 priv = pci_get_drvdata(pdev);
753
754 rc = request_irq(pdev->irq, dscc4_irq, IRQF_SHARED, DRV_NAME, priv->root);
755 if (rc < 0) {
756 printk(KERN_WARNING "%s: IRQ %d busy\n", DRV_NAME, pdev->irq);
757 goto err_release_4;
758 }
759
760 /* power up/little endian/dma core controlled via lrda/ltda */
761 writel(0x00000001, ioaddr + GMODE);
762 /* Shared interrupt queue */
763 {
764 u32 bits;
765
766 bits = (IRQ_RING_SIZE >> 5) - 1;
767 bits |= bits << 4;
768 bits |= bits << 8;
769 bits |= bits << 16;
770 writel(bits, ioaddr + IQLENR0);
771 }
772 /* Global interrupt queue */
773 writel((u32)(((IRQ_RING_SIZE >> 5) - 1) << 20), ioaddr + IQLENR1);
774 priv->iqcfg = (__le32 *) pci_alloc_consistent(pdev,
775 IRQ_RING_SIZE*sizeof(__le32), &priv->iqcfg_dma);
776 if (!priv->iqcfg)
777 goto err_free_irq_5;
778 writel(priv->iqcfg_dma, ioaddr + IQCFG);
779
780 rc = -ENOMEM;
781
782 /*
783 * SCC 0-3 private rx/tx irq structures
784 * IQRX/TXi needs to be set soon. Learned it the hard way...
785 */
786 for (i = 0; i < dev_per_card; i++) {
787 dpriv = priv->root + i;
788 dpriv->iqtx = (__le32 *) pci_alloc_consistent(pdev,
789 IRQ_RING_SIZE*sizeof(u32), &dpriv->iqtx_dma);
790 if (!dpriv->iqtx)
791 goto err_free_iqtx_6;
792 writel(dpriv->iqtx_dma, ioaddr + IQTX0 + i*4);
793 }
794 for (i = 0; i < dev_per_card; i++) {
795 dpriv = priv->root + i;
796 dpriv->iqrx = (__le32 *) pci_alloc_consistent(pdev,
797 IRQ_RING_SIZE*sizeof(u32), &dpriv->iqrx_dma);
798 if (!dpriv->iqrx)
799 goto err_free_iqrx_7;
800 writel(dpriv->iqrx_dma, ioaddr + IQRX0 + i*4);
801 }
802
803 /* Cf application hint. Beware of hard-lock condition on threshold. */
804 writel(0x42104000, ioaddr + FIFOCR1);
805 //writel(0x9ce69800, ioaddr + FIFOCR2);
806 writel(0xdef6d800, ioaddr + FIFOCR2);
807 //writel(0x11111111, ioaddr + FIFOCR4);
808 writel(0x18181818, ioaddr + FIFOCR4);
809 // FIXME: should depend on the chipset revision
810 writel(0x0000000e, ioaddr + FIFOCR3);
811
812 writel(0xff200001, ioaddr + GCMDR);
813
814 rc = 0;
815 out:
816 return rc;
817
818 err_free_iqrx_7:
819 while (--i >= 0) {
820 dpriv = priv->root + i;
821 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32),
822 dpriv->iqrx, dpriv->iqrx_dma);
823 }
824 i = dev_per_card;
825 err_free_iqtx_6:
826 while (--i >= 0) {
827 dpriv = priv->root + i;
828 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32),
829 dpriv->iqtx, dpriv->iqtx_dma);
830 }
831 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32), priv->iqcfg,
832 priv->iqcfg_dma);
833 err_free_irq_5:
834 free_irq(pdev->irq, priv->root);
835 err_release_4:
836 dscc4_free1(pdev);
837 err_iounmap_3:
838 iounmap (ioaddr);
839 err_free_mmio_regions_2:
840 pci_release_region(pdev, 1);
841 err_free_mmio_region_1:
842 pci_release_region(pdev, 0);
843 err_disable_0:
844 pci_disable_device(pdev);
845 goto out;
846 };
847
848 /*
849 * Let's hope the default values are decent enough to protect my
850 * feet from the user's gun - Ueimor
851 */
dscc4_init_registers(struct dscc4_dev_priv * dpriv,struct net_device * dev)852 static void dscc4_init_registers(struct dscc4_dev_priv *dpriv,
853 struct net_device *dev)
854 {
855 /* No interrupts, SCC core disabled. Let's relax */
856 scc_writel(0x00000000, dpriv, dev, CCR0);
857
858 scc_writel(LengthCheck | (HDLC_MAX_MRU >> 5), dpriv, dev, RLCR);
859
860 /*
861 * No address recognition/crc-CCITT/cts enabled
862 * Shared flags transmission disabled - cf errata DS5 p.11
863 * Carrier detect disabled - cf errata p.14
864 * FIXME: carrier detection/polarity may be handled more gracefully.
865 */
866 scc_writel(0x02408000, dpriv, dev, CCR1);
867
868 /* crc not forwarded - Cf errata DS5 p.11 */
869 scc_writel(0x00050008 & ~RxActivate, dpriv, dev, CCR2);
870 // crc forwarded
871 //scc_writel(0x00250008 & ~RxActivate, dpriv, dev, CCR2);
872 }
873
dscc4_set_quartz(struct dscc4_dev_priv * dpriv,int hz)874 static inline int dscc4_set_quartz(struct dscc4_dev_priv *dpriv, int hz)
875 {
876 int ret = 0;
877
878 if ((hz < 0) || (hz > DSCC4_HZ_MAX))
879 ret = -EOPNOTSUPP;
880 else
881 dpriv->pci_priv->xtal_hz = hz;
882
883 return ret;
884 }
885
dscc4_found1(struct pci_dev * pdev,void __iomem * ioaddr)886 static int dscc4_found1(struct pci_dev *pdev, void __iomem *ioaddr)
887 {
888 struct dscc4_pci_priv *ppriv;
889 struct dscc4_dev_priv *root;
890 int i, ret = -ENOMEM;
891
892 root = kcalloc(dev_per_card, sizeof(*root), GFP_KERNEL);
893 if (!root) {
894 printk(KERN_ERR "%s: can't allocate data\n", DRV_NAME);
895 goto err_out;
896 }
897
898 for (i = 0; i < dev_per_card; i++) {
899 root[i].dev = alloc_hdlcdev(root + i);
900 if (!root[i].dev)
901 goto err_free_dev;
902 }
903
904 ppriv = kzalloc(sizeof(*ppriv), GFP_KERNEL);
905 if (!ppriv) {
906 printk(KERN_ERR "%s: can't allocate private data\n", DRV_NAME);
907 goto err_free_dev;
908 }
909
910 ppriv->root = root;
911 spin_lock_init(&ppriv->lock);
912
913 for (i = 0; i < dev_per_card; i++) {
914 struct dscc4_dev_priv *dpriv = root + i;
915 struct net_device *d = dscc4_to_dev(dpriv);
916 hdlc_device *hdlc = dev_to_hdlc(d);
917
918 d->base_addr = (unsigned long)ioaddr;
919 d->init = NULL;
920 d->irq = pdev->irq;
921 d->open = dscc4_open;
922 d->stop = dscc4_close;
923 d->set_multicast_list = NULL;
924 d->do_ioctl = dscc4_ioctl;
925 d->tx_timeout = dscc4_tx_timeout;
926 d->watchdog_timeo = TX_TIMEOUT;
927 SET_NETDEV_DEV(d, &pdev->dev);
928
929 dpriv->dev_id = i;
930 dpriv->pci_priv = ppriv;
931 dpriv->base_addr = ioaddr;
932 spin_lock_init(&dpriv->lock);
933
934 hdlc->xmit = dscc4_start_xmit;
935 hdlc->attach = dscc4_hdlc_attach;
936
937 dscc4_init_registers(dpriv, d);
938 dpriv->parity = PARITY_CRC16_PR0_CCITT;
939 dpriv->encoding = ENCODING_NRZ;
940
941 ret = dscc4_init_ring(d);
942 if (ret < 0)
943 goto err_unregister;
944
945 ret = register_hdlc_device(d);
946 if (ret < 0) {
947 printk(KERN_ERR "%s: unable to register\n", DRV_NAME);
948 dscc4_release_ring(dpriv);
949 goto err_unregister;
950 }
951 }
952
953 ret = dscc4_set_quartz(root, quartz);
954 if (ret < 0)
955 goto err_unregister;
956
957 pci_set_drvdata(pdev, ppriv);
958 return ret;
959
960 err_unregister:
961 while (i-- > 0) {
962 dscc4_release_ring(root + i);
963 unregister_hdlc_device(dscc4_to_dev(root + i));
964 }
965 kfree(ppriv);
966 i = dev_per_card;
967 err_free_dev:
968 while (i-- > 0)
969 free_netdev(root[i].dev);
970 kfree(root);
971 err_out:
972 return ret;
973 };
974
975 /* FIXME: get rid of the unneeded code */
dscc4_timer(unsigned long data)976 static void dscc4_timer(unsigned long data)
977 {
978 struct net_device *dev = (struct net_device *)data;
979 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
980 // struct dscc4_pci_priv *ppriv;
981
982 goto done;
983 done:
984 dpriv->timer.expires = jiffies + TX_TIMEOUT;
985 add_timer(&dpriv->timer);
986 }
987
dscc4_tx_timeout(struct net_device * dev)988 static void dscc4_tx_timeout(struct net_device *dev)
989 {
990 /* FIXME: something is missing there */
991 }
992
dscc4_loopback_check(struct dscc4_dev_priv * dpriv)993 static int dscc4_loopback_check(struct dscc4_dev_priv *dpriv)
994 {
995 sync_serial_settings *settings = &dpriv->settings;
996
997 if (settings->loopback && (settings->clock_type != CLOCK_INT)) {
998 struct net_device *dev = dscc4_to_dev(dpriv);
999
1000 printk(KERN_INFO "%s: loopback requires clock\n", dev->name);
1001 return -1;
1002 }
1003 return 0;
1004 }
1005
1006 #ifdef CONFIG_DSCC4_PCI_RST
1007 /*
1008 * Some DSCC4-based cards wires the GPIO port and the PCI #RST pin together
1009 * so as to provide a safe way to reset the asic while not the whole machine
1010 * rebooting.
1011 *
1012 * This code doesn't need to be efficient. Keep It Simple
1013 */
dscc4_pci_reset(struct pci_dev * pdev,void __iomem * ioaddr)1014 static void dscc4_pci_reset(struct pci_dev *pdev, void __iomem *ioaddr)
1015 {
1016 int i;
1017
1018 mutex_lock(&dscc4_mutex);
1019 for (i = 0; i < 16; i++)
1020 pci_read_config_dword(pdev, i << 2, dscc4_pci_config_store + i);
1021
1022 /* Maximal LBI clock divider (who cares ?) and whole GPIO range. */
1023 writel(0x001c0000, ioaddr + GMODE);
1024 /* Configure GPIO port as output */
1025 writel(0x0000ffff, ioaddr + GPDIR);
1026 /* Disable interruption */
1027 writel(0x0000ffff, ioaddr + GPIM);
1028
1029 writel(0x0000ffff, ioaddr + GPDATA);
1030 writel(0x00000000, ioaddr + GPDATA);
1031
1032 /* Flush posted writes */
1033 readl(ioaddr + GSTAR);
1034
1035 schedule_timeout_uninterruptible(10);
1036
1037 for (i = 0; i < 16; i++)
1038 pci_write_config_dword(pdev, i << 2, dscc4_pci_config_store[i]);
1039 mutex_unlock(&dscc4_mutex);
1040 }
1041 #else
1042 #define dscc4_pci_reset(pdev,ioaddr) do {} while (0)
1043 #endif /* CONFIG_DSCC4_PCI_RST */
1044
dscc4_open(struct net_device * dev)1045 static int dscc4_open(struct net_device *dev)
1046 {
1047 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1048 struct dscc4_pci_priv *ppriv;
1049 int ret = -EAGAIN;
1050
1051 if ((dscc4_loopback_check(dpriv) < 0) || !dev->hard_start_xmit)
1052 goto err;
1053
1054 if ((ret = hdlc_open(dev)))
1055 goto err;
1056
1057 ppriv = dpriv->pci_priv;
1058
1059 /*
1060 * Due to various bugs, there is no way to reliably reset a
1061 * specific port (manufacturer's dependant special PCI #RST wiring
1062 * apart: it affects all ports). Thus the device goes in the best
1063 * silent mode possible at dscc4_close() time and simply claims to
1064 * be up if it's opened again. It still isn't possible to change
1065 * the HDLC configuration without rebooting but at least the ports
1066 * can be up/down ifconfig'ed without killing the host.
1067 */
1068 if (dpriv->flags & FakeReset) {
1069 dpriv->flags &= ~FakeReset;
1070 scc_patchl(0, PowerUp, dpriv, dev, CCR0);
1071 scc_patchl(0, 0x00050000, dpriv, dev, CCR2);
1072 scc_writel(EventsMask, dpriv, dev, IMR);
1073 printk(KERN_INFO "%s: up again.\n", dev->name);
1074 goto done;
1075 }
1076
1077 /* IDT+IDR during XPR */
1078 dpriv->flags = NeedIDR | NeedIDT;
1079
1080 scc_patchl(0, PowerUp | Vis, dpriv, dev, CCR0);
1081
1082 /*
1083 * The following is a bit paranoid...
1084 *
1085 * NB: the datasheet "...CEC will stay active if the SCC is in
1086 * power-down mode or..." and CCR2.RAC = 1 are two different
1087 * situations.
1088 */
1089 if (scc_readl_star(dpriv, dev) & SccBusy) {
1090 printk(KERN_ERR "%s busy. Try later\n", dev->name);
1091 ret = -EAGAIN;
1092 goto err_out;
1093 } else
1094 printk(KERN_INFO "%s: available. Good\n", dev->name);
1095
1096 scc_writel(EventsMask, dpriv, dev, IMR);
1097
1098 /* Posted write is flushed in the wait_ack loop */
1099 scc_writel(TxSccRes | RxSccRes, dpriv, dev, CMDR);
1100
1101 if ((ret = dscc4_wait_ack_cec(dpriv, dev, "Cec")) < 0)
1102 goto err_disable_scc_events;
1103
1104 /*
1105 * I would expect XPR near CE completion (before ? after ?).
1106 * At worst, this code won't see a late XPR and people
1107 * will have to re-issue an ifconfig (this is harmless).
1108 * WARNING, a really missing XPR usually means a hardware
1109 * reset is needed. Suggestions anyone ?
1110 */
1111 if ((ret = dscc4_xpr_ack(dpriv)) < 0) {
1112 printk(KERN_ERR "%s: %s timeout\n", DRV_NAME, "XPR");
1113 goto err_disable_scc_events;
1114 }
1115
1116 if (debug > 2)
1117 dscc4_tx_print(dev, dpriv, "Open");
1118
1119 done:
1120 netif_start_queue(dev);
1121
1122 init_timer(&dpriv->timer);
1123 dpriv->timer.expires = jiffies + 10*HZ;
1124 dpriv->timer.data = (unsigned long)dev;
1125 dpriv->timer.function = &dscc4_timer;
1126 add_timer(&dpriv->timer);
1127 netif_carrier_on(dev);
1128
1129 return 0;
1130
1131 err_disable_scc_events:
1132 scc_writel(0xffffffff, dpriv, dev, IMR);
1133 scc_patchl(PowerUp | Vis, 0, dpriv, dev, CCR0);
1134 err_out:
1135 hdlc_close(dev);
1136 err:
1137 return ret;
1138 }
1139
1140 #ifdef DSCC4_POLLING
dscc4_tx_poll(struct dscc4_dev_priv * dpriv,struct net_device * dev)1141 static int dscc4_tx_poll(struct dscc4_dev_priv *dpriv, struct net_device *dev)
1142 {
1143 /* FIXME: it's gonna be easy (TM), for sure */
1144 }
1145 #endif /* DSCC4_POLLING */
1146
dscc4_start_xmit(struct sk_buff * skb,struct net_device * dev)1147 static int dscc4_start_xmit(struct sk_buff *skb, struct net_device *dev)
1148 {
1149 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1150 struct dscc4_pci_priv *ppriv = dpriv->pci_priv;
1151 struct TxFD *tx_fd;
1152 int next;
1153
1154 next = dpriv->tx_current%TX_RING_SIZE;
1155 dpriv->tx_skbuff[next] = skb;
1156 tx_fd = dpriv->tx_fd + next;
1157 tx_fd->state = FrameEnd | TO_STATE_TX(skb->len);
1158 tx_fd->data = cpu_to_le32(pci_map_single(ppriv->pdev, skb->data, skb->len,
1159 PCI_DMA_TODEVICE));
1160 tx_fd->complete = 0x00000000;
1161 tx_fd->jiffies = jiffies;
1162 mb();
1163
1164 #ifdef DSCC4_POLLING
1165 spin_lock(&dpriv->lock);
1166 while (dscc4_tx_poll(dpriv, dev));
1167 spin_unlock(&dpriv->lock);
1168 #endif
1169
1170 dev->trans_start = jiffies;
1171
1172 if (debug > 2)
1173 dscc4_tx_print(dev, dpriv, "Xmit");
1174 /* To be cleaned(unsigned int)/optimized. Later, ok ? */
1175 if (!((++dpriv->tx_current - dpriv->tx_dirty)%TX_RING_SIZE))
1176 netif_stop_queue(dev);
1177
1178 if (dscc4_tx_quiescent(dpriv, dev))
1179 dscc4_do_tx(dpriv, dev);
1180
1181 return 0;
1182 }
1183
dscc4_close(struct net_device * dev)1184 static int dscc4_close(struct net_device *dev)
1185 {
1186 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1187
1188 del_timer_sync(&dpriv->timer);
1189 netif_stop_queue(dev);
1190
1191 scc_patchl(PowerUp | Vis, 0, dpriv, dev, CCR0);
1192 scc_patchl(0x00050000, 0, dpriv, dev, CCR2);
1193 scc_writel(0xffffffff, dpriv, dev, IMR);
1194
1195 dpriv->flags |= FakeReset;
1196
1197 hdlc_close(dev);
1198
1199 return 0;
1200 }
1201
dscc4_check_clock_ability(int port)1202 static inline int dscc4_check_clock_ability(int port)
1203 {
1204 int ret = 0;
1205
1206 #ifdef CONFIG_DSCC4_PCISYNC
1207 if (port >= 2)
1208 ret = -1;
1209 #endif
1210 return ret;
1211 }
1212
1213 /*
1214 * DS1 p.137: "There are a total of 13 different clocking modes..."
1215 * ^^
1216 * Design choices:
1217 * - by default, assume a clock is provided on pin RxClk/TxClk (clock mode 0a).
1218 * Clock mode 3b _should_ work but the testing seems to make this point
1219 * dubious (DIY testing requires setting CCR0 at 0x00000033).
1220 * This is supposed to provide least surprise "DTE like" behavior.
1221 * - if line rate is specified, clocks are assumed to be locally generated.
1222 * A quartz must be available (on pin XTAL1). Modes 6b/7b are used. Choosing
1223 * between these it automagically done according on the required frequency
1224 * scaling. Of course some rounding may take place.
1225 * - no high speed mode (40Mb/s). May be trivial to do but I don't have an
1226 * appropriate external clocking device for testing.
1227 * - no time-slot/clock mode 5: shameless lazyness.
1228 *
1229 * The clock signals wiring can be (is ?) manufacturer dependant. Good luck.
1230 *
1231 * BIG FAT WARNING: if the device isn't provided enough clocking signal, it
1232 * won't pass the init sequence. For example, straight back-to-back DTE without
1233 * external clock will fail when dscc4_open() (<- 'ifconfig hdlcx xxx') is
1234 * called.
1235 *
1236 * Typos lurk in datasheet (missing divier in clock mode 7a figure 51 p.153
1237 * DS0 for example)
1238 *
1239 * Clock mode related bits of CCR0:
1240 * +------------ TOE: output TxClk (0b/2b/3a/3b/6b/7a/7b only)
1241 * | +---------- SSEL: sub-mode select 0 -> a, 1 -> b
1242 * | | +-------- High Speed: say 0
1243 * | | | +-+-+-- Clock Mode: 0..7
1244 * | | | | | |
1245 * -+-+-+-+-+-+-+-+
1246 * x|x|5|4|3|2|1|0| lower bits
1247 *
1248 * Division factor of BRR: k = (N+1)x2^M (total divider = 16xk in mode 6b)
1249 * +-+-+-+------------------ M (0..15)
1250 * | | | | +-+-+-+-+-+-- N (0..63)
1251 * 0 0 0 0 | | | | 0 0 | | | | | |
1252 * ...-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1253 * f|e|d|c|b|a|9|8|7|6|5|4|3|2|1|0| lower bits
1254 *
1255 */
dscc4_set_clock(struct net_device * dev,u32 * bps,u32 * state)1256 static int dscc4_set_clock(struct net_device *dev, u32 *bps, u32 *state)
1257 {
1258 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1259 int ret = -1;
1260 u32 brr;
1261
1262 *state &= ~Ccr0ClockMask;
1263 if (*bps) { /* Clock generated - required for DCE */
1264 u32 n = 0, m = 0, divider;
1265 int xtal;
1266
1267 xtal = dpriv->pci_priv->xtal_hz;
1268 if (!xtal)
1269 goto done;
1270 if (dscc4_check_clock_ability(dpriv->dev_id) < 0)
1271 goto done;
1272 divider = xtal / *bps;
1273 if (divider > BRR_DIVIDER_MAX) {
1274 divider >>= 4;
1275 *state |= 0x00000036; /* Clock mode 6b (BRG/16) */
1276 } else
1277 *state |= 0x00000037; /* Clock mode 7b (BRG) */
1278 if (divider >> 22) {
1279 n = 63;
1280 m = 15;
1281 } else if (divider) {
1282 /* Extraction of the 6 highest weighted bits */
1283 m = 0;
1284 while (0xffffffc0 & divider) {
1285 m++;
1286 divider >>= 1;
1287 }
1288 n = divider;
1289 }
1290 brr = (m << 8) | n;
1291 divider = n << m;
1292 if (!(*state & 0x00000001)) /* ?b mode mask => clock mode 6b */
1293 divider <<= 4;
1294 *bps = xtal / divider;
1295 } else {
1296 /*
1297 * External clock - DTE
1298 * "state" already reflects Clock mode 0a (CCR0 = 0xzzzzzz00).
1299 * Nothing more to be done
1300 */
1301 brr = 0;
1302 }
1303 scc_writel(brr, dpriv, dev, BRR);
1304 ret = 0;
1305 done:
1306 return ret;
1307 }
1308
dscc4_ioctl(struct net_device * dev,struct ifreq * ifr,int cmd)1309 static int dscc4_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1310 {
1311 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1312 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1313 const size_t size = sizeof(dpriv->settings);
1314 int ret = 0;
1315
1316 if (dev->flags & IFF_UP)
1317 return -EBUSY;
1318
1319 if (cmd != SIOCWANDEV)
1320 return -EOPNOTSUPP;
1321
1322 switch(ifr->ifr_settings.type) {
1323 case IF_GET_IFACE:
1324 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1325 if (ifr->ifr_settings.size < size) {
1326 ifr->ifr_settings.size = size; /* data size wanted */
1327 return -ENOBUFS;
1328 }
1329 if (copy_to_user(line, &dpriv->settings, size))
1330 return -EFAULT;
1331 break;
1332
1333 case IF_IFACE_SYNC_SERIAL:
1334 if (!capable(CAP_NET_ADMIN))
1335 return -EPERM;
1336
1337 if (dpriv->flags & FakeReset) {
1338 printk(KERN_INFO "%s: please reset the device"
1339 " before this command\n", dev->name);
1340 return -EPERM;
1341 }
1342 if (copy_from_user(&dpriv->settings, line, size))
1343 return -EFAULT;
1344 ret = dscc4_set_iface(dpriv, dev);
1345 break;
1346
1347 default:
1348 ret = hdlc_ioctl(dev, ifr, cmd);
1349 break;
1350 }
1351
1352 return ret;
1353 }
1354
dscc4_match(struct thingie * p,int value)1355 static int dscc4_match(struct thingie *p, int value)
1356 {
1357 int i;
1358
1359 for (i = 0; p[i].define != -1; i++) {
1360 if (value == p[i].define)
1361 break;
1362 }
1363 if (p[i].define == -1)
1364 return -1;
1365 else
1366 return i;
1367 }
1368
dscc4_clock_setting(struct dscc4_dev_priv * dpriv,struct net_device * dev)1369 static int dscc4_clock_setting(struct dscc4_dev_priv *dpriv,
1370 struct net_device *dev)
1371 {
1372 sync_serial_settings *settings = &dpriv->settings;
1373 int ret = -EOPNOTSUPP;
1374 u32 bps, state;
1375
1376 bps = settings->clock_rate;
1377 state = scc_readl(dpriv, CCR0);
1378 if (dscc4_set_clock(dev, &bps, &state) < 0)
1379 goto done;
1380 if (bps) { /* DCE */
1381 printk(KERN_DEBUG "%s: generated RxClk (DCE)\n", dev->name);
1382 if (settings->clock_rate != bps) {
1383 printk(KERN_DEBUG "%s: clock adjusted (%08d -> %08d)\n",
1384 dev->name, settings->clock_rate, bps);
1385 settings->clock_rate = bps;
1386 }
1387 } else { /* DTE */
1388 state |= PowerUp | Vis;
1389 printk(KERN_DEBUG "%s: external RxClk (DTE)\n", dev->name);
1390 }
1391 scc_writel(state, dpriv, dev, CCR0);
1392 ret = 0;
1393 done:
1394 return ret;
1395 }
1396
dscc4_encoding_setting(struct dscc4_dev_priv * dpriv,struct net_device * dev)1397 static int dscc4_encoding_setting(struct dscc4_dev_priv *dpriv,
1398 struct net_device *dev)
1399 {
1400 struct thingie encoding[] = {
1401 { ENCODING_NRZ, 0x00000000 },
1402 { ENCODING_NRZI, 0x00200000 },
1403 { ENCODING_FM_MARK, 0x00400000 },
1404 { ENCODING_FM_SPACE, 0x00500000 },
1405 { ENCODING_MANCHESTER, 0x00600000 },
1406 { -1, 0}
1407 };
1408 int i, ret = 0;
1409
1410 i = dscc4_match(encoding, dpriv->encoding);
1411 if (i >= 0)
1412 scc_patchl(EncodingMask, encoding[i].bits, dpriv, dev, CCR0);
1413 else
1414 ret = -EOPNOTSUPP;
1415 return ret;
1416 }
1417
dscc4_loopback_setting(struct dscc4_dev_priv * dpriv,struct net_device * dev)1418 static int dscc4_loopback_setting(struct dscc4_dev_priv *dpriv,
1419 struct net_device *dev)
1420 {
1421 sync_serial_settings *settings = &dpriv->settings;
1422 u32 state;
1423
1424 state = scc_readl(dpriv, CCR1);
1425 if (settings->loopback) {
1426 printk(KERN_DEBUG "%s: loopback\n", dev->name);
1427 state |= 0x00000100;
1428 } else {
1429 printk(KERN_DEBUG "%s: normal\n", dev->name);
1430 state &= ~0x00000100;
1431 }
1432 scc_writel(state, dpriv, dev, CCR1);
1433 return 0;
1434 }
1435
dscc4_crc_setting(struct dscc4_dev_priv * dpriv,struct net_device * dev)1436 static int dscc4_crc_setting(struct dscc4_dev_priv *dpriv,
1437 struct net_device *dev)
1438 {
1439 struct thingie crc[] = {
1440 { PARITY_CRC16_PR0_CCITT, 0x00000010 },
1441 { PARITY_CRC16_PR1_CCITT, 0x00000000 },
1442 { PARITY_CRC32_PR0_CCITT, 0x00000011 },
1443 { PARITY_CRC32_PR1_CCITT, 0x00000001 }
1444 };
1445 int i, ret = 0;
1446
1447 i = dscc4_match(crc, dpriv->parity);
1448 if (i >= 0)
1449 scc_patchl(CrcMask, crc[i].bits, dpriv, dev, CCR1);
1450 else
1451 ret = -EOPNOTSUPP;
1452 return ret;
1453 }
1454
dscc4_set_iface(struct dscc4_dev_priv * dpriv,struct net_device * dev)1455 static int dscc4_set_iface(struct dscc4_dev_priv *dpriv, struct net_device *dev)
1456 {
1457 struct {
1458 int (*action)(struct dscc4_dev_priv *, struct net_device *);
1459 } *p, do_setting[] = {
1460 { dscc4_encoding_setting },
1461 { dscc4_clock_setting },
1462 { dscc4_loopback_setting },
1463 { dscc4_crc_setting },
1464 { NULL }
1465 };
1466 int ret = 0;
1467
1468 for (p = do_setting; p->action; p++) {
1469 if ((ret = p->action(dpriv, dev)) < 0)
1470 break;
1471 }
1472 return ret;
1473 }
1474
dscc4_irq(int irq,void * token)1475 static irqreturn_t dscc4_irq(int irq, void *token)
1476 {
1477 struct dscc4_dev_priv *root = token;
1478 struct dscc4_pci_priv *priv;
1479 struct net_device *dev;
1480 void __iomem *ioaddr;
1481 u32 state;
1482 unsigned long flags;
1483 int i, handled = 1;
1484
1485 priv = root->pci_priv;
1486 dev = dscc4_to_dev(root);
1487
1488 spin_lock_irqsave(&priv->lock, flags);
1489
1490 ioaddr = root->base_addr;
1491
1492 state = readl(ioaddr + GSTAR);
1493 if (!state) {
1494 handled = 0;
1495 goto out;
1496 }
1497 if (debug > 3)
1498 printk(KERN_DEBUG "%s: GSTAR = 0x%08x\n", DRV_NAME, state);
1499 writel(state, ioaddr + GSTAR);
1500
1501 if (state & Arf) {
1502 printk(KERN_ERR "%s: failure (Arf). Harass the maintener\n",
1503 dev->name);
1504 goto out;
1505 }
1506 state &= ~ArAck;
1507 if (state & Cfg) {
1508 if (debug > 0)
1509 printk(KERN_DEBUG "%s: CfgIV\n", DRV_NAME);
1510 if (priv->iqcfg[priv->cfg_cur++%IRQ_RING_SIZE] & cpu_to_le32(Arf))
1511 printk(KERN_ERR "%s: %s failed\n", dev->name, "CFG");
1512 if (!(state &= ~Cfg))
1513 goto out;
1514 }
1515 if (state & RxEvt) {
1516 i = dev_per_card - 1;
1517 do {
1518 dscc4_rx_irq(priv, root + i);
1519 } while (--i >= 0);
1520 state &= ~RxEvt;
1521 }
1522 if (state & TxEvt) {
1523 i = dev_per_card - 1;
1524 do {
1525 dscc4_tx_irq(priv, root + i);
1526 } while (--i >= 0);
1527 state &= ~TxEvt;
1528 }
1529 out:
1530 spin_unlock_irqrestore(&priv->lock, flags);
1531 return IRQ_RETVAL(handled);
1532 }
1533
dscc4_tx_irq(struct dscc4_pci_priv * ppriv,struct dscc4_dev_priv * dpriv)1534 static void dscc4_tx_irq(struct dscc4_pci_priv *ppriv,
1535 struct dscc4_dev_priv *dpriv)
1536 {
1537 struct net_device *dev = dscc4_to_dev(dpriv);
1538 u32 state;
1539 int cur, loop = 0;
1540
1541 try:
1542 cur = dpriv->iqtx_current%IRQ_RING_SIZE;
1543 state = le32_to_cpu(dpriv->iqtx[cur]);
1544 if (!state) {
1545 if (debug > 4)
1546 printk(KERN_DEBUG "%s: Tx ISR = 0x%08x\n", dev->name,
1547 state);
1548 if ((debug > 1) && (loop > 1))
1549 printk(KERN_DEBUG "%s: Tx irq loop=%d\n", dev->name, loop);
1550 if (loop && netif_queue_stopped(dev))
1551 if ((dpriv->tx_current - dpriv->tx_dirty)%TX_RING_SIZE)
1552 netif_wake_queue(dev);
1553
1554 if (netif_running(dev) && dscc4_tx_quiescent(dpriv, dev) &&
1555 !dscc4_tx_done(dpriv))
1556 dscc4_do_tx(dpriv, dev);
1557 return;
1558 }
1559 loop++;
1560 dpriv->iqtx[cur] = 0;
1561 dpriv->iqtx_current++;
1562
1563 if (state_check(state, dpriv, dev, "Tx") < 0)
1564 return;
1565
1566 if (state & SccEvt) {
1567 if (state & Alls) {
1568 struct sk_buff *skb;
1569 struct TxFD *tx_fd;
1570
1571 if (debug > 2)
1572 dscc4_tx_print(dev, dpriv, "Alls");
1573 /*
1574 * DataComplete can't be trusted for Tx completion.
1575 * Cf errata DS5 p.8
1576 */
1577 cur = dpriv->tx_dirty%TX_RING_SIZE;
1578 tx_fd = dpriv->tx_fd + cur;
1579 skb = dpriv->tx_skbuff[cur];
1580 if (skb) {
1581 pci_unmap_single(ppriv->pdev, le32_to_cpu(tx_fd->data),
1582 skb->len, PCI_DMA_TODEVICE);
1583 if (tx_fd->state & FrameEnd) {
1584 dev->stats.tx_packets++;
1585 dev->stats.tx_bytes += skb->len;
1586 }
1587 dev_kfree_skb_irq(skb);
1588 dpriv->tx_skbuff[cur] = NULL;
1589 ++dpriv->tx_dirty;
1590 } else {
1591 if (debug > 1)
1592 printk(KERN_ERR "%s Tx: NULL skb %d\n",
1593 dev->name, cur);
1594 }
1595 /*
1596 * If the driver ends sending crap on the wire, it
1597 * will be way easier to diagnose than the (not so)
1598 * random freeze induced by null sized tx frames.
1599 */
1600 tx_fd->data = tx_fd->next;
1601 tx_fd->state = FrameEnd | TO_STATE_TX(2*DUMMY_SKB_SIZE);
1602 tx_fd->complete = 0x00000000;
1603 tx_fd->jiffies = 0;
1604
1605 if (!(state &= ~Alls))
1606 goto try;
1607 }
1608 /*
1609 * Transmit Data Underrun
1610 */
1611 if (state & Xdu) {
1612 printk(KERN_ERR "%s: XDU. Ask maintainer\n", DRV_NAME);
1613 dpriv->flags = NeedIDT;
1614 /* Tx reset */
1615 writel(MTFi | Rdt,
1616 dpriv->base_addr + 0x0c*dpriv->dev_id + CH0CFG);
1617 writel(Action, dpriv->base_addr + GCMDR);
1618 return;
1619 }
1620 if (state & Cts) {
1621 printk(KERN_INFO "%s: CTS transition\n", dev->name);
1622 if (!(state &= ~Cts)) /* DEBUG */
1623 goto try;
1624 }
1625 if (state & Xmr) {
1626 /* Frame needs to be sent again - FIXME */
1627 printk(KERN_ERR "%s: Xmr. Ask maintainer\n", DRV_NAME);
1628 if (!(state &= ~Xmr)) /* DEBUG */
1629 goto try;
1630 }
1631 if (state & Xpr) {
1632 void __iomem *scc_addr;
1633 unsigned long ring;
1634 int i;
1635
1636 /*
1637 * - the busy condition happens (sometimes);
1638 * - it doesn't seem to make the handler unreliable.
1639 */
1640 for (i = 1; i; i <<= 1) {
1641 if (!(scc_readl_star(dpriv, dev) & SccBusy))
1642 break;
1643 }
1644 if (!i)
1645 printk(KERN_INFO "%s busy in irq\n", dev->name);
1646
1647 scc_addr = dpriv->base_addr + 0x0c*dpriv->dev_id;
1648 /* Keep this order: IDT before IDR */
1649 if (dpriv->flags & NeedIDT) {
1650 if (debug > 2)
1651 dscc4_tx_print(dev, dpriv, "Xpr");
1652 ring = dpriv->tx_fd_dma +
1653 (dpriv->tx_dirty%TX_RING_SIZE)*
1654 sizeof(struct TxFD);
1655 writel(ring, scc_addr + CH0BTDA);
1656 dscc4_do_tx(dpriv, dev);
1657 writel(MTFi | Idt, scc_addr + CH0CFG);
1658 if (dscc4_do_action(dev, "IDT") < 0)
1659 goto err_xpr;
1660 dpriv->flags &= ~NeedIDT;
1661 }
1662 if (dpriv->flags & NeedIDR) {
1663 ring = dpriv->rx_fd_dma +
1664 (dpriv->rx_current%RX_RING_SIZE)*
1665 sizeof(struct RxFD);
1666 writel(ring, scc_addr + CH0BRDA);
1667 dscc4_rx_update(dpriv, dev);
1668 writel(MTFi | Idr, scc_addr + CH0CFG);
1669 if (dscc4_do_action(dev, "IDR") < 0)
1670 goto err_xpr;
1671 dpriv->flags &= ~NeedIDR;
1672 smp_wmb();
1673 /* Activate receiver and misc */
1674 scc_writel(0x08050008, dpriv, dev, CCR2);
1675 }
1676 err_xpr:
1677 if (!(state &= ~Xpr))
1678 goto try;
1679 }
1680 if (state & Cd) {
1681 if (debug > 0)
1682 printk(KERN_INFO "%s: CD transition\n", dev->name);
1683 if (!(state &= ~Cd)) /* DEBUG */
1684 goto try;
1685 }
1686 } else { /* ! SccEvt */
1687 if (state & Hi) {
1688 #ifdef DSCC4_POLLING
1689 while (!dscc4_tx_poll(dpriv, dev));
1690 #endif
1691 printk(KERN_INFO "%s: Tx Hi\n", dev->name);
1692 state &= ~Hi;
1693 }
1694 if (state & Err) {
1695 printk(KERN_INFO "%s: Tx ERR\n", dev->name);
1696 dev->stats.tx_errors++;
1697 state &= ~Err;
1698 }
1699 }
1700 goto try;
1701 }
1702
dscc4_rx_irq(struct dscc4_pci_priv * priv,struct dscc4_dev_priv * dpriv)1703 static void dscc4_rx_irq(struct dscc4_pci_priv *priv,
1704 struct dscc4_dev_priv *dpriv)
1705 {
1706 struct net_device *dev = dscc4_to_dev(dpriv);
1707 u32 state;
1708 int cur;
1709
1710 try:
1711 cur = dpriv->iqrx_current%IRQ_RING_SIZE;
1712 state = le32_to_cpu(dpriv->iqrx[cur]);
1713 if (!state)
1714 return;
1715 dpriv->iqrx[cur] = 0;
1716 dpriv->iqrx_current++;
1717
1718 if (state_check(state, dpriv, dev, "Rx") < 0)
1719 return;
1720
1721 if (!(state & SccEvt)){
1722 struct RxFD *rx_fd;
1723
1724 if (debug > 4)
1725 printk(KERN_DEBUG "%s: Rx ISR = 0x%08x\n", dev->name,
1726 state);
1727 state &= 0x00ffffff;
1728 if (state & Err) { /* Hold or reset */
1729 printk(KERN_DEBUG "%s: Rx ERR\n", dev->name);
1730 cur = dpriv->rx_current%RX_RING_SIZE;
1731 rx_fd = dpriv->rx_fd + cur;
1732 /*
1733 * Presume we're not facing a DMAC receiver reset.
1734 * As We use the rx size-filtering feature of the
1735 * DSCC4, the beginning of a new frame is waiting in
1736 * the rx fifo. I bet a Receive Data Overflow will
1737 * happen most of time but let's try and avoid it.
1738 * Btw (as for RDO) if one experiences ERR whereas
1739 * the system looks rather idle, there may be a
1740 * problem with latency. In this case, increasing
1741 * RX_RING_SIZE may help.
1742 */
1743 //while (dpriv->rx_needs_refill) {
1744 while (!(rx_fd->state1 & Hold)) {
1745 rx_fd++;
1746 cur++;
1747 if (!(cur = cur%RX_RING_SIZE))
1748 rx_fd = dpriv->rx_fd;
1749 }
1750 //dpriv->rx_needs_refill--;
1751 try_get_rx_skb(dpriv, dev);
1752 if (!rx_fd->data)
1753 goto try;
1754 rx_fd->state1 &= ~Hold;
1755 rx_fd->state2 = 0x00000000;
1756 rx_fd->end = cpu_to_le32(0xbabeface);
1757 //}
1758 goto try;
1759 }
1760 if (state & Fi) {
1761 dscc4_rx_skb(dpriv, dev);
1762 goto try;
1763 }
1764 if (state & Hi ) { /* HI bit */
1765 printk(KERN_INFO "%s: Rx Hi\n", dev->name);
1766 state &= ~Hi;
1767 goto try;
1768 }
1769 } else { /* SccEvt */
1770 if (debug > 1) {
1771 //FIXME: verifier la presence de tous les evenements
1772 static struct {
1773 u32 mask;
1774 const char *irq_name;
1775 } evts[] = {
1776 { 0x00008000, "TIN"},
1777 { 0x00000020, "RSC"},
1778 { 0x00000010, "PCE"},
1779 { 0x00000008, "PLLA"},
1780 { 0, NULL}
1781 }, *evt;
1782
1783 for (evt = evts; evt->irq_name; evt++) {
1784 if (state & evt->mask) {
1785 printk(KERN_DEBUG "%s: %s\n",
1786 dev->name, evt->irq_name);
1787 if (!(state &= ~evt->mask))
1788 goto try;
1789 }
1790 }
1791 } else {
1792 if (!(state &= ~0x0000c03c))
1793 goto try;
1794 }
1795 if (state & Cts) {
1796 printk(KERN_INFO "%s: CTS transition\n", dev->name);
1797 if (!(state &= ~Cts)) /* DEBUG */
1798 goto try;
1799 }
1800 /*
1801 * Receive Data Overflow (FIXME: fscked)
1802 */
1803 if (state & Rdo) {
1804 struct RxFD *rx_fd;
1805 void __iomem *scc_addr;
1806 int cur;
1807
1808 //if (debug)
1809 // dscc4_rx_dump(dpriv);
1810 scc_addr = dpriv->base_addr + 0x0c*dpriv->dev_id;
1811
1812 scc_patchl(RxActivate, 0, dpriv, dev, CCR2);
1813 /*
1814 * This has no effect. Why ?
1815 * ORed with TxSccRes, one sees the CFG ack (for
1816 * the TX part only).
1817 */
1818 scc_writel(RxSccRes, dpriv, dev, CMDR);
1819 dpriv->flags |= RdoSet;
1820
1821 /*
1822 * Let's try and save something in the received data.
1823 * rx_current must be incremented at least once to
1824 * avoid HOLD in the BRDA-to-be-pointed desc.
1825 */
1826 do {
1827 cur = dpriv->rx_current++%RX_RING_SIZE;
1828 rx_fd = dpriv->rx_fd + cur;
1829 if (!(rx_fd->state2 & DataComplete))
1830 break;
1831 if (rx_fd->state2 & FrameAborted) {
1832 dev->stats.rx_over_errors++;
1833 rx_fd->state1 |= Hold;
1834 rx_fd->state2 = 0x00000000;
1835 rx_fd->end = cpu_to_le32(0xbabeface);
1836 } else
1837 dscc4_rx_skb(dpriv, dev);
1838 } while (1);
1839
1840 if (debug > 0) {
1841 if (dpriv->flags & RdoSet)
1842 printk(KERN_DEBUG
1843 "%s: no RDO in Rx data\n", DRV_NAME);
1844 }
1845 #ifdef DSCC4_RDO_EXPERIMENTAL_RECOVERY
1846 /*
1847 * FIXME: must the reset be this violent ?
1848 */
1849 #warning "FIXME: CH0BRDA"
1850 writel(dpriv->rx_fd_dma +
1851 (dpriv->rx_current%RX_RING_SIZE)*
1852 sizeof(struct RxFD), scc_addr + CH0BRDA);
1853 writel(MTFi|Rdr|Idr, scc_addr + CH0CFG);
1854 if (dscc4_do_action(dev, "RDR") < 0) {
1855 printk(KERN_ERR "%s: RDO recovery failed(%s)\n",
1856 dev->name, "RDR");
1857 goto rdo_end;
1858 }
1859 writel(MTFi|Idr, scc_addr + CH0CFG);
1860 if (dscc4_do_action(dev, "IDR") < 0) {
1861 printk(KERN_ERR "%s: RDO recovery failed(%s)\n",
1862 dev->name, "IDR");
1863 goto rdo_end;
1864 }
1865 rdo_end:
1866 #endif
1867 scc_patchl(0, RxActivate, dpriv, dev, CCR2);
1868 goto try;
1869 }
1870 if (state & Cd) {
1871 printk(KERN_INFO "%s: CD transition\n", dev->name);
1872 if (!(state &= ~Cd)) /* DEBUG */
1873 goto try;
1874 }
1875 if (state & Flex) {
1876 printk(KERN_DEBUG "%s: Flex. Ttttt...\n", DRV_NAME);
1877 if (!(state &= ~Flex))
1878 goto try;
1879 }
1880 }
1881 }
1882
1883 /*
1884 * I had expected the following to work for the first descriptor
1885 * (tx_fd->state = 0xc0000000)
1886 * - Hold=1 (don't try and branch to the next descripto);
1887 * - No=0 (I want an empty data section, i.e. size=0);
1888 * - Fe=1 (required by No=0 or we got an Err irq and must reset).
1889 * It failed and locked solid. Thus the introduction of a dummy skb.
1890 * Problem is acknowledged in errata sheet DS5. Joy :o/
1891 */
dscc4_init_dummy_skb(struct dscc4_dev_priv * dpriv)1892 static struct sk_buff *dscc4_init_dummy_skb(struct dscc4_dev_priv *dpriv)
1893 {
1894 struct sk_buff *skb;
1895
1896 skb = dev_alloc_skb(DUMMY_SKB_SIZE);
1897 if (skb) {
1898 int last = dpriv->tx_dirty%TX_RING_SIZE;
1899 struct TxFD *tx_fd = dpriv->tx_fd + last;
1900
1901 skb->len = DUMMY_SKB_SIZE;
1902 skb_copy_to_linear_data(skb, version,
1903 strlen(version) % DUMMY_SKB_SIZE);
1904 tx_fd->state = FrameEnd | TO_STATE_TX(DUMMY_SKB_SIZE);
1905 tx_fd->data = cpu_to_le32(pci_map_single(dpriv->pci_priv->pdev,
1906 skb->data, DUMMY_SKB_SIZE,
1907 PCI_DMA_TODEVICE));
1908 dpriv->tx_skbuff[last] = skb;
1909 }
1910 return skb;
1911 }
1912
dscc4_init_ring(struct net_device * dev)1913 static int dscc4_init_ring(struct net_device *dev)
1914 {
1915 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1916 struct pci_dev *pdev = dpriv->pci_priv->pdev;
1917 struct TxFD *tx_fd;
1918 struct RxFD *rx_fd;
1919 void *ring;
1920 int i;
1921
1922 ring = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &dpriv->rx_fd_dma);
1923 if (!ring)
1924 goto err_out;
1925 dpriv->rx_fd = rx_fd = (struct RxFD *) ring;
1926
1927 ring = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &dpriv->tx_fd_dma);
1928 if (!ring)
1929 goto err_free_dma_rx;
1930 dpriv->tx_fd = tx_fd = (struct TxFD *) ring;
1931
1932 memset(dpriv->tx_skbuff, 0, sizeof(struct sk_buff *)*TX_RING_SIZE);
1933 dpriv->tx_dirty = 0xffffffff;
1934 i = dpriv->tx_current = 0;
1935 do {
1936 tx_fd->state = FrameEnd | TO_STATE_TX(2*DUMMY_SKB_SIZE);
1937 tx_fd->complete = 0x00000000;
1938 /* FIXME: NULL should be ok - to be tried */
1939 tx_fd->data = cpu_to_le32(dpriv->tx_fd_dma);
1940 (tx_fd++)->next = cpu_to_le32(dpriv->tx_fd_dma +
1941 (++i%TX_RING_SIZE)*sizeof(*tx_fd));
1942 } while (i < TX_RING_SIZE);
1943
1944 if (!dscc4_init_dummy_skb(dpriv))
1945 goto err_free_dma_tx;
1946
1947 memset(dpriv->rx_skbuff, 0, sizeof(struct sk_buff *)*RX_RING_SIZE);
1948 i = dpriv->rx_dirty = dpriv->rx_current = 0;
1949 do {
1950 /* size set by the host. Multiple of 4 bytes please */
1951 rx_fd->state1 = HiDesc;
1952 rx_fd->state2 = 0x00000000;
1953 rx_fd->end = cpu_to_le32(0xbabeface);
1954 rx_fd->state1 |= TO_STATE_RX(HDLC_MAX_MRU);
1955 // FIXME: return value verifiee mais traitement suspect
1956 if (try_get_rx_skb(dpriv, dev) >= 0)
1957 dpriv->rx_dirty++;
1958 (rx_fd++)->next = cpu_to_le32(dpriv->rx_fd_dma +
1959 (++i%RX_RING_SIZE)*sizeof(*rx_fd));
1960 } while (i < RX_RING_SIZE);
1961
1962 return 0;
1963
1964 err_free_dma_tx:
1965 pci_free_consistent(pdev, TX_TOTAL_SIZE, ring, dpriv->tx_fd_dma);
1966 err_free_dma_rx:
1967 pci_free_consistent(pdev, RX_TOTAL_SIZE, rx_fd, dpriv->rx_fd_dma);
1968 err_out:
1969 return -ENOMEM;
1970 }
1971
dscc4_remove_one(struct pci_dev * pdev)1972 static void __devexit dscc4_remove_one(struct pci_dev *pdev)
1973 {
1974 struct dscc4_pci_priv *ppriv;
1975 struct dscc4_dev_priv *root;
1976 void __iomem *ioaddr;
1977 int i;
1978
1979 ppriv = pci_get_drvdata(pdev);
1980 root = ppriv->root;
1981
1982 ioaddr = root->base_addr;
1983
1984 dscc4_pci_reset(pdev, ioaddr);
1985
1986 free_irq(pdev->irq, root);
1987 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32), ppriv->iqcfg,
1988 ppriv->iqcfg_dma);
1989 for (i = 0; i < dev_per_card; i++) {
1990 struct dscc4_dev_priv *dpriv = root + i;
1991
1992 dscc4_release_ring(dpriv);
1993 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32),
1994 dpriv->iqrx, dpriv->iqrx_dma);
1995 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32),
1996 dpriv->iqtx, dpriv->iqtx_dma);
1997 }
1998
1999 dscc4_free1(pdev);
2000
2001 iounmap(ioaddr);
2002
2003 pci_release_region(pdev, 1);
2004 pci_release_region(pdev, 0);
2005
2006 pci_disable_device(pdev);
2007 }
2008
dscc4_hdlc_attach(struct net_device * dev,unsigned short encoding,unsigned short parity)2009 static int dscc4_hdlc_attach(struct net_device *dev, unsigned short encoding,
2010 unsigned short parity)
2011 {
2012 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
2013
2014 if (encoding != ENCODING_NRZ &&
2015 encoding != ENCODING_NRZI &&
2016 encoding != ENCODING_FM_MARK &&
2017 encoding != ENCODING_FM_SPACE &&
2018 encoding != ENCODING_MANCHESTER)
2019 return -EINVAL;
2020
2021 if (parity != PARITY_NONE &&
2022 parity != PARITY_CRC16_PR0_CCITT &&
2023 parity != PARITY_CRC16_PR1_CCITT &&
2024 parity != PARITY_CRC32_PR0_CCITT &&
2025 parity != PARITY_CRC32_PR1_CCITT)
2026 return -EINVAL;
2027
2028 dpriv->encoding = encoding;
2029 dpriv->parity = parity;
2030 return 0;
2031 }
2032
2033 #ifndef MODULE
dscc4_setup(char * str)2034 static int __init dscc4_setup(char *str)
2035 {
2036 int *args[] = { &debug, &quartz, NULL }, **p = args;
2037
2038 while (*p && (get_option(&str, *p) == 2))
2039 p++;
2040 return 1;
2041 }
2042
2043 __setup("dscc4.setup=", dscc4_setup);
2044 #endif
2045
2046 static struct pci_device_id dscc4_pci_tbl[] = {
2047 { PCI_VENDOR_ID_SIEMENS, PCI_DEVICE_ID_SIEMENS_DSCC4,
2048 PCI_ANY_ID, PCI_ANY_ID, },
2049 { 0,}
2050 };
2051 MODULE_DEVICE_TABLE(pci, dscc4_pci_tbl);
2052
2053 static struct pci_driver dscc4_driver = {
2054 .name = DRV_NAME,
2055 .id_table = dscc4_pci_tbl,
2056 .probe = dscc4_init_one,
2057 .remove = __devexit_p(dscc4_remove_one),
2058 };
2059
dscc4_init_module(void)2060 static int __init dscc4_init_module(void)
2061 {
2062 return pci_register_driver(&dscc4_driver);
2063 }
2064
dscc4_cleanup_module(void)2065 static void __exit dscc4_cleanup_module(void)
2066 {
2067 pci_unregister_driver(&dscc4_driver);
2068 }
2069
2070 module_init(dscc4_init_module);
2071 module_exit(dscc4_cleanup_module);
2072