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Searched refs:reg0 (Results 1 – 25 of 27) sorted by relevance

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/drivers/sbus/char/
Djsflash.c460 struct linux_prom_registers reg0; in jsflash_init() local
466 (char *)&reg0, sizeof(reg0)) == -1) { in jsflash_init()
470 if (reg0.which_io != 0) { in jsflash_init()
472 reg0.which_io, reg0.phys_addr); in jsflash_init()
480 if ((reg0.phys_addr >> 24) != 0x20) { in jsflash_init()
482 reg0.which_io, reg0.phys_addr); in jsflash_init()
486 if ((int)reg0.reg_size <= 0) { in jsflash_init()
487 printk("jsflash: bad size 0x%x\n", (int)reg0.reg_size); in jsflash_init()
498 reg0.which_io = 0; in jsflash_init()
499 reg0.phys_addr = 0x20400000; in jsflash_init()
[all …]
/drivers/media/dvb/frontends/
Dves1820.c42 u8 reg0; member
93 static int ves1820_setup_reg0(struct ves1820_state *state, u8 reg0, fe_spectral_inversion_t inversi… in ves1820_setup_reg0() argument
95 reg0 |= state->reg0 & 0x62; in ves1820_setup_reg0()
98 if (!state->config->invert) reg0 |= 0x20; in ves1820_setup_reg0()
99 else reg0 &= ~0x20; in ves1820_setup_reg0()
101 if (!state->config->invert) reg0 &= ~0x20; in ves1820_setup_reg0()
102 else reg0 |= 0x20; in ves1820_setup_reg0()
105 ves1820_writereg(state, 0x00, reg0 & 0xfe); in ves1820_setup_reg0()
106 ves1820_writereg(state, 0x00, reg0 | 0x01); in ves1820_setup_reg0()
108 state->reg0 = reg0; in ves1820_setup_reg0()
[all …]
Dtda10021.c43 u8 reg0; member
132 static int tda10021_setup_reg0 (struct tda10021_state* state, u8 reg0, in tda10021_setup_reg0() argument
135 reg0 |= state->reg0 & 0x63; in tda10021_setup_reg0()
138 reg0 &= ~0x20; in tda10021_setup_reg0()
140 reg0 |= 0x20; in tda10021_setup_reg0()
142 _tda10021_writereg (state, 0x00, reg0 & 0xfe); in tda10021_setup_reg0()
143 _tda10021_writereg (state, 0x00, reg0 | 0x01); in tda10021_setup_reg0()
145 state->reg0 = reg0; in tda10021_setup_reg0()
366 …p->inversion = ((state->reg0 & 0x20) == 0x20) ^ (state->config->invert != 0) ? INVERSION_ON : INVE… in tda10021_get_frontend()
367 p->u.qam.modulation = ((state->reg0 >> 2) & 7) + QAM_16; in tda10021_get_frontend()
[all …]
Dtua6100.c55 u8 reg0[] = { 0x00, 0x00 }; in tua6100_sleep() local
56 struct i2c_msg msg = { .addr = priv->i2c_address, .flags = 0, .buf = reg0, .len = 2 }; in tua6100_sleep()
75 u8 reg0[] = { 0x00, 0x00 }; in tua6100_set_params() local
78 struct i2c_msg msg0 = { .addr = priv->i2c_address, .flags = 0, .buf = reg0, .len = 2 }; in tua6100_set_params()
88 reg0[1] = 0x03; in tua6100_set_params()
90 reg0[1] = 0x07; in tua6100_set_params()
Dtda10023.c50 u8 reg0; member
158 static int tda10023_setup_reg0 (struct tda10023_state* state, u8 reg0) in tda10023_setup_reg0() argument
160 reg0 |= state->reg0 & 0x63; in tda10023_setup_reg0()
162 tda10023_writereg (state, 0x00, reg0 & 0xfe); in tda10023_setup_reg0()
163 tda10023_writereg (state, 0x00, reg0 | 0x01); in tda10023_setup_reg0()
165 state->reg0 = reg0; in tda10023_setup_reg0()
440 p->u.qam.modulation = ((state->reg0 >> 2) & 7) + QAM_16; in tda10023_get_frontend()
503 state->reg0 = REG0_INIT_VAL; in tda10023_attach()
/drivers/net/tokenring/
Dmadgemc.c521 unsigned int reg0; in madgemc_setsifsel() local
523 reg0 = inb(dev->base_addr + MC_CONTROL_REG0); in madgemc_setsifsel()
524 if ((val == 0) && (reg0 & MC_CONTROL_REG0_SIFSEL)) { in madgemc_setsifsel()
525 outb(reg0 ^ MC_CONTROL_REG0_SIFSEL, in madgemc_setsifsel()
528 outb(reg0 | MC_CONTROL_REG0_SIFSEL, in madgemc_setsifsel()
531 reg0 = inb(dev->base_addr + MC_CONTROL_REG0); in madgemc_setsifsel()
635 unsigned char reg0, reg1, tmpreg0, i; in madgemc_read_rom() local
639 reg0 = inb(ioaddr + MC_CONTROL_REG0); in madgemc_read_rom()
643 tmpreg0 = reg0 & ~(MC_CONTROL_REG0_PAGE + MC_CONTROL_REG0_SIFSEL); in madgemc_read_rom()
659 outb(reg0, ioaddr + MC_CONTROL_REG0); in madgemc_read_rom()
/drivers/net/
Dsmc-ultra32.c251 ei_status.reg0 = inb(ioaddr + ULTRA32_CFG3) & 0xfc; in ultra32_probe1()
253 dev->mem_start = 0xc0000 + ((ei_status.reg0 & 0x7c) << 11); in ultra32_probe1()
357 outb(ei_status.reg0 | ((ring_page & 0x60) >> 5), RamReg); in ultra32_get_8390_hdr()
389 outb(ei_status.reg0 | ((ring_offset & 0x6000) >> 13), RamReg); in ultra32_block_input()
393 outb(ei_status.reg0, RamReg); in ultra32_block_input()
410 outb(ei_status.reg0, RamReg); in ultra32_block_output()
Dwd.c259 int reg0 = inb(ioaddr); in wd_probe1() local
260 if (reg0 == 0xff || reg0 == 0) { in wd_probe1()
269 dev->mem_start = ((reg0&0x3f) << 13) + (high_addr_bits << 19); in wd_probe1()
373 ei_status.reg0 = ((dev->mem_start>>13) & 0x3f) | WD_MEMENB; in wd_open()
378 outb(ei_status.reg0, ioaddr); /* WD_CMDREG */ in wd_open()
487 outb(ei_status.reg0 & ~WD_MEMENB, wd_cmdreg); in wd_close()
Dne2k-pci.c96 #define ne2k_flags reg0
225 int irq, reg0, chip_idx = ent->driver_data; in ne2k_pci_init_one() local
257 reg0 = inb(ioaddr); in ne2k_pci_init_one()
258 if (reg0 == 0xFF) in ne2k_pci_init_one()
270 outb(reg0, ioaddr); in ne2k_pci_init_one()
Dstarfire.c1118 u16 reg0; in check_duplex() local
1131 reg0 = mdio_read(dev, np->phys[0], MII_BMCR); in check_duplex()
1134 reg0 |= BMCR_ANENABLE | BMCR_ANRESTART; in check_duplex()
1136 reg0 &= ~(BMCR_ANENABLE | BMCR_ANRESTART); in check_duplex()
1138 reg0 |= BMCR_SPEED100; in check_duplex()
1140 reg0 |= BMCR_FULLDPLX; in check_duplex()
1146 mdio_write(dev, np->phys[0], MII_BMCR, reg0); in check_duplex()
1636 u16 reg0, reg1, reg4, reg5; in netdev_media_change() local
1644 reg0 = mdio_read(dev, np->phys[0], MII_BMCR); in netdev_media_change()
1649 if (reg0 & BMCR_ANENABLE) { in netdev_media_change()
[all …]
Dne-h8300.c219 int reg0, ret; in ne_probe1() local
227 reg0 = inb_p(ioaddr); in ne_probe1()
228 if (reg0 == 0xFF) { in ne_probe1()
242 outb_p(reg0, ioaddr + EI_SHIFT(0)); in ne_probe1()
Dne.c295 int reg0, ret; in ne_probe1() local
301 reg0 = inb_p(ioaddr); in ne_probe1()
302 if (reg0 == 0xFF) { in ne_probe1()
316 outb_p(reg0, ioaddr); in ne_probe1()
Dax88796.c116 int reg0; in ax_initial_check() local
119 reg0 = ei_inb(ioaddr); in ax_initial_check()
120 if (reg0 == 0xFF) in ax_initial_check()
129 ei_outb(reg0, ioaddr); in ax_initial_check()
D8390.h97 unsigned char reg0; /* Register '0' in a WD8013 */ member
Dac3200.c268 if (ei_status.reg0) in ac_probe1()
Dlne390.c286 if (ei_status.reg0) in lne390_probe1()
/drivers/s390/crypto/
Dap_bus.c120 register unsigned long reg0 asm ("0") = AP_MKQID(0,0); in ap_instructions_available()
129 : "+d" (reg0), "+d" (reg1), "+d" (reg2) : : "cc" ); in ap_instructions_available()
161 register unsigned long reg0 asm ("0") = qid; in ap_test_queue()
166 : "+d" (reg0), "=d" (reg1), "+d" (reg2) : : "cc"); in ap_test_queue()
180 register unsigned long reg0 asm ("0") = qid | 0x01000000UL; in ap_reset_queue()
186 : "+d" (reg0), "=d" (reg1), "+d" (reg2) : : "cc"); in ap_reset_queue()
201 register unsigned long reg0 asm ("0") = qid | 0x03000000UL; in ap_queue_interruption_control()
207 : "+d" (reg0), "+d" (reg1_in), "=d" (reg1_out), "+d" (reg2) in ap_queue_interruption_control()
280 register unsigned long reg0 asm ("0") = qid | 0x40000000UL; in __ap_send()
290 : "+d" (reg0), "=d" (reg1), "+d" (reg2), "+d" (reg3) in __ap_send()
[all …]
/drivers/media/video/zoran/
Dzoran_procfs.c95 int i = 0, reg0, reg, val; in setparam() local
99 reg = reg0 = btread(zr67[i].reg); in setparam()
110 ZR_DEVNAME(zr), zr67[i].reg, reg0, reg, in setparam()
/drivers/staging/agnx/
Dsta.h50 __le32 reg0; member
90 __le32 reg0; member
Ddebug.h61 reg = be32_to_cpu(hdr->reg0); in agnx_print_hdr()
197 reg = le32_to_cpu(tx_wq.reg0); in agnx_print_sta_tx_wq()
221 reg = le32_to_cpu(traffic->reg0); in agnx_print_sta_traffic()
Dxmit.h44 __be32 reg0; member
Dsta.c185 traffic->reg0 = cpu_to_le32(reg); in sta_traffic_init()
/drivers/gpu/drm/r128/
Dr128_drv.h407 #define CCE_PACKET1( reg0, reg1 ) (R128_CCE_PACKET1 | \ argument
408 (((reg1) >> 2) << 11) | ((reg0) >> 2))
/drivers/gpu/drm/mga/
Dmga_drv.h344 #define DMA_BLOCK( reg0, val0, reg1, val1, reg2, val2, reg3, val3 ) \ argument
346 DMA_WRITE( 0, ((DMAREG( reg0 ) << 0) | \
/drivers/gpu/drm/radeon/
Dradeon_drv.h1254 #define CP_PACKET1( reg0, reg1 ) \ argument
1255 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2))

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