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Searched refs:bfin_write_SIC_IWR1 (Results 1 – 8 of 8) sorted by relevance

/arch/blackfin/mach-common/
Dclocks-init.c52 bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11)); in init_clocks()
54 bfin_write_SIC_IWR1(IWR_DISABLE_ALL); in init_clocks()
Dpm.c94 bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11)); in bfin_pm_suspend_standby_enter()
96 bfin_write_SIC_IWR1(IWR_DISABLE_ALL); in bfin_pm_suspend_standby_enter()
Dints-priority.c1128 bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
1130 bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
/arch/blackfin/mach-bf561/include/mach/
Dblackfin.h58 #define bfin_write_SIC_IWR1 bfin_write_SICA_IWR1 macro
/arch/blackfin/mach-bf518/include/mach/
DcdefBF51x_base.h103 #define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val) macro
/arch/blackfin/mach-bf527/include/mach/
DcdefBF52x_base.h103 #define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val) macro
/arch/blackfin/mach-bf538/include/mach/
DcdefBF538.h75 #define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val) macro
/arch/blackfin/mach-bf548/include/mach/
DcdefBF54x_base.h88 #define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val) macro