| /arch/mips/include/asm/ |
| D | gic.h | 153 #define GIC_SH_MAP_TO_PIN(intr) \ argument
154 (GIC_SH_INTR_MAP_TO_PIN_BASE_OFS + (4 * intr))
159 #define GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe) \ argument
160 (GIC_SH_INTR_MAP_TO_VPE_BASE_OFS + (32 * (intr)) + (((vpe) / 32) * 4))
165 #define GIC_SET_POLARITY(intr, pol) \ argument
166 GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_POLARITY_OFS + (((intr) / 32) * 4)), (pol) << ((intr) % 32))
170 #define GIC_SET_TRIGGER(intr, trig) \ argument
171 GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_TRIGGER_OFS + (((intr) / 32) * 4)), (trig) << ((intr) % 32))
175 #define GIC_SET_INTR_MASK(intr, val) \ argument
176 GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_SMASK_OFS + (((intr) / 32) * 4)), ((val) << ((intr) % 32)))
[all …]
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| /arch/powerpc/platforms/52xx/ |
| D | mpc52xx_pic.c | 133 static struct mpc52xx_intr __iomem *intr; variable
168 io_be_clrbit(&intr->ctrl, 11 - l2irq); in mpc52xx_extirq_mask()
181 io_be_setbit(&intr->ctrl, 11 - l2irq); in mpc52xx_extirq_unmask()
194 io_be_setbit(&intr->ctrl, 27-l2irq); in mpc52xx_extirq_ack()
231 ctrl_reg = in_be32(&intr->ctrl); in mpc52xx_extirq_set_type()
234 out_be32(&intr->ctrl, ctrl_reg); in mpc52xx_extirq_set_type()
260 io_be_setbit(&intr->main_mask, 16 - l2irq); in mpc52xx_main_mask()
273 io_be_clrbit(&intr->main_mask, 16 - l2irq); in mpc52xx_main_unmask()
296 io_be_setbit(&intr->per_mask, 31 - l2irq); in mpc52xx_periph_mask()
309 io_be_clrbit(&intr->per_mask, 31 - l2irq); in mpc52xx_periph_unmask()
[all …]
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| D | mpc52xx_pm.c | 19 static struct mpc52xx_intr __iomem *intr; variable
79 intr = mbar + 0x500; in mpc52xx_pm_prepare()
113 intr_main_mask = in_be32(&intr->main_mask); in mpc52xx_pm_enter()
114 out_be32(&intr->main_mask, intr_main_mask | 0x1ffff); in mpc52xx_pm_enter()
147 mpc52xx_deep_sleep(sram, sdram, cdm, intr); in mpc52xx_pm_enter()
169 out_be32(&intr->main_mask, intr_main_mask); in mpc52xx_pm_enter()
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| /arch/mips/kernel/ |
| D | irq-gic.c | 30 void gic_send_ipi(unsigned int intr) in gic_send_ipi() argument
39 GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), 0x80000000 | intr); in gic_send_ipi()
209 static void __init setup_intr(unsigned int intr, unsigned int cpu, in setup_intr() argument
214 GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_PIN(intr)), pin); in setup_intr()
218 GIC_SH_MAP_TO_VPE_REG_OFF(intr, cpu)), in setup_intr()
222 GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_PIN(intr)), in setup_intr()
225 GIC_SH_MAP_TO_VPE_SMASK(intr, cpu); in setup_intr()
229 GIC_SET_POLARITY(intr, polarity); in setup_intr()
232 GIC_SET_TRIGGER(intr, trigtype); in setup_intr()
235 GIC_SET_INTR_MASK(intr, 0); in setup_intr()
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| /arch/ia64/hp/sim/ |
| D | hpsim_setup.c | 29 ia64_ssc_connect_irq (long intr, long irq) in ia64_ssc_connect_irq() argument
31 ia64_ssc(intr, irq, 0, 0, SSC_CONNECT_INTERRUPT); in ia64_ssc_connect_irq()
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| /arch/mips/pci/ |
| D | ops-msc.c | 51 u32 intr; in msc_pcibios_config_access() local
70 MSC_READ(MSC01_PCI_INTSTAT, intr); in msc_pcibios_config_access()
71 if (intr & (MSC01_PCI_INTCFG_MA_BIT | MSC01_PCI_INTCFG_TA_BIT)) { in msc_pcibios_config_access()
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| D | ops-gt64xxx_pci0.c | 46 u32 intr; in gt64xxx_pci0_pcibios_config_access() local
83 intr = GT_READ(GT_INTRCAUSE_OFS); in gt64xxx_pci0_pcibios_config_access()
85 if (intr & (GT_INTRCAUSE_MASABORT0_BIT | GT_INTRCAUSE_TARABORT0_BIT)) { in gt64xxx_pci0_pcibios_config_access()
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| D | ops-pmcmsp.c | 136 int intr; in gen_pci_cfg_wr() local
169 intr = preg->if_status; in gen_pci_cfg_wr()
385 unsigned long intr; in msp_pcibios_config_access() local
458 intr = preg->if_status; in msp_pcibios_config_access()
464 if (intr & ~(BPCI_IFSTATUS_BC0F | BPCI_IFSTATUS_BC1F)) { in msp_pcibios_config_access()
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| /arch/cris/include/arch-v32/arch/hwregs/ |
| D | dma.h | 22 unsigned intr : 1; member
40 unsigned intr : 1; member
62 unsigned intr : 1; member
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| D | dma_defs.h | 107 unsigned int intr : 1; member
158 unsigned int intr : 1; member
258 unsigned int intr : 1; member
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| /arch/arm/mach-pxa/include/mach/ |
| D | pxa27x-udc.h | 40 #define UDCICR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2)) argument
49 #define UDCISR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2)) argument
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| /arch/ia64/include/asm/ |
| D | hpsim.h | 13 void ia64_ssc_connect_irq(long intr, long irq);
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| /arch/ia64/include/asm/sn/ |
| D | sn_sal.h | 409 ia64_sn_console_intr_enable(u64 intr) in ia64_sn_console_intr_enable() argument
418 intr, SAL_CONSOLE_INTR_ON, in ia64_sn_console_intr_enable()
426 ia64_sn_console_intr_disable(u64 intr) in ia64_sn_console_intr_disable() argument
435 intr, SAL_CONSOLE_INTR_OFF, in ia64_sn_console_intr_disable()
877 ia64_sn_irtr_intr_enable(nasid_t nasid, int subch, u64 intr) in ia64_sn_irtr_intr_enable() argument
881 (u64) nasid, (u64) subch, intr, 0, 0, 0); in ia64_sn_irtr_intr_enable()
890 ia64_sn_irtr_intr_disable(nasid_t nasid, int subch, u64 intr) in ia64_sn_irtr_intr_disable() argument
894 (u64) nasid, (u64) subch, intr, 0, 0, 0); in ia64_sn_irtr_intr_disable()
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| /arch/cris/arch-v32/drivers/mach-a3/ |
| D | gpio.c | 201 int intr = bit % 8; in gpio_set_alarm() local
209 intr_cfg |= (regk_gio_hi << (intr * 3)); in gpio_set_alarm()
210 mask |= 1 << intr; in gpio_set_alarm()
212 pins |= pin << (intr * 4); in gpio_set_alarm()
214 intr_cfg |= (regk_gio_lo << (intr * 3)); in gpio_set_alarm()
215 mask |= 1 << intr; in gpio_set_alarm()
217 pins |= pin << (intr * 4); in gpio_set_alarm()
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| /arch/sparc/kernel/ |
| D | of_device_32.c | 472 const struct linux_prom_irqs *intr; in scan_one_device() local
491 intr = of_get_property(dp, "intr", &len); in scan_one_device()
492 if (intr) { in scan_one_device()
495 op->irqs[i] = intr[i].pri; in scan_one_device()
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| /arch/mips/sgi-ip27/ |
| D | TODO | 17 This might need to change later. Only the timer intr is set up to be
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| /arch/cris/arch-v32/drivers/ |
| D | cryptocop.c | 340 cdesc->dma_descr->intr = 0; in alloc_cdesc()
491 key_desc->dma_descr->intr = 0; in setup_key_dl_desc()
522 iv_desc->dma_descr->intr = 0; in setup_cipher_iv_desc()
1303 current_in_cdesc->dma_descr->intr = 1; in cryptocop_setup_dma_list()
1310 (*int_op)->ctx_out.intr = 0; in cryptocop_setup_dma_list()
1324 (*int_op)->ctx_in.intr = 0; in cryptocop_setup_dma_list()
3195 td->intr); in print_dma_descriptors()
3223 td->intr); in print_dma_descriptors()
3406 dd->intr); in print_user_dma_lists()
3437 dd->intr); in print_user_dma_lists()
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| D | sync_serial.c | 372 port->out_descr[i].intr = 1; in initialize_port()
1228 port->active_tr_descr->intr = 1; in start_dma_out()
1275 port->in_descr[i].intr = 1; in start_dma_in()
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| /arch/powerpc/boot/dts/ |
| D | sbc8349.dts | 258 * interrupts cell = <intr #, sense>
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| D | asp834x-redboot.dts | 287 * interrupts cell = <intr #, sense>
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| D | mpc8378_rdb.dts | 291 * interrupts cell = <intr #, sense>
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| D | mpc8315erdb.dts | 303 * interrupts cell = <intr #, sense>
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| D | mpc8377_rdb.dts | 307 * interrupts cell = <intr #, sense>
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| D | mpc8379_rdb.dts | 320 * interrupts cell = <intr #, sense>
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| D | mpc8313erdb.dts | 268 * interrupts cell = <intr #, sense>
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