1/* 2 * SBC8349E Device Tree Source 3 * 4 * Copyright 2007 Wind River Inc. 5 * 6 * Paul Gortmaker (see MAINTAINERS for contact information) 7 * 8 * -based largely on the Freescale MPC834x_MDS dts. 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License as published by the 12 * Free Software Foundation; either version 2 of the License, or (at your 13 * option) any later version. 14 */ 15 16/dts-v1/; 17 18/ { 19 model = "SBC8349E"; 20 compatible = "SBC834xE"; 21 #address-cells = <1>; 22 #size-cells = <1>; 23 24 aliases { 25 ethernet0 = &enet0; 26 ethernet1 = &enet1; 27 serial0 = &serial0; 28 serial1 = &serial1; 29 pci0 = &pci0; 30 }; 31 32 cpus { 33 #address-cells = <1>; 34 #size-cells = <0>; 35 36 PowerPC,8349@0 { 37 device_type = "cpu"; 38 reg = <0x0>; 39 d-cache-line-size = <32>; 40 i-cache-line-size = <32>; 41 d-cache-size = <32768>; 42 i-cache-size = <32768>; 43 timebase-frequency = <0>; // from bootloader 44 bus-frequency = <0>; // from bootloader 45 clock-frequency = <0>; // from bootloader 46 }; 47 }; 48 49 memory { 50 device_type = "memory"; 51 reg = <0x00000000 0x10000000>; // 256MB at 0 52 }; 53 54 soc8349@e0000000 { 55 #address-cells = <1>; 56 #size-cells = <1>; 57 device_type = "soc"; 58 ranges = <0x0 0xe0000000 0x00100000>; 59 reg = <0xe0000000 0x00000200>; 60 bus-frequency = <0>; 61 62 wdt@200 { 63 compatible = "mpc83xx_wdt"; 64 reg = <0x200 0x100>; 65 }; 66 67 i2c@3000 { 68 #address-cells = <1>; 69 #size-cells = <0>; 70 cell-index = <0>; 71 compatible = "fsl-i2c"; 72 reg = <0x3000 0x100>; 73 interrupts = <14 0x8>; 74 interrupt-parent = <&ipic>; 75 dfsrr; 76 }; 77 78 i2c@3100 { 79 #address-cells = <1>; 80 #size-cells = <0>; 81 cell-index = <1>; 82 compatible = "fsl-i2c"; 83 reg = <0x3100 0x100>; 84 interrupts = <15 0x8>; 85 interrupt-parent = <&ipic>; 86 dfsrr; 87 }; 88 89 spi@7000 { 90 cell-index = <0>; 91 compatible = "fsl,spi"; 92 reg = <0x7000 0x1000>; 93 interrupts = <16 0x8>; 94 interrupt-parent = <&ipic>; 95 mode = "cpu"; 96 }; 97 98 dma@82a8 { 99 #address-cells = <1>; 100 #size-cells = <1>; 101 compatible = "fsl,mpc8349-dma", "fsl,elo-dma"; 102 reg = <0x82a8 4>; 103 ranges = <0 0x8100 0x1a8>; 104 interrupt-parent = <&ipic>; 105 interrupts = <71 8>; 106 cell-index = <0>; 107 dma-channel@0 { 108 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; 109 reg = <0 0x80>; 110 cell-index = <0>; 111 interrupt-parent = <&ipic>; 112 interrupts = <71 8>; 113 }; 114 dma-channel@80 { 115 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; 116 reg = <0x80 0x80>; 117 cell-index = <1>; 118 interrupt-parent = <&ipic>; 119 interrupts = <71 8>; 120 }; 121 dma-channel@100 { 122 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; 123 reg = <0x100 0x80>; 124 cell-index = <2>; 125 interrupt-parent = <&ipic>; 126 interrupts = <71 8>; 127 }; 128 dma-channel@180 { 129 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; 130 reg = <0x180 0x28>; 131 cell-index = <3>; 132 interrupt-parent = <&ipic>; 133 interrupts = <71 8>; 134 }; 135 }; 136 137 /* phy type (ULPI or SERIAL) are only types supported for MPH */ 138 /* port = 0 or 1 */ 139 usb@22000 { 140 compatible = "fsl-usb2-mph"; 141 reg = <0x22000 0x1000>; 142 #address-cells = <1>; 143 #size-cells = <0>; 144 interrupt-parent = <&ipic>; 145 interrupts = <39 0x8>; 146 phy_type = "ulpi"; 147 port1; 148 }; 149 /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */ 150 usb@23000 { 151 device_type = "usb"; 152 compatible = "fsl-usb2-dr"; 153 reg = <0x23000 0x1000>; 154 #address-cells = <1>; 155 #size-cells = <0>; 156 interrupt-parent = <&ipic>; 157 interrupts = <38 0x8>; 158 dr_mode = "otg"; 159 phy_type = "ulpi"; 160 }; 161 162 mdio@24520 { 163 #address-cells = <1>; 164 #size-cells = <0>; 165 compatible = "fsl,gianfar-mdio"; 166 reg = <0x24520 0x20>; 167 168 phy0: ethernet-phy@19 { 169 interrupt-parent = <&ipic>; 170 interrupts = <20 0x8>; 171 reg = <0x19>; 172 device_type = "ethernet-phy"; 173 }; 174 phy1: ethernet-phy@1a { 175 interrupt-parent = <&ipic>; 176 interrupts = <21 0x8>; 177 reg = <0x1a>; 178 device_type = "ethernet-phy"; 179 }; 180 tbi0: tbi-phy@11 { 181 reg = <0x11>; 182 device_type = "tbi-phy"; 183 }; 184 }; 185 186 mdio@25520 { 187 #address-cells = <1>; 188 #size-cells = <0>; 189 compatible = "fsl,gianfar-tbi"; 190 reg = <0x25520 0x20>; 191 192 tbi1: tbi-phy@11 { 193 reg = <0x11>; 194 device_type = "tbi-phy"; 195 }; 196 }; 197 198 enet0: ethernet@24000 { 199 cell-index = <0>; 200 device_type = "network"; 201 model = "TSEC"; 202 compatible = "gianfar"; 203 reg = <0x24000 0x1000>; 204 local-mac-address = [ 00 00 00 00 00 00 ]; 205 interrupts = <32 0x8 33 0x8 34 0x8>; 206 interrupt-parent = <&ipic>; 207 tbi-handle = <&tbi0>; 208 phy-handle = <&phy0>; 209 linux,network-index = <0>; 210 }; 211 212 enet1: ethernet@25000 { 213 cell-index = <1>; 214 device_type = "network"; 215 model = "TSEC"; 216 compatible = "gianfar"; 217 reg = <0x25000 0x1000>; 218 local-mac-address = [ 00 00 00 00 00 00 ]; 219 interrupts = <35 0x8 36 0x8 37 0x8>; 220 interrupt-parent = <&ipic>; 221 tbi-handle = <&tbi1>; 222 phy-handle = <&phy1>; 223 linux,network-index = <1>; 224 }; 225 226 serial0: serial@4500 { 227 cell-index = <0>; 228 device_type = "serial"; 229 compatible = "ns16550"; 230 reg = <0x4500 0x100>; 231 clock-frequency = <0>; 232 interrupts = <9 0x8>; 233 interrupt-parent = <&ipic>; 234 }; 235 236 serial1: serial@4600 { 237 cell-index = <1>; 238 device_type = "serial"; 239 compatible = "ns16550"; 240 reg = <0x4600 0x100>; 241 clock-frequency = <0>; 242 interrupts = <10 0x8>; 243 interrupt-parent = <&ipic>; 244 }; 245 246 crypto@30000 { 247 compatible = "fsl,sec2.0"; 248 reg = <0x30000 0x10000>; 249 interrupts = <11 0x8>; 250 interrupt-parent = <&ipic>; 251 fsl,num-channels = <4>; 252 fsl,channel-fifo-len = <24>; 253 fsl,exec-units-mask = <0x7e>; 254 fsl,descriptor-types-mask = <0x01010ebf>; 255 }; 256 257 /* IPIC 258 * interrupts cell = <intr #, sense> 259 * sense values match linux IORESOURCE_IRQ_* defines: 260 * sense == 8: Level, low assertion 261 * sense == 2: Edge, high-to-low change 262 */ 263 ipic: pic@700 { 264 interrupt-controller; 265 #address-cells = <0>; 266 #interrupt-cells = <2>; 267 reg = <0x700 0x100>; 268 device_type = "ipic"; 269 }; 270 }; 271 272 pci0: pci@e0008500 { 273 cell-index = <1>; 274 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 275 interrupt-map = < 276 277 /* IDSEL 0x11 */ 278 0x8800 0x0 0x0 0x1 &ipic 20 0x8 279 0x8800 0x0 0x0 0x2 &ipic 21 0x8 280 0x8800 0x0 0x0 0x3 &ipic 22 0x8 281 0x8800 0x0 0x0 0x4 &ipic 23 0x8>; 282 283 interrupt-parent = <&ipic>; 284 interrupts = <0x42 0x8>; 285 bus-range = <0 0>; 286 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000 287 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000 288 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>; 289 clock-frequency = <66666666>; 290 #interrupt-cells = <1>; 291 #size-cells = <2>; 292 #address-cells = <3>; 293 reg = <0xe0008500 0x100 /* internal registers */ 294 0xe0008300 0x8>; /* config space access registers */ 295 compatible = "fsl,mpc8349-pci"; 296 device_type = "pci"; 297 }; 298}; 299