1 /*
2 * linux/arch/alpha/kernel/sys_cabriolet.c
3 *
4 * Copyright (C) 1995 David A Rusling
5 * Copyright (C) 1996 Jay A Estabrook
6 * Copyright (C) 1998, 1999, 2000 Richard Henderson
7 *
8 * Code supporting the Cabriolet (AlphaPC64), EB66+, and EB164,
9 * PC164 and LX164.
10 */
11
12 #include <linux/kernel.h>
13 #include <linux/types.h>
14 #include <linux/mm.h>
15 #include <linux/sched.h>
16 #include <linux/pci.h>
17 #include <linux/init.h>
18 #include <linux/bitops.h>
19
20 #include <asm/ptrace.h>
21 #include <asm/system.h>
22 #include <asm/dma.h>
23 #include <asm/irq.h>
24 #include <asm/mmu_context.h>
25 #include <asm/io.h>
26 #include <asm/pgtable.h>
27 #include <asm/core_apecs.h>
28 #include <asm/core_cia.h>
29 #include <asm/core_lca.h>
30 #include <asm/tlbflush.h>
31
32 #include "proto.h"
33 #include "irq_impl.h"
34 #include "pci_impl.h"
35 #include "machvec_impl.h"
36
37
38 /* Note mask bit is true for DISABLED irqs. */
39 static unsigned long cached_irq_mask = ~0UL;
40
41 static inline void
cabriolet_update_irq_hw(unsigned int irq,unsigned long mask)42 cabriolet_update_irq_hw(unsigned int irq, unsigned long mask)
43 {
44 int ofs = (irq - 16) / 8;
45 outb(mask >> (16 + ofs * 8), 0x804 + ofs);
46 }
47
48 static inline void
cabriolet_enable_irq(unsigned int irq)49 cabriolet_enable_irq(unsigned int irq)
50 {
51 cabriolet_update_irq_hw(irq, cached_irq_mask &= ~(1UL << irq));
52 }
53
54 static void
cabriolet_disable_irq(unsigned int irq)55 cabriolet_disable_irq(unsigned int irq)
56 {
57 cabriolet_update_irq_hw(irq, cached_irq_mask |= 1UL << irq);
58 }
59
60 static unsigned int
cabriolet_startup_irq(unsigned int irq)61 cabriolet_startup_irq(unsigned int irq)
62 {
63 cabriolet_enable_irq(irq);
64 return 0; /* never anything pending */
65 }
66
67 static void
cabriolet_end_irq(unsigned int irq)68 cabriolet_end_irq(unsigned int irq)
69 {
70 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
71 cabriolet_enable_irq(irq);
72 }
73
74 static struct hw_interrupt_type cabriolet_irq_type = {
75 .typename = "CABRIOLET",
76 .startup = cabriolet_startup_irq,
77 .shutdown = cabriolet_disable_irq,
78 .enable = cabriolet_enable_irq,
79 .disable = cabriolet_disable_irq,
80 .ack = cabriolet_disable_irq,
81 .end = cabriolet_end_irq,
82 };
83
84 static void
cabriolet_device_interrupt(unsigned long v)85 cabriolet_device_interrupt(unsigned long v)
86 {
87 unsigned long pld;
88 unsigned int i;
89
90 /* Read the interrupt summary registers */
91 pld = inb(0x804) | (inb(0x805) << 8) | (inb(0x806) << 16);
92
93 /*
94 * Now for every possible bit set, work through them and call
95 * the appropriate interrupt handler.
96 */
97 while (pld) {
98 i = ffz(~pld);
99 pld &= pld - 1; /* clear least bit set */
100 if (i == 4) {
101 isa_device_interrupt(v);
102 } else {
103 handle_irq(16 + i);
104 }
105 }
106 }
107
108 static void __init
common_init_irq(void (* srm_dev_int)(unsigned long v))109 common_init_irq(void (*srm_dev_int)(unsigned long v))
110 {
111 init_i8259a_irqs();
112
113 if (alpha_using_srm) {
114 alpha_mv.device_interrupt = srm_dev_int;
115 init_srm_irqs(35, 0);
116 }
117 else {
118 long i;
119
120 outb(0xff, 0x804);
121 outb(0xff, 0x805);
122 outb(0xff, 0x806);
123
124 for (i = 16; i < 35; ++i) {
125 irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL;
126 irq_desc[i].chip = &cabriolet_irq_type;
127 }
128 }
129
130 common_init_isa_dma();
131 setup_irq(16+4, &isa_cascade_irqaction);
132 }
133
134 #ifndef CONFIG_ALPHA_PC164
135 static void __init
cabriolet_init_irq(void)136 cabriolet_init_irq(void)
137 {
138 common_init_irq(srm_device_interrupt);
139 }
140 #endif
141
142 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_PC164)
143 /* In theory, the PC164 has the same interrupt hardware as the other
144 Cabriolet based systems. However, something got screwed up late
145 in the development cycle which broke the interrupt masking hardware.
146 Repeat, it is not possible to mask and ack interrupts. At all.
147
148 In an attempt to work around this, while processing interrupts,
149 we do not allow the IPL to drop below what it is currently. This
150 prevents the possibility of recursion.
151
152 ??? Another option might be to force all PCI devices to use edge
153 triggered rather than level triggered interrupts. That might be
154 too invasive though. */
155
156 static void
pc164_srm_device_interrupt(unsigned long v)157 pc164_srm_device_interrupt(unsigned long v)
158 {
159 __min_ipl = getipl();
160 srm_device_interrupt(v);
161 __min_ipl = 0;
162 }
163
164 static void
pc164_device_interrupt(unsigned long v)165 pc164_device_interrupt(unsigned long v)
166 {
167 __min_ipl = getipl();
168 cabriolet_device_interrupt(v);
169 __min_ipl = 0;
170 }
171
172 static void __init
pc164_init_irq(void)173 pc164_init_irq(void)
174 {
175 common_init_irq(pc164_srm_device_interrupt);
176 }
177 #endif
178
179 /*
180 * The EB66+ is very similar to the EB66 except that it does not have
181 * the on-board NCR and Tulip chips. In the code below, I have used
182 * slot number to refer to the id select line and *not* the slot
183 * number used in the EB66+ documentation. However, in the table,
184 * I've given the slot number, the id select line and the Jxx number
185 * that's printed on the board. The interrupt pins from the PCI slots
186 * are wired into 3 interrupt summary registers at 0x804, 0x805 and
187 * 0x806 ISA.
188 *
189 * In the table, -1 means don't assign an IRQ number. This is usually
190 * because it is the Saturn IO (SIO) PCI/ISA Bridge Chip.
191 */
192
193 static inline int __init
eb66p_map_irq(struct pci_dev * dev,u8 slot,u8 pin)194 eb66p_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
195 {
196 static char irq_tab[5][5] __initdata = {
197 /*INT INTA INTB INTC INTD */
198 {16+0, 16+0, 16+5, 16+9, 16+13}, /* IdSel 6, slot 0, J25 */
199 {16+1, 16+1, 16+6, 16+10, 16+14}, /* IdSel 7, slot 1, J26 */
200 { -1, -1, -1, -1, -1}, /* IdSel 8, SIO */
201 {16+2, 16+2, 16+7, 16+11, 16+15}, /* IdSel 9, slot 2, J27 */
202 {16+3, 16+3, 16+8, 16+12, 16+6} /* IdSel 10, slot 3, J28 */
203 };
204 const long min_idsel = 6, max_idsel = 10, irqs_per_slot = 5;
205 return COMMON_TABLE_LOOKUP;
206 }
207
208
209 /*
210 * The AlphaPC64 is very similar to the EB66+ except that its slots
211 * are numbered differently. In the code below, I have used slot
212 * number to refer to the id select line and *not* the slot number
213 * used in the AlphaPC64 documentation. However, in the table, I've
214 * given the slot number, the id select line and the Jxx number that's
215 * printed on the board. The interrupt pins from the PCI slots are
216 * wired into 3 interrupt summary registers at 0x804, 0x805 and 0x806
217 * ISA.
218 *
219 * In the table, -1 means don't assign an IRQ number. This is usually
220 * because it is the Saturn IO (SIO) PCI/ISA Bridge Chip.
221 */
222
223 static inline int __init
cabriolet_map_irq(struct pci_dev * dev,u8 slot,u8 pin)224 cabriolet_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
225 {
226 static char irq_tab[5][5] __initdata = {
227 /*INT INTA INTB INTC INTD */
228 { 16+2, 16+2, 16+7, 16+11, 16+15}, /* IdSel 5, slot 2, J21 */
229 { 16+0, 16+0, 16+5, 16+9, 16+13}, /* IdSel 6, slot 0, J19 */
230 { 16+1, 16+1, 16+6, 16+10, 16+14}, /* IdSel 7, slot 1, J20 */
231 { -1, -1, -1, -1, -1}, /* IdSel 8, SIO */
232 { 16+3, 16+3, 16+8, 16+12, 16+16} /* IdSel 9, slot 3, J22 */
233 };
234 const long min_idsel = 5, max_idsel = 9, irqs_per_slot = 5;
235 return COMMON_TABLE_LOOKUP;
236 }
237
238 static inline void __init
cabriolet_init_pci(void)239 cabriolet_init_pci(void)
240 {
241 common_init_pci();
242 ns87312_enable_ide(0x398);
243 }
244
245 static inline void __init
cia_cab_init_pci(void)246 cia_cab_init_pci(void)
247 {
248 cia_init_pci();
249 ns87312_enable_ide(0x398);
250 }
251
252 /*
253 * The PC164 and LX164 have 19 PCI interrupts, four from each of the four
254 * PCI slots, the SIO, PCI/IDE, and USB.
255 *
256 * Each of the interrupts can be individually masked. This is
257 * accomplished by setting the appropriate bit in the mask register.
258 * A bit is set by writing a "1" to the desired position in the mask
259 * register and cleared by writing a "0". There are 3 mask registers
260 * located at ISA address 804h, 805h and 806h.
261 *
262 * An I/O read at ISA address 804h, 805h, 806h will return the
263 * state of the 11 PCI interrupts and not the state of the MASKED
264 * interrupts.
265 *
266 * Note: A write to I/O 804h, 805h, and 806h the mask register will be
267 * updated.
268 *
269 *
270 * ISA DATA<7:0>
271 * ISA +--------------------------------------------------------------+
272 * ADDRESS | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
273 * +==============================================================+
274 * 0x804 | INTB0 | USB | IDE | SIO | INTA3 |INTA2 | INTA1 | INTA0 |
275 * +--------------------------------------------------------------+
276 * 0x805 | INTD0 | INTC3 | INTC2 | INTC1 | INTC0 |INTB3 | INTB2 | INTB1 |
277 * +--------------------------------------------------------------+
278 * 0x806 | Rsrv | Rsrv | Rsrv | Rsrv | Rsrv |INTD3 | INTD2 | INTD1 |
279 * +--------------------------------------------------------------+
280 * * Rsrv = reserved bits
281 * Note: The mask register is write-only.
282 *
283 * IdSel
284 * 5 32 bit PCI option slot 2
285 * 6 64 bit PCI option slot 0
286 * 7 64 bit PCI option slot 1
287 * 8 Saturn I/O
288 * 9 32 bit PCI option slot 3
289 * 10 USB
290 * 11 IDE
291 *
292 */
293
294 static inline int __init
alphapc164_map_irq(struct pci_dev * dev,u8 slot,u8 pin)295 alphapc164_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
296 {
297 static char irq_tab[7][5] __initdata = {
298 /*INT INTA INTB INTC INTD */
299 { 16+2, 16+2, 16+9, 16+13, 16+17}, /* IdSel 5, slot 2, J20 */
300 { 16+0, 16+0, 16+7, 16+11, 16+15}, /* IdSel 6, slot 0, J29 */
301 { 16+1, 16+1, 16+8, 16+12, 16+16}, /* IdSel 7, slot 1, J26 */
302 { -1, -1, -1, -1, -1}, /* IdSel 8, SIO */
303 { 16+3, 16+3, 16+10, 16+14, 16+18}, /* IdSel 9, slot 3, J19 */
304 { 16+6, 16+6, 16+6, 16+6, 16+6}, /* IdSel 10, USB */
305 { 16+5, 16+5, 16+5, 16+5, 16+5} /* IdSel 11, IDE */
306 };
307 const long min_idsel = 5, max_idsel = 11, irqs_per_slot = 5;
308 return COMMON_TABLE_LOOKUP;
309 }
310
311 static inline void __init
alphapc164_init_pci(void)312 alphapc164_init_pci(void)
313 {
314 cia_init_pci();
315 SMC93x_Init();
316 }
317
318
319 /*
320 * The System Vector
321 */
322
323 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_CABRIOLET)
324 struct alpha_machine_vector cabriolet_mv __initmv = {
325 .vector_name = "Cabriolet",
326 DO_EV4_MMU,
327 DO_DEFAULT_RTC,
328 DO_APECS_IO,
329 .machine_check = apecs_machine_check,
330 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
331 .min_io_address = DEFAULT_IO_BASE,
332 .min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE,
333
334 .nr_irqs = 35,
335 .device_interrupt = cabriolet_device_interrupt,
336
337 .init_arch = apecs_init_arch,
338 .init_irq = cabriolet_init_irq,
339 .init_rtc = common_init_rtc,
340 .init_pci = cabriolet_init_pci,
341 .pci_map_irq = cabriolet_map_irq,
342 .pci_swizzle = common_swizzle,
343 };
344 #ifndef CONFIG_ALPHA_EB64P
345 ALIAS_MV(cabriolet)
346 #endif
347 #endif
348
349 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_EB164)
350 struct alpha_machine_vector eb164_mv __initmv = {
351 .vector_name = "EB164",
352 DO_EV5_MMU,
353 DO_DEFAULT_RTC,
354 DO_CIA_IO,
355 .machine_check = cia_machine_check,
356 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
357 .min_io_address = DEFAULT_IO_BASE,
358 .min_mem_address = CIA_DEFAULT_MEM_BASE,
359
360 .nr_irqs = 35,
361 .device_interrupt = cabriolet_device_interrupt,
362
363 .init_arch = cia_init_arch,
364 .init_irq = cabriolet_init_irq,
365 .init_rtc = common_init_rtc,
366 .init_pci = cia_cab_init_pci,
367 .kill_arch = cia_kill_arch,
368 .pci_map_irq = cabriolet_map_irq,
369 .pci_swizzle = common_swizzle,
370 };
371 ALIAS_MV(eb164)
372 #endif
373
374 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_EB66P)
375 struct alpha_machine_vector eb66p_mv __initmv = {
376 .vector_name = "EB66+",
377 DO_EV4_MMU,
378 DO_DEFAULT_RTC,
379 DO_LCA_IO,
380 .machine_check = lca_machine_check,
381 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
382 .min_io_address = DEFAULT_IO_BASE,
383 .min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE,
384
385 .nr_irqs = 35,
386 .device_interrupt = cabriolet_device_interrupt,
387
388 .init_arch = lca_init_arch,
389 .init_irq = cabriolet_init_irq,
390 .init_rtc = common_init_rtc,
391 .init_pci = cabriolet_init_pci,
392 .pci_map_irq = eb66p_map_irq,
393 .pci_swizzle = common_swizzle,
394 };
395 ALIAS_MV(eb66p)
396 #endif
397
398 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_LX164)
399 struct alpha_machine_vector lx164_mv __initmv = {
400 .vector_name = "LX164",
401 DO_EV5_MMU,
402 DO_DEFAULT_RTC,
403 DO_PYXIS_IO,
404 .machine_check = cia_machine_check,
405 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
406 .min_io_address = DEFAULT_IO_BASE,
407 .min_mem_address = DEFAULT_MEM_BASE,
408 .pci_dac_offset = PYXIS_DAC_OFFSET,
409
410 .nr_irqs = 35,
411 .device_interrupt = cabriolet_device_interrupt,
412
413 .init_arch = pyxis_init_arch,
414 .init_irq = cabriolet_init_irq,
415 .init_rtc = common_init_rtc,
416 .init_pci = alphapc164_init_pci,
417 .kill_arch = cia_kill_arch,
418 .pci_map_irq = alphapc164_map_irq,
419 .pci_swizzle = common_swizzle,
420 };
421 ALIAS_MV(lx164)
422 #endif
423
424 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_PC164)
425 struct alpha_machine_vector pc164_mv __initmv = {
426 .vector_name = "PC164",
427 DO_EV5_MMU,
428 DO_DEFAULT_RTC,
429 DO_CIA_IO,
430 .machine_check = cia_machine_check,
431 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
432 .min_io_address = DEFAULT_IO_BASE,
433 .min_mem_address = CIA_DEFAULT_MEM_BASE,
434
435 .nr_irqs = 35,
436 .device_interrupt = pc164_device_interrupt,
437
438 .init_arch = cia_init_arch,
439 .init_irq = pc164_init_irq,
440 .init_rtc = common_init_rtc,
441 .init_pci = alphapc164_init_pci,
442 .kill_arch = cia_kill_arch,
443 .pci_map_irq = alphapc164_map_irq,
444 .pci_swizzle = common_swizzle,
445 };
446 ALIAS_MV(pc164)
447 #endif
448