1 /*
2 * linux/arch/arm/mach-imx/irq.c
3 *
4 * Copyright (C) 1999 ARM Limited
5 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 *
21 * 03/03/2004 Sascha Hauer <sascha@saschahauer.de>
22 * Copied from the motorola bsp package and added gpio demux
23 * interrupt handler
24 */
25
26 #include <linux/init.h>
27 #include <linux/list.h>
28 #include <linux/timer.h>
29 #include <linux/io.h>
30
31 #include <mach/hardware.h>
32 #include <asm/irq.h>
33
34 #include <asm/mach/irq.h>
35
36 /*
37 *
38 * We simply use the ENABLE DISABLE registers inside of the IMX
39 * to turn on/off specific interrupts.
40 *
41 */
42
43 #define INTCNTL_OFF 0x00
44 #define NIMASK_OFF 0x04
45 #define INTENNUM_OFF 0x08
46 #define INTDISNUM_OFF 0x0C
47 #define INTENABLEH_OFF 0x10
48 #define INTENABLEL_OFF 0x14
49 #define INTTYPEH_OFF 0x18
50 #define INTTYPEL_OFF 0x1C
51 #define NIPRIORITY_OFF(x) (0x20+4*(7-(x)))
52 #define NIVECSR_OFF 0x40
53 #define FIVECSR_OFF 0x44
54 #define INTSRCH_OFF 0x48
55 #define INTSRCL_OFF 0x4C
56 #define INTFRCH_OFF 0x50
57 #define INTFRCL_OFF 0x54
58 #define NIPNDH_OFF 0x58
59 #define NIPNDL_OFF 0x5C
60 #define FIPNDH_OFF 0x60
61 #define FIPNDL_OFF 0x64
62
63 #define VA_AITC_BASE IO_ADDRESS(IMX_AITC_BASE)
64 #define IMX_AITC_INTCNTL (VA_AITC_BASE + INTCNTL_OFF)
65 #define IMX_AITC_NIMASK (VA_AITC_BASE + NIMASK_OFF)
66 #define IMX_AITC_INTENNUM (VA_AITC_BASE + INTENNUM_OFF)
67 #define IMX_AITC_INTDISNUM (VA_AITC_BASE + INTDISNUM_OFF)
68 #define IMX_AITC_INTENABLEH (VA_AITC_BASE + INTENABLEH_OFF)
69 #define IMX_AITC_INTENABLEL (VA_AITC_BASE + INTENABLEL_OFF)
70 #define IMX_AITC_INTTYPEH (VA_AITC_BASE + INTTYPEH_OFF)
71 #define IMX_AITC_INTTYPEL (VA_AITC_BASE + INTTYPEL_OFF)
72 #define IMX_AITC_NIPRIORITY(x) (VA_AITC_BASE + NIPRIORITY_OFF(x))
73 #define IMX_AITC_NIVECSR (VA_AITC_BASE + NIVECSR_OFF)
74 #define IMX_AITC_FIVECSR (VA_AITC_BASE + FIVECSR_OFF)
75 #define IMX_AITC_INTSRCH (VA_AITC_BASE + INTSRCH_OFF)
76 #define IMX_AITC_INTSRCL (VA_AITC_BASE + INTSRCL_OFF)
77 #define IMX_AITC_INTFRCH (VA_AITC_BASE + INTFRCH_OFF)
78 #define IMX_AITC_INTFRCL (VA_AITC_BASE + INTFRCL_OFF)
79 #define IMX_AITC_NIPNDH (VA_AITC_BASE + NIPNDH_OFF)
80 #define IMX_AITC_NIPNDL (VA_AITC_BASE + NIPNDL_OFF)
81 #define IMX_AITC_FIPNDH (VA_AITC_BASE + FIPNDH_OFF)
82 #define IMX_AITC_FIPNDL (VA_AITC_BASE + FIPNDL_OFF)
83
84 #if 0
85 #define DEBUG_IRQ(fmt...) printk(fmt)
86 #else
87 #define DEBUG_IRQ(fmt...) do { } while (0)
88 #endif
89
90 static void
imx_mask_irq(unsigned int irq)91 imx_mask_irq(unsigned int irq)
92 {
93 __raw_writel(irq, IMX_AITC_INTDISNUM);
94 }
95
96 static void
imx_unmask_irq(unsigned int irq)97 imx_unmask_irq(unsigned int irq)
98 {
99 __raw_writel(irq, IMX_AITC_INTENNUM);
100 }
101
102 #ifdef CONFIG_FIQ
imx_set_irq_fiq(unsigned int irq,unsigned int type)103 int imx_set_irq_fiq(unsigned int irq, unsigned int type)
104 {
105 unsigned int irqt;
106
107 if (irq >= IMX_IRQS)
108 return -EINVAL;
109
110 if (irq < IMX_IRQS / 2) {
111 irqt = __raw_readl(IMX_AITC_INTTYPEL) & ~(1 << irq);
112 __raw_writel(irqt | (!!type << irq), IMX_AITC_INTTYPEL);
113 } else {
114 irq -= IMX_IRQS / 2;
115 irqt = __raw_readl(IMX_AITC_INTTYPEH) & ~(1 << irq);
116 __raw_writel(irqt | (!!type << irq), IMX_AITC_INTTYPEH);
117 }
118
119 return 0;
120 }
121 EXPORT_SYMBOL(imx_set_irq_fiq);
122 #endif /* CONFIG_FIQ */
123
124 static int
imx_gpio_irq_type(unsigned int _irq,unsigned int type)125 imx_gpio_irq_type(unsigned int _irq, unsigned int type)
126 {
127 unsigned int irq_type = 0, irq, reg, bit;
128
129 irq = _irq - IRQ_GPIOA(0);
130 reg = irq >> 5;
131 bit = 1 << (irq % 32);
132
133 if (type == IRQ_TYPE_PROBE) {
134 /* Don't mess with enabled GPIOs using preconfigured edges or
135 GPIOs set to alternate function during probe */
136 /* TODO: support probe */
137 // if ((GPIO_IRQ_rising_edge[idx] | GPIO_IRQ_falling_edge[idx]) &
138 // GPIO_bit(gpio))
139 // return 0;
140 // if (GAFR(gpio) & (0x3 << (((gpio) & 0xf)*2)))
141 // return 0;
142 // type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
143 }
144
145 GIUS(reg) |= bit;
146 DDIR(reg) &= ~(bit);
147
148 DEBUG_IRQ("setting type of irq %d to ", _irq);
149
150 if (type & IRQ_TYPE_EDGE_RISING) {
151 DEBUG_IRQ("rising edges\n");
152 irq_type = 0x0;
153 }
154 if (type & IRQ_TYPE_EDGE_FALLING) {
155 DEBUG_IRQ("falling edges\n");
156 irq_type = 0x1;
157 }
158 if (type & IRQ_TYPE_LEVEL_LOW) {
159 DEBUG_IRQ("low level\n");
160 irq_type = 0x3;
161 }
162 if (type & IRQ_TYPE_LEVEL_HIGH) {
163 DEBUG_IRQ("high level\n");
164 irq_type = 0x2;
165 }
166
167 if (irq % 32 < 16) {
168 ICR1(reg) = (ICR1(reg) & ~(0x3 << ((irq % 16) * 2))) |
169 (irq_type << ((irq % 16) * 2));
170 } else {
171 ICR2(reg) = (ICR2(reg) & ~(0x3 << ((irq % 16) * 2))) |
172 (irq_type << ((irq % 16) * 2));
173 }
174
175 return 0;
176
177 }
178
179 static void
imx_gpio_ack_irq(unsigned int irq)180 imx_gpio_ack_irq(unsigned int irq)
181 {
182 DEBUG_IRQ("%s: irq %d\n", __func__, irq);
183 ISR(IRQ_TO_REG(irq)) = 1 << ((irq - IRQ_GPIOA(0)) % 32);
184 }
185
186 static void
imx_gpio_mask_irq(unsigned int irq)187 imx_gpio_mask_irq(unsigned int irq)
188 {
189 DEBUG_IRQ("%s: irq %d\n", __func__, irq);
190 IMR(IRQ_TO_REG(irq)) &= ~( 1 << ((irq - IRQ_GPIOA(0)) % 32));
191 }
192
193 static void
imx_gpio_unmask_irq(unsigned int irq)194 imx_gpio_unmask_irq(unsigned int irq)
195 {
196 DEBUG_IRQ("%s: irq %d\n", __func__, irq);
197 IMR(IRQ_TO_REG(irq)) |= 1 << ((irq - IRQ_GPIOA(0)) % 32);
198 }
199
200 static void
imx_gpio_handler(unsigned int mask,unsigned int irq,struct irq_desc * desc)201 imx_gpio_handler(unsigned int mask, unsigned int irq,
202 struct irq_desc *desc)
203 {
204 while (mask) {
205 if (mask & 1) {
206 DEBUG_IRQ("handling irq %d\n", irq);
207 generic_handle_irq(irq);
208 }
209 irq++;
210 mask >>= 1;
211 }
212 }
213
214 static void
imx_gpioa_demux_handler(unsigned int irq_unused,struct irq_desc * desc)215 imx_gpioa_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
216 {
217 unsigned int mask, irq;
218
219 mask = ISR(0);
220 irq = IRQ_GPIOA(0);
221 imx_gpio_handler(mask, irq, desc);
222 }
223
224 static void
imx_gpiob_demux_handler(unsigned int irq_unused,struct irq_desc * desc)225 imx_gpiob_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
226 {
227 unsigned int mask, irq;
228
229 mask = ISR(1);
230 irq = IRQ_GPIOB(0);
231 imx_gpio_handler(mask, irq, desc);
232 }
233
234 static void
imx_gpioc_demux_handler(unsigned int irq_unused,struct irq_desc * desc)235 imx_gpioc_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
236 {
237 unsigned int mask, irq;
238
239 mask = ISR(2);
240 irq = IRQ_GPIOC(0);
241 imx_gpio_handler(mask, irq, desc);
242 }
243
244 static void
imx_gpiod_demux_handler(unsigned int irq_unused,struct irq_desc * desc)245 imx_gpiod_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
246 {
247 unsigned int mask, irq;
248
249 mask = ISR(3);
250 irq = IRQ_GPIOD(0);
251 imx_gpio_handler(mask, irq, desc);
252 }
253
254 static struct irq_chip imx_internal_chip = {
255 .name = "MPU",
256 .ack = imx_mask_irq,
257 .mask = imx_mask_irq,
258 .unmask = imx_unmask_irq,
259 };
260
261 static struct irq_chip imx_gpio_chip = {
262 .name = "GPIO",
263 .ack = imx_gpio_ack_irq,
264 .mask = imx_gpio_mask_irq,
265 .unmask = imx_gpio_unmask_irq,
266 .set_type = imx_gpio_irq_type,
267 };
268
269 void __init
imx_init_irq(void)270 imx_init_irq(void)
271 {
272 unsigned int irq;
273
274 DEBUG_IRQ("Initializing imx interrupts\n");
275
276 /* Disable all interrupts initially. */
277 /* Do not rely on the bootloader. */
278 __raw_writel(0, IMX_AITC_INTENABLEH);
279 __raw_writel(0, IMX_AITC_INTENABLEL);
280
281 /* Mask all GPIO interrupts as well */
282 IMR(0) = 0;
283 IMR(1) = 0;
284 IMR(2) = 0;
285 IMR(3) = 0;
286
287 for (irq = 0; irq < IMX_IRQS; irq++) {
288 set_irq_chip(irq, &imx_internal_chip);
289 set_irq_handler(irq, handle_level_irq);
290 set_irq_flags(irq, IRQF_VALID);
291 }
292
293 for (irq = IRQ_GPIOA(0); irq < IRQ_GPIOD(32); irq++) {
294 set_irq_chip(irq, &imx_gpio_chip);
295 set_irq_handler(irq, handle_edge_irq);
296 set_irq_flags(irq, IRQF_VALID);
297 }
298
299 set_irq_chained_handler(GPIO_INT_PORTA, imx_gpioa_demux_handler);
300 set_irq_chained_handler(GPIO_INT_PORTB, imx_gpiob_demux_handler);
301 set_irq_chained_handler(GPIO_INT_PORTC, imx_gpioc_demux_handler);
302 set_irq_chained_handler(GPIO_INT_PORTD, imx_gpiod_demux_handler);
303
304 /* Release masking of interrupts according to priority */
305 __raw_writel(-1, IMX_AITC_NIMASK);
306
307 #ifdef CONFIG_FIQ
308 /* Initialize FIQ */
309 init_FIQ();
310 #endif
311 }
312