1 /* 2 * OMAP3 clock framework 3 * 4 * Copyright (C) 2007-2008 Texas Instruments, Inc. 5 * Copyright (C) 2007-2008 Nokia Corporation 6 * 7 * Written by Paul Walmsley 8 * With many device clock fixes by Kevin Hilman and Jouni Högander 9 * DPLL bypass clock support added by Roman Tereshonkov 10 * 11 */ 12 13 /* 14 * Virtual clocks are introduced as convenient tools. 15 * They are sources for other clocks and not supposed 16 * to be requested from drivers directly. 17 */ 18 19 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H 20 #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H 21 22 #include <mach/control.h> 23 24 #include "clock.h" 25 #include "cm.h" 26 #include "cm-regbits-34xx.h" 27 #include "prm.h" 28 #include "prm-regbits-34xx.h" 29 30 static void omap3_dpll_recalc(struct clk *clk); 31 static void omap3_clkoutx2_recalc(struct clk *clk); 32 static void omap3_dpll_allow_idle(struct clk *clk); 33 static void omap3_dpll_deny_idle(struct clk *clk); 34 static u32 omap3_dpll_autoidle_read(struct clk *clk); 35 static int omap3_noncore_dpll_enable(struct clk *clk); 36 static void omap3_noncore_dpll_disable(struct clk *clk); 37 38 /* Maximum DPLL multiplier, divider values for OMAP3 */ 39 #define OMAP3_MAX_DPLL_MULT 2048 40 #define OMAP3_MAX_DPLL_DIV 128 41 42 /* 43 * DPLL1 supplies clock to the MPU. 44 * DPLL2 supplies clock to the IVA2. 45 * DPLL3 supplies CORE domain clocks. 46 * DPLL4 supplies peripheral clocks. 47 * DPLL5 supplies other peripheral clocks (USBHOST, USIM). 48 */ 49 50 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */ 51 #define DPLL_LOW_POWER_STOP 0x1 52 #define DPLL_LOW_POWER_BYPASS 0x5 53 #define DPLL_LOCKED 0x7 54 55 /* PRM CLOCKS */ 56 57 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */ 58 static struct clk omap_32k_fck = { 59 .name = "omap_32k_fck", 60 .rate = 32768, 61 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | 62 ALWAYS_ENABLED, 63 .recalc = &propagate_rate, 64 }; 65 66 static struct clk secure_32k_fck = { 67 .name = "secure_32k_fck", 68 .rate = 32768, 69 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | 70 ALWAYS_ENABLED, 71 .recalc = &propagate_rate, 72 }; 73 74 /* Virtual source clocks for osc_sys_ck */ 75 static struct clk virt_12m_ck = { 76 .name = "virt_12m_ck", 77 .rate = 12000000, 78 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | 79 ALWAYS_ENABLED, 80 .recalc = &propagate_rate, 81 }; 82 83 static struct clk virt_13m_ck = { 84 .name = "virt_13m_ck", 85 .rate = 13000000, 86 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | 87 ALWAYS_ENABLED, 88 .recalc = &propagate_rate, 89 }; 90 91 static struct clk virt_16_8m_ck = { 92 .name = "virt_16_8m_ck", 93 .rate = 16800000, 94 .flags = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES | 95 ALWAYS_ENABLED, 96 .recalc = &propagate_rate, 97 }; 98 99 static struct clk virt_19_2m_ck = { 100 .name = "virt_19_2m_ck", 101 .rate = 19200000, 102 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | 103 ALWAYS_ENABLED, 104 .recalc = &propagate_rate, 105 }; 106 107 static struct clk virt_26m_ck = { 108 .name = "virt_26m_ck", 109 .rate = 26000000, 110 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | 111 ALWAYS_ENABLED, 112 .recalc = &propagate_rate, 113 }; 114 115 static struct clk virt_38_4m_ck = { 116 .name = "virt_38_4m_ck", 117 .rate = 38400000, 118 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | 119 ALWAYS_ENABLED, 120 .recalc = &propagate_rate, 121 }; 122 123 static const struct clksel_rate osc_sys_12m_rates[] = { 124 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, 125 { .div = 0 } 126 }; 127 128 static const struct clksel_rate osc_sys_13m_rates[] = { 129 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, 130 { .div = 0 } 131 }; 132 133 static const struct clksel_rate osc_sys_16_8m_rates[] = { 134 { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE }, 135 { .div = 0 } 136 }; 137 138 static const struct clksel_rate osc_sys_19_2m_rates[] = { 139 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, 140 { .div = 0 } 141 }; 142 143 static const struct clksel_rate osc_sys_26m_rates[] = { 144 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, 145 { .div = 0 } 146 }; 147 148 static const struct clksel_rate osc_sys_38_4m_rates[] = { 149 { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE }, 150 { .div = 0 } 151 }; 152 153 static const struct clksel osc_sys_clksel[] = { 154 { .parent = &virt_12m_ck, .rates = osc_sys_12m_rates }, 155 { .parent = &virt_13m_ck, .rates = osc_sys_13m_rates }, 156 { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates }, 157 { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates }, 158 { .parent = &virt_26m_ck, .rates = osc_sys_26m_rates }, 159 { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates }, 160 { .parent = NULL }, 161 }; 162 163 /* Oscillator clock */ 164 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */ 165 static struct clk osc_sys_ck = { 166 .name = "osc_sys_ck", 167 .init = &omap2_init_clksel_parent, 168 .clksel_reg = OMAP3430_PRM_CLKSEL, 169 .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK, 170 .clksel = osc_sys_clksel, 171 /* REVISIT: deal with autoextclkmode? */ 172 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | 173 ALWAYS_ENABLED, 174 .recalc = &omap2_clksel_recalc, 175 }; 176 177 static const struct clksel_rate div2_rates[] = { 178 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, 179 { .div = 2, .val = 2, .flags = RATE_IN_343X }, 180 { .div = 0 } 181 }; 182 183 static const struct clksel sys_clksel[] = { 184 { .parent = &osc_sys_ck, .rates = div2_rates }, 185 { .parent = NULL } 186 }; 187 188 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */ 189 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */ 190 static struct clk sys_ck = { 191 .name = "sys_ck", 192 .parent = &osc_sys_ck, 193 .init = &omap2_init_clksel_parent, 194 .clksel_reg = OMAP3430_PRM_CLKSRC_CTRL, 195 .clksel_mask = OMAP_SYSCLKDIV_MASK, 196 .clksel = sys_clksel, 197 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, 198 .recalc = &omap2_clksel_recalc, 199 }; 200 201 static struct clk sys_altclk = { 202 .name = "sys_altclk", 203 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, 204 .recalc = &propagate_rate, 205 }; 206 207 /* Optional external clock input for some McBSPs */ 208 static struct clk mcbsp_clks = { 209 .name = "mcbsp_clks", 210 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, 211 .recalc = &propagate_rate, 212 }; 213 214 /* PRM EXTERNAL CLOCK OUTPUT */ 215 216 static struct clk sys_clkout1 = { 217 .name = "sys_clkout1", 218 .parent = &osc_sys_ck, 219 .enable_reg = OMAP3430_PRM_CLKOUT_CTRL, 220 .enable_bit = OMAP3430_CLKOUT_EN_SHIFT, 221 .flags = CLOCK_IN_OMAP343X, 222 .recalc = &followparent_recalc, 223 }; 224 225 /* DPLLS */ 226 227 /* CM CLOCKS */ 228 229 static const struct clksel_rate dpll_bypass_rates[] = { 230 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, 231 { .div = 0 } 232 }; 233 234 static const struct clksel_rate dpll_locked_rates[] = { 235 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, 236 { .div = 0 } 237 }; 238 239 static const struct clksel_rate div16_dpll_rates[] = { 240 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, 241 { .div = 2, .val = 2, .flags = RATE_IN_343X }, 242 { .div = 3, .val = 3, .flags = RATE_IN_343X }, 243 { .div = 4, .val = 4, .flags = RATE_IN_343X }, 244 { .div = 5, .val = 5, .flags = RATE_IN_343X }, 245 { .div = 6, .val = 6, .flags = RATE_IN_343X }, 246 { .div = 7, .val = 7, .flags = RATE_IN_343X }, 247 { .div = 8, .val = 8, .flags = RATE_IN_343X }, 248 { .div = 9, .val = 9, .flags = RATE_IN_343X }, 249 { .div = 10, .val = 10, .flags = RATE_IN_343X }, 250 { .div = 11, .val = 11, .flags = RATE_IN_343X }, 251 { .div = 12, .val = 12, .flags = RATE_IN_343X }, 252 { .div = 13, .val = 13, .flags = RATE_IN_343X }, 253 { .div = 14, .val = 14, .flags = RATE_IN_343X }, 254 { .div = 15, .val = 15, .flags = RATE_IN_343X }, 255 { .div = 16, .val = 16, .flags = RATE_IN_343X }, 256 { .div = 0 } 257 }; 258 259 /* DPLL1 */ 260 /* MPU clock source */ 261 /* Type: DPLL */ 262 static struct dpll_data dpll1_dd = { 263 .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), 264 .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK, 265 .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK, 266 .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL), 267 .enable_mask = OMAP3430_EN_MPU_DPLL_MASK, 268 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 269 .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT, 270 .recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT, 271 .recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT, 272 .autoidle_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL), 273 .autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK, 274 .idlest_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), 275 .idlest_bit = OMAP3430_ST_MPU_CLK_SHIFT, 276 .max_multiplier = OMAP3_MAX_DPLL_MULT, 277 .max_divider = OMAP3_MAX_DPLL_DIV, 278 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE 279 }; 280 281 static struct clk dpll1_ck = { 282 .name = "dpll1_ck", 283 .parent = &sys_ck, 284 .dpll_data = &dpll1_dd, 285 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, 286 .round_rate = &omap2_dpll_round_rate, 287 .recalc = &omap3_dpll_recalc, 288 }; 289 290 /* 291 * This virtual clock provides the CLKOUTX2 output from the DPLL if the 292 * DPLL isn't bypassed. 293 */ 294 static struct clk dpll1_x2_ck = { 295 .name = "dpll1_x2_ck", 296 .parent = &dpll1_ck, 297 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 298 PARENT_CONTROLS_CLOCK, 299 .recalc = &omap3_clkoutx2_recalc, 300 }; 301 302 /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */ 303 static const struct clksel div16_dpll1_x2m2_clksel[] = { 304 { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates }, 305 { .parent = NULL } 306 }; 307 308 /* 309 * Does not exist in the TRM - needed to separate the M2 divider from 310 * bypass selection in mpu_ck 311 */ 312 static struct clk dpll1_x2m2_ck = { 313 .name = "dpll1_x2m2_ck", 314 .parent = &dpll1_x2_ck, 315 .init = &omap2_init_clksel_parent, 316 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL), 317 .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK, 318 .clksel = div16_dpll1_x2m2_clksel, 319 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 320 PARENT_CONTROLS_CLOCK, 321 .recalc = &omap2_clksel_recalc, 322 }; 323 324 /* DPLL2 */ 325 /* IVA2 clock source */ 326 /* Type: DPLL */ 327 328 static struct dpll_data dpll2_dd = { 329 .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), 330 .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK, 331 .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK, 332 .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL), 333 .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK, 334 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) | 335 (1 << DPLL_LOW_POWER_BYPASS), 336 .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT, 337 .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT, 338 .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT, 339 .autoidle_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL), 340 .autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK, 341 .idlest_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL), 342 .idlest_bit = OMAP3430_ST_IVA2_CLK_SHIFT, 343 .max_multiplier = OMAP3_MAX_DPLL_MULT, 344 .max_divider = OMAP3_MAX_DPLL_DIV, 345 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE 346 }; 347 348 static struct clk dpll2_ck = { 349 .name = "dpll2_ck", 350 .parent = &sys_ck, 351 .dpll_data = &dpll2_dd, 352 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 353 .enable = &omap3_noncore_dpll_enable, 354 .disable = &omap3_noncore_dpll_disable, 355 .round_rate = &omap2_dpll_round_rate, 356 .recalc = &omap3_dpll_recalc, 357 }; 358 359 static const struct clksel div16_dpll2_m2x2_clksel[] = { 360 { .parent = &dpll2_ck, .rates = div16_dpll_rates }, 361 { .parent = NULL } 362 }; 363 364 /* 365 * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT 366 * or CLKOUTX2. CLKOUT seems most plausible. 367 */ 368 static struct clk dpll2_m2_ck = { 369 .name = "dpll2_m2_ck", 370 .parent = &dpll2_ck, 371 .init = &omap2_init_clksel_parent, 372 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, 373 OMAP3430_CM_CLKSEL2_PLL), 374 .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK, 375 .clksel = div16_dpll2_m2x2_clksel, 376 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 377 PARENT_CONTROLS_CLOCK, 378 .recalc = &omap2_clksel_recalc, 379 }; 380 381 /* 382 * DPLL3 383 * Source clock for all interfaces and for some device fclks 384 * REVISIT: Also supports fast relock bypass - not included below 385 */ 386 static struct dpll_data dpll3_dd = { 387 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), 388 .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK, 389 .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK, 390 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 391 .enable_mask = OMAP3430_EN_CORE_DPLL_MASK, 392 .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT, 393 .recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT, 394 .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT, 395 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE), 396 .autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK, 397 .max_multiplier = OMAP3_MAX_DPLL_MULT, 398 .max_divider = OMAP3_MAX_DPLL_DIV, 399 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE 400 }; 401 402 static struct clk dpll3_ck = { 403 .name = "dpll3_ck", 404 .parent = &sys_ck, 405 .dpll_data = &dpll3_dd, 406 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, 407 .round_rate = &omap2_dpll_round_rate, 408 .recalc = &omap3_dpll_recalc, 409 }; 410 411 /* 412 * This virtual clock provides the CLKOUTX2 output from the DPLL if the 413 * DPLL isn't bypassed 414 */ 415 static struct clk dpll3_x2_ck = { 416 .name = "dpll3_x2_ck", 417 .parent = &dpll3_ck, 418 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 419 PARENT_CONTROLS_CLOCK, 420 .recalc = &omap3_clkoutx2_recalc, 421 }; 422 423 static const struct clksel_rate div31_dpll3_rates[] = { 424 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, 425 { .div = 2, .val = 2, .flags = RATE_IN_343X }, 426 { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 }, 427 { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 }, 428 { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 }, 429 { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 }, 430 { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 }, 431 { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 }, 432 { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 }, 433 { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 }, 434 { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 }, 435 { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 }, 436 { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 }, 437 { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 }, 438 { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 }, 439 { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 }, 440 { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 }, 441 { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 }, 442 { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 }, 443 { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 }, 444 { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 }, 445 { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 }, 446 { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 }, 447 { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 }, 448 { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 }, 449 { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 }, 450 { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 }, 451 { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 }, 452 { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 }, 453 { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 }, 454 { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 }, 455 { .div = 0 }, 456 }; 457 458 static const struct clksel div31_dpll3m2_clksel[] = { 459 { .parent = &dpll3_ck, .rates = div31_dpll3_rates }, 460 { .parent = NULL } 461 }; 462 463 /* 464 * DPLL3 output M2 465 * REVISIT: This DPLL output divider must be changed in SRAM, so until 466 * that code is ready, this should remain a 'read-only' clksel clock. 467 */ 468 static struct clk dpll3_m2_ck = { 469 .name = "dpll3_m2_ck", 470 .parent = &dpll3_ck, 471 .init = &omap2_init_clksel_parent, 472 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), 473 .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK, 474 .clksel = div31_dpll3m2_clksel, 475 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 476 PARENT_CONTROLS_CLOCK, 477 .recalc = &omap2_clksel_recalc, 478 }; 479 480 static const struct clksel core_ck_clksel[] = { 481 { .parent = &sys_ck, .rates = dpll_bypass_rates }, 482 { .parent = &dpll3_m2_ck, .rates = dpll_locked_rates }, 483 { .parent = NULL } 484 }; 485 486 static struct clk core_ck = { 487 .name = "core_ck", 488 .init = &omap2_init_clksel_parent, 489 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), 490 .clksel_mask = OMAP3430_ST_CORE_CLK_MASK, 491 .clksel = core_ck_clksel, 492 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 493 PARENT_CONTROLS_CLOCK, 494 .recalc = &omap2_clksel_recalc, 495 }; 496 497 static const struct clksel dpll3_m2x2_ck_clksel[] = { 498 { .parent = &sys_ck, .rates = dpll_bypass_rates }, 499 { .parent = &dpll3_x2_ck, .rates = dpll_locked_rates }, 500 { .parent = NULL } 501 }; 502 503 static struct clk dpll3_m2x2_ck = { 504 .name = "dpll3_m2x2_ck", 505 .init = &omap2_init_clksel_parent, 506 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), 507 .clksel_mask = OMAP3430_ST_CORE_CLK_MASK, 508 .clksel = dpll3_m2x2_ck_clksel, 509 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 510 PARENT_CONTROLS_CLOCK, 511 .recalc = &omap2_clksel_recalc, 512 }; 513 514 /* The PWRDN bit is apparently only available on 3430ES2 and above */ 515 static const struct clksel div16_dpll3_clksel[] = { 516 { .parent = &dpll3_ck, .rates = div16_dpll_rates }, 517 { .parent = NULL } 518 }; 519 520 /* This virtual clock is the source for dpll3_m3x2_ck */ 521 static struct clk dpll3_m3_ck = { 522 .name = "dpll3_m3_ck", 523 .parent = &dpll3_ck, 524 .init = &omap2_init_clksel_parent, 525 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), 526 .clksel_mask = OMAP3430_DIV_DPLL3_MASK, 527 .clksel = div16_dpll3_clksel, 528 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 529 PARENT_CONTROLS_CLOCK, 530 .recalc = &omap2_clksel_recalc, 531 }; 532 533 /* The PWRDN bit is apparently only available on 3430ES2 and above */ 534 static struct clk dpll3_m3x2_ck = { 535 .name = "dpll3_m3x2_ck", 536 .parent = &dpll3_m3_ck, 537 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 538 .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT, 539 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, 540 .recalc = &omap3_clkoutx2_recalc, 541 }; 542 543 static const struct clksel emu_core_alwon_ck_clksel[] = { 544 { .parent = &sys_ck, .rates = dpll_bypass_rates }, 545 { .parent = &dpll3_m3x2_ck, .rates = dpll_locked_rates }, 546 { .parent = NULL } 547 }; 548 549 static struct clk emu_core_alwon_ck = { 550 .name = "emu_core_alwon_ck", 551 .parent = &dpll3_m3x2_ck, 552 .init = &omap2_init_clksel_parent, 553 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), 554 .clksel_mask = OMAP3430_ST_CORE_CLK_MASK, 555 .clksel = emu_core_alwon_ck_clksel, 556 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 557 PARENT_CONTROLS_CLOCK, 558 .recalc = &omap2_clksel_recalc, 559 }; 560 561 /* DPLL4 */ 562 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */ 563 /* Type: DPLL */ 564 static struct dpll_data dpll4_dd = { 565 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2), 566 .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK, 567 .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK, 568 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 569 .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK, 570 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), 571 .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT, 572 .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT, 573 .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT, 574 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE), 575 .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK, 576 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), 577 .idlest_bit = OMAP3430_ST_PERIPH_CLK_SHIFT, 578 .max_multiplier = OMAP3_MAX_DPLL_MULT, 579 .max_divider = OMAP3_MAX_DPLL_DIV, 580 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE 581 }; 582 583 static struct clk dpll4_ck = { 584 .name = "dpll4_ck", 585 .parent = &sys_ck, 586 .dpll_data = &dpll4_dd, 587 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 588 .enable = &omap3_noncore_dpll_enable, 589 .disable = &omap3_noncore_dpll_disable, 590 .round_rate = &omap2_dpll_round_rate, 591 .recalc = &omap3_dpll_recalc, 592 }; 593 594 /* 595 * This virtual clock provides the CLKOUTX2 output from the DPLL if the 596 * DPLL isn't bypassed -- 597 * XXX does this serve any downstream clocks? 598 */ 599 static struct clk dpll4_x2_ck = { 600 .name = "dpll4_x2_ck", 601 .parent = &dpll4_ck, 602 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 603 PARENT_CONTROLS_CLOCK, 604 .recalc = &omap3_clkoutx2_recalc, 605 }; 606 607 static const struct clksel div16_dpll4_clksel[] = { 608 { .parent = &dpll4_ck, .rates = div16_dpll_rates }, 609 { .parent = NULL } 610 }; 611 612 /* This virtual clock is the source for dpll4_m2x2_ck */ 613 static struct clk dpll4_m2_ck = { 614 .name = "dpll4_m2_ck", 615 .parent = &dpll4_ck, 616 .init = &omap2_init_clksel_parent, 617 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3), 618 .clksel_mask = OMAP3430_DIV_96M_MASK, 619 .clksel = div16_dpll4_clksel, 620 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 621 PARENT_CONTROLS_CLOCK, 622 .recalc = &omap2_clksel_recalc, 623 }; 624 625 /* The PWRDN bit is apparently only available on 3430ES2 and above */ 626 static struct clk dpll4_m2x2_ck = { 627 .name = "dpll4_m2x2_ck", 628 .parent = &dpll4_m2_ck, 629 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 630 .enable_bit = OMAP3430_PWRDN_96M_SHIFT, 631 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, 632 .recalc = &omap3_clkoutx2_recalc, 633 }; 634 635 static const struct clksel omap_96m_alwon_fck_clksel[] = { 636 { .parent = &sys_ck, .rates = dpll_bypass_rates }, 637 { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates }, 638 { .parent = NULL } 639 }; 640 641 static struct clk omap_96m_alwon_fck = { 642 .name = "omap_96m_alwon_fck", 643 .parent = &dpll4_m2x2_ck, 644 .init = &omap2_init_clksel_parent, 645 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), 646 .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, 647 .clksel = omap_96m_alwon_fck_clksel, 648 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 649 PARENT_CONTROLS_CLOCK, 650 .recalc = &omap2_clksel_recalc, 651 }; 652 653 static struct clk omap_96m_fck = { 654 .name = "omap_96m_fck", 655 .parent = &omap_96m_alwon_fck, 656 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 657 PARENT_CONTROLS_CLOCK, 658 .recalc = &followparent_recalc, 659 }; 660 661 static const struct clksel cm_96m_fck_clksel[] = { 662 { .parent = &sys_ck, .rates = dpll_bypass_rates }, 663 { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates }, 664 { .parent = NULL } 665 }; 666 667 static struct clk cm_96m_fck = { 668 .name = "cm_96m_fck", 669 .parent = &dpll4_m2x2_ck, 670 .init = &omap2_init_clksel_parent, 671 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), 672 .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, 673 .clksel = cm_96m_fck_clksel, 674 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 675 PARENT_CONTROLS_CLOCK, 676 .recalc = &omap2_clksel_recalc, 677 }; 678 679 /* This virtual clock is the source for dpll4_m3x2_ck */ 680 static struct clk dpll4_m3_ck = { 681 .name = "dpll4_m3_ck", 682 .parent = &dpll4_ck, 683 .init = &omap2_init_clksel_parent, 684 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), 685 .clksel_mask = OMAP3430_CLKSEL_TV_MASK, 686 .clksel = div16_dpll4_clksel, 687 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 688 PARENT_CONTROLS_CLOCK, 689 .recalc = &omap2_clksel_recalc, 690 }; 691 692 /* The PWRDN bit is apparently only available on 3430ES2 and above */ 693 static struct clk dpll4_m3x2_ck = { 694 .name = "dpll4_m3x2_ck", 695 .parent = &dpll4_m3_ck, 696 .init = &omap2_init_clksel_parent, 697 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 698 .enable_bit = OMAP3430_PWRDN_TV_SHIFT, 699 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, 700 .recalc = &omap3_clkoutx2_recalc, 701 }; 702 703 static const struct clksel virt_omap_54m_fck_clksel[] = { 704 { .parent = &sys_ck, .rates = dpll_bypass_rates }, 705 { .parent = &dpll4_m3x2_ck, .rates = dpll_locked_rates }, 706 { .parent = NULL } 707 }; 708 709 static struct clk virt_omap_54m_fck = { 710 .name = "virt_omap_54m_fck", 711 .parent = &dpll4_m3x2_ck, 712 .init = &omap2_init_clksel_parent, 713 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), 714 .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, 715 .clksel = virt_omap_54m_fck_clksel, 716 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 717 PARENT_CONTROLS_CLOCK, 718 .recalc = &omap2_clksel_recalc, 719 }; 720 721 static const struct clksel_rate omap_54m_d4m3x2_rates[] = { 722 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, 723 { .div = 0 } 724 }; 725 726 static const struct clksel_rate omap_54m_alt_rates[] = { 727 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, 728 { .div = 0 } 729 }; 730 731 static const struct clksel omap_54m_clksel[] = { 732 { .parent = &virt_omap_54m_fck, .rates = omap_54m_d4m3x2_rates }, 733 { .parent = &sys_altclk, .rates = omap_54m_alt_rates }, 734 { .parent = NULL } 735 }; 736 737 static struct clk omap_54m_fck = { 738 .name = "omap_54m_fck", 739 .init = &omap2_init_clksel_parent, 740 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), 741 .clksel_mask = OMAP3430_SOURCE_54M, 742 .clksel = omap_54m_clksel, 743 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 744 PARENT_CONTROLS_CLOCK, 745 .recalc = &omap2_clksel_recalc, 746 }; 747 748 static const struct clksel_rate omap_48m_96md2_rates[] = { 749 { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, 750 { .div = 0 } 751 }; 752 753 static const struct clksel_rate omap_48m_alt_rates[] = { 754 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, 755 { .div = 0 } 756 }; 757 758 static const struct clksel omap_48m_clksel[] = { 759 { .parent = &cm_96m_fck, .rates = omap_48m_96md2_rates }, 760 { .parent = &sys_altclk, .rates = omap_48m_alt_rates }, 761 { .parent = NULL } 762 }; 763 764 static struct clk omap_48m_fck = { 765 .name = "omap_48m_fck", 766 .init = &omap2_init_clksel_parent, 767 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), 768 .clksel_mask = OMAP3430_SOURCE_48M, 769 .clksel = omap_48m_clksel, 770 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 771 PARENT_CONTROLS_CLOCK, 772 .recalc = &omap2_clksel_recalc, 773 }; 774 775 static struct clk omap_12m_fck = { 776 .name = "omap_12m_fck", 777 .parent = &omap_48m_fck, 778 .fixed_div = 4, 779 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 780 PARENT_CONTROLS_CLOCK, 781 .recalc = &omap2_fixed_divisor_recalc, 782 }; 783 784 /* This virstual clock is the source for dpll4_m4x2_ck */ 785 static struct clk dpll4_m4_ck = { 786 .name = "dpll4_m4_ck", 787 .parent = &dpll4_ck, 788 .init = &omap2_init_clksel_parent, 789 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), 790 .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK, 791 .clksel = div16_dpll4_clksel, 792 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 793 PARENT_CONTROLS_CLOCK, 794 .recalc = &omap2_clksel_recalc, 795 }; 796 797 /* The PWRDN bit is apparently only available on 3430ES2 and above */ 798 static struct clk dpll4_m4x2_ck = { 799 .name = "dpll4_m4x2_ck", 800 .parent = &dpll4_m4_ck, 801 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 802 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT, 803 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, 804 .recalc = &omap3_clkoutx2_recalc, 805 }; 806 807 /* This virtual clock is the source for dpll4_m5x2_ck */ 808 static struct clk dpll4_m5_ck = { 809 .name = "dpll4_m5_ck", 810 .parent = &dpll4_ck, 811 .init = &omap2_init_clksel_parent, 812 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL), 813 .clksel_mask = OMAP3430_CLKSEL_CAM_MASK, 814 .clksel = div16_dpll4_clksel, 815 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 816 PARENT_CONTROLS_CLOCK, 817 .recalc = &omap2_clksel_recalc, 818 }; 819 820 /* The PWRDN bit is apparently only available on 3430ES2 and above */ 821 static struct clk dpll4_m5x2_ck = { 822 .name = "dpll4_m5x2_ck", 823 .parent = &dpll4_m5_ck, 824 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 825 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT, 826 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, 827 .recalc = &omap3_clkoutx2_recalc, 828 }; 829 830 /* This virtual clock is the source for dpll4_m6x2_ck */ 831 static struct clk dpll4_m6_ck = { 832 .name = "dpll4_m6_ck", 833 .parent = &dpll4_ck, 834 .init = &omap2_init_clksel_parent, 835 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), 836 .clksel_mask = OMAP3430_DIV_DPLL4_MASK, 837 .clksel = div16_dpll4_clksel, 838 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 839 PARENT_CONTROLS_CLOCK, 840 .recalc = &omap2_clksel_recalc, 841 }; 842 843 /* The PWRDN bit is apparently only available on 3430ES2 and above */ 844 static struct clk dpll4_m6x2_ck = { 845 .name = "dpll4_m6x2_ck", 846 .parent = &dpll4_m6_ck, 847 .init = &omap2_init_clksel_parent, 848 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 849 .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT, 850 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, 851 .recalc = &omap3_clkoutx2_recalc, 852 }; 853 854 static struct clk emu_per_alwon_ck = { 855 .name = "emu_per_alwon_ck", 856 .parent = &dpll4_m6x2_ck, 857 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 858 PARENT_CONTROLS_CLOCK, 859 .recalc = &followparent_recalc, 860 }; 861 862 /* DPLL5 */ 863 /* Supplies 120MHz clock, USIM source clock */ 864 /* Type: DPLL */ 865 /* 3430ES2 only */ 866 static struct dpll_data dpll5_dd = { 867 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4), 868 .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK, 869 .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK, 870 .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2), 871 .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK, 872 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), 873 .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT, 874 .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT, 875 .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT, 876 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL), 877 .autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK, 878 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2), 879 .idlest_bit = OMAP3430ES2_ST_PERIPH2_CLK_SHIFT, 880 .max_multiplier = OMAP3_MAX_DPLL_MULT, 881 .max_divider = OMAP3_MAX_DPLL_DIV, 882 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE 883 }; 884 885 static struct clk dpll5_ck = { 886 .name = "dpll5_ck", 887 .parent = &sys_ck, 888 .dpll_data = &dpll5_dd, 889 .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES, 890 .enable = &omap3_noncore_dpll_enable, 891 .disable = &omap3_noncore_dpll_disable, 892 .round_rate = &omap2_dpll_round_rate, 893 .recalc = &omap3_dpll_recalc, 894 }; 895 896 static const struct clksel div16_dpll5_clksel[] = { 897 { .parent = &dpll5_ck, .rates = div16_dpll_rates }, 898 { .parent = NULL } 899 }; 900 901 static struct clk dpll5_m2_ck = { 902 .name = "dpll5_m2_ck", 903 .parent = &dpll5_ck, 904 .init = &omap2_init_clksel_parent, 905 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5), 906 .clksel_mask = OMAP3430ES2_DIV_120M_MASK, 907 .clksel = div16_dpll5_clksel, 908 .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES | 909 PARENT_CONTROLS_CLOCK, 910 .recalc = &omap2_clksel_recalc, 911 }; 912 913 static const struct clksel omap_120m_fck_clksel[] = { 914 { .parent = &sys_ck, .rates = dpll_bypass_rates }, 915 { .parent = &dpll5_m2_ck, .rates = dpll_locked_rates }, 916 { .parent = NULL } 917 }; 918 919 static struct clk omap_120m_fck = { 920 .name = "omap_120m_fck", 921 .parent = &dpll5_m2_ck, 922 .init = &omap2_init_clksel_parent, 923 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2), 924 .clksel_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK, 925 .clksel = omap_120m_fck_clksel, 926 .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES | 927 PARENT_CONTROLS_CLOCK, 928 .recalc = &omap2_clksel_recalc, 929 }; 930 931 /* CM EXTERNAL CLOCK OUTPUTS */ 932 933 static const struct clksel_rate clkout2_src_core_rates[] = { 934 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, 935 { .div = 0 } 936 }; 937 938 static const struct clksel_rate clkout2_src_sys_rates[] = { 939 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, 940 { .div = 0 } 941 }; 942 943 static const struct clksel_rate clkout2_src_96m_rates[] = { 944 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, 945 { .div = 0 } 946 }; 947 948 static const struct clksel_rate clkout2_src_54m_rates[] = { 949 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, 950 { .div = 0 } 951 }; 952 953 static const struct clksel clkout2_src_clksel[] = { 954 { .parent = &core_ck, .rates = clkout2_src_core_rates }, 955 { .parent = &sys_ck, .rates = clkout2_src_sys_rates }, 956 { .parent = &omap_96m_alwon_fck, .rates = clkout2_src_96m_rates }, 957 { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates }, 958 { .parent = NULL } 959 }; 960 961 static struct clk clkout2_src_ck = { 962 .name = "clkout2_src_ck", 963 .init = &omap2_init_clksel_parent, 964 .enable_reg = OMAP3430_CM_CLKOUT_CTRL, 965 .enable_bit = OMAP3430_CLKOUT2_EN_SHIFT, 966 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL, 967 .clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK, 968 .clksel = clkout2_src_clksel, 969 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 970 .recalc = &omap2_clksel_recalc, 971 }; 972 973 static const struct clksel_rate sys_clkout2_rates[] = { 974 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, 975 { .div = 2, .val = 1, .flags = RATE_IN_343X }, 976 { .div = 4, .val = 2, .flags = RATE_IN_343X }, 977 { .div = 8, .val = 3, .flags = RATE_IN_343X }, 978 { .div = 16, .val = 4, .flags = RATE_IN_343X }, 979 { .div = 0 }, 980 }; 981 982 static const struct clksel sys_clkout2_clksel[] = { 983 { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates }, 984 { .parent = NULL }, 985 }; 986 987 static struct clk sys_clkout2 = { 988 .name = "sys_clkout2", 989 .init = &omap2_init_clksel_parent, 990 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL, 991 .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK, 992 .clksel = sys_clkout2_clksel, 993 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, 994 .recalc = &omap2_clksel_recalc, 995 }; 996 997 /* CM OUTPUT CLOCKS */ 998 999 static struct clk corex2_fck = { 1000 .name = "corex2_fck", 1001 .parent = &dpll3_m2x2_ck, 1002 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 1003 PARENT_CONTROLS_CLOCK, 1004 .recalc = &followparent_recalc, 1005 }; 1006 1007 /* DPLL power domain clock controls */ 1008 1009 static const struct clksel div2_core_clksel[] = { 1010 { .parent = &core_ck, .rates = div2_rates }, 1011 { .parent = NULL } 1012 }; 1013 1014 /* 1015 * REVISIT: Are these in DPLL power domain or CM power domain? docs 1016 * may be inconsistent here? 1017 */ 1018 static struct clk dpll1_fck = { 1019 .name = "dpll1_fck", 1020 .parent = &core_ck, 1021 .init = &omap2_init_clksel_parent, 1022 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), 1023 .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK, 1024 .clksel = div2_core_clksel, 1025 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 1026 PARENT_CONTROLS_CLOCK, 1027 .recalc = &omap2_clksel_recalc, 1028 }; 1029 1030 /* 1031 * MPU clksel: 1032 * If DPLL1 is locked, mpu_ck derives from DPLL1; otherwise, mpu_ck 1033 * derives from the high-frequency bypass clock originating from DPLL3, 1034 * called 'dpll1_fck' 1035 */ 1036 static const struct clksel mpu_clksel[] = { 1037 { .parent = &dpll1_fck, .rates = dpll_bypass_rates }, 1038 { .parent = &dpll1_x2m2_ck, .rates = dpll_locked_rates }, 1039 { .parent = NULL } 1040 }; 1041 1042 static struct clk mpu_ck = { 1043 .name = "mpu_ck", 1044 .parent = &dpll1_x2m2_ck, 1045 .init = &omap2_init_clksel_parent, 1046 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), 1047 .clksel_mask = OMAP3430_ST_MPU_CLK_MASK, 1048 .clksel = mpu_clksel, 1049 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 1050 PARENT_CONTROLS_CLOCK, 1051 .clkdm_name = "mpu_clkdm", 1052 .recalc = &omap2_clksel_recalc, 1053 }; 1054 1055 /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */ 1056 static const struct clksel_rate arm_fck_rates[] = { 1057 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, 1058 { .div = 2, .val = 1, .flags = RATE_IN_343X }, 1059 { .div = 0 }, 1060 }; 1061 1062 static const struct clksel arm_fck_clksel[] = { 1063 { .parent = &mpu_ck, .rates = arm_fck_rates }, 1064 { .parent = NULL } 1065 }; 1066 1067 static struct clk arm_fck = { 1068 .name = "arm_fck", 1069 .parent = &mpu_ck, 1070 .init = &omap2_init_clksel_parent, 1071 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), 1072 .clksel_mask = OMAP3430_ST_MPU_CLK_MASK, 1073 .clksel = arm_fck_clksel, 1074 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 1075 PARENT_CONTROLS_CLOCK, 1076 .recalc = &omap2_clksel_recalc, 1077 }; 1078 1079 /* XXX What about neon_clkdm ? */ 1080 1081 /* 1082 * REVISIT: This clock is never specifically defined in the 3430 TRM, 1083 * although it is referenced - so this is a guess 1084 */ 1085 static struct clk emu_mpu_alwon_ck = { 1086 .name = "emu_mpu_alwon_ck", 1087 .parent = &mpu_ck, 1088 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 1089 PARENT_CONTROLS_CLOCK, 1090 .recalc = &followparent_recalc, 1091 }; 1092 1093 static struct clk dpll2_fck = { 1094 .name = "dpll2_fck", 1095 .parent = &core_ck, 1096 .init = &omap2_init_clksel_parent, 1097 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), 1098 .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK, 1099 .clksel = div2_core_clksel, 1100 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 1101 PARENT_CONTROLS_CLOCK, 1102 .recalc = &omap2_clksel_recalc, 1103 }; 1104 1105 /* 1106 * IVA2 clksel: 1107 * If DPLL2 is locked, iva2_ck derives from DPLL2; otherwise, iva2_ck 1108 * derives from the high-frequency bypass clock originating from DPLL3, 1109 * called 'dpll2_fck' 1110 */ 1111 1112 static const struct clksel iva2_clksel[] = { 1113 { .parent = &dpll2_fck, .rates = dpll_bypass_rates }, 1114 { .parent = &dpll2_m2_ck, .rates = dpll_locked_rates }, 1115 { .parent = NULL } 1116 }; 1117 1118 static struct clk iva2_ck = { 1119 .name = "iva2_ck", 1120 .parent = &dpll2_m2_ck, 1121 .init = &omap2_init_clksel_parent, 1122 .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN), 1123 .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT, 1124 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, 1125 OMAP3430_CM_IDLEST_PLL), 1126 .clksel_mask = OMAP3430_ST_IVA2_CLK_MASK, 1127 .clksel = iva2_clksel, 1128 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 1129 .clkdm_name = "iva2_clkdm", 1130 .recalc = &omap2_clksel_recalc, 1131 }; 1132 1133 /* Common interface clocks */ 1134 1135 static struct clk l3_ick = { 1136 .name = "l3_ick", 1137 .parent = &core_ck, 1138 .init = &omap2_init_clksel_parent, 1139 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), 1140 .clksel_mask = OMAP3430_CLKSEL_L3_MASK, 1141 .clksel = div2_core_clksel, 1142 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 1143 PARENT_CONTROLS_CLOCK, 1144 .clkdm_name = "core_l3_clkdm", 1145 .recalc = &omap2_clksel_recalc, 1146 }; 1147 1148 static const struct clksel div2_l3_clksel[] = { 1149 { .parent = &l3_ick, .rates = div2_rates }, 1150 { .parent = NULL } 1151 }; 1152 1153 static struct clk l4_ick = { 1154 .name = "l4_ick", 1155 .parent = &l3_ick, 1156 .init = &omap2_init_clksel_parent, 1157 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), 1158 .clksel_mask = OMAP3430_CLKSEL_L4_MASK, 1159 .clksel = div2_l3_clksel, 1160 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 1161 PARENT_CONTROLS_CLOCK, 1162 .clkdm_name = "core_l4_clkdm", 1163 .recalc = &omap2_clksel_recalc, 1164 1165 }; 1166 1167 static const struct clksel div2_l4_clksel[] = { 1168 { .parent = &l4_ick, .rates = div2_rates }, 1169 { .parent = NULL } 1170 }; 1171 1172 static struct clk rm_ick = { 1173 .name = "rm_ick", 1174 .parent = &l4_ick, 1175 .init = &omap2_init_clksel_parent, 1176 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), 1177 .clksel_mask = OMAP3430_CLKSEL_RM_MASK, 1178 .clksel = div2_l4_clksel, 1179 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, 1180 .recalc = &omap2_clksel_recalc, 1181 }; 1182 1183 /* GFX power domain */ 1184 1185 /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */ 1186 1187 static const struct clksel gfx_l3_clksel[] = { 1188 { .parent = &l3_ick, .rates = gfx_l3_rates }, 1189 { .parent = NULL } 1190 }; 1191 1192 /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */ 1193 static struct clk gfx_l3_ck = { 1194 .name = "gfx_l3_ck", 1195 .parent = &l3_ick, 1196 .init = &omap2_init_clksel_parent, 1197 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), 1198 .enable_bit = OMAP_EN_GFX_SHIFT, 1199 .flags = CLOCK_IN_OMAP3430ES1, 1200 .recalc = &followparent_recalc, 1201 }; 1202 1203 static struct clk gfx_l3_fck = { 1204 .name = "gfx_l3_fck", 1205 .parent = &gfx_l3_ck, 1206 .init = &omap2_init_clksel_parent, 1207 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), 1208 .clksel_mask = OMAP_CLKSEL_GFX_MASK, 1209 .clksel = gfx_l3_clksel, 1210 .flags = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES | 1211 PARENT_CONTROLS_CLOCK, 1212 .clkdm_name = "gfx_3430es1_clkdm", 1213 .recalc = &omap2_clksel_recalc, 1214 }; 1215 1216 static struct clk gfx_l3_ick = { 1217 .name = "gfx_l3_ick", 1218 .parent = &gfx_l3_ck, 1219 .flags = CLOCK_IN_OMAP3430ES1 | PARENT_CONTROLS_CLOCK, 1220 .clkdm_name = "gfx_3430es1_clkdm", 1221 .recalc = &followparent_recalc, 1222 }; 1223 1224 static struct clk gfx_cg1_ck = { 1225 .name = "gfx_cg1_ck", 1226 .parent = &gfx_l3_fck, /* REVISIT: correct? */ 1227 .init = &omap2_init_clk_clkdm, 1228 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), 1229 .enable_bit = OMAP3430ES1_EN_2D_SHIFT, 1230 .flags = CLOCK_IN_OMAP3430ES1, 1231 .clkdm_name = "gfx_3430es1_clkdm", 1232 .recalc = &followparent_recalc, 1233 }; 1234 1235 static struct clk gfx_cg2_ck = { 1236 .name = "gfx_cg2_ck", 1237 .parent = &gfx_l3_fck, /* REVISIT: correct? */ 1238 .init = &omap2_init_clk_clkdm, 1239 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), 1240 .enable_bit = OMAP3430ES1_EN_3D_SHIFT, 1241 .flags = CLOCK_IN_OMAP3430ES1, 1242 .clkdm_name = "gfx_3430es1_clkdm", 1243 .recalc = &followparent_recalc, 1244 }; 1245 1246 /* SGX power domain - 3430ES2 only */ 1247 1248 static const struct clksel_rate sgx_core_rates[] = { 1249 { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, 1250 { .div = 4, .val = 1, .flags = RATE_IN_343X }, 1251 { .div = 6, .val = 2, .flags = RATE_IN_343X }, 1252 { .div = 0 }, 1253 }; 1254 1255 static const struct clksel_rate sgx_96m_rates[] = { 1256 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, 1257 { .div = 0 }, 1258 }; 1259 1260 static const struct clksel sgx_clksel[] = { 1261 { .parent = &core_ck, .rates = sgx_core_rates }, 1262 { .parent = &cm_96m_fck, .rates = sgx_96m_rates }, 1263 { .parent = NULL }, 1264 }; 1265 1266 static struct clk sgx_fck = { 1267 .name = "sgx_fck", 1268 .init = &omap2_init_clksel_parent, 1269 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN), 1270 .enable_bit = OMAP3430ES2_EN_SGX_SHIFT, 1271 .clksel_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL), 1272 .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK, 1273 .clksel = sgx_clksel, 1274 .flags = CLOCK_IN_OMAP3430ES2, 1275 .clkdm_name = "sgx_clkdm", 1276 .recalc = &omap2_clksel_recalc, 1277 }; 1278 1279 static struct clk sgx_ick = { 1280 .name = "sgx_ick", 1281 .parent = &l3_ick, 1282 .init = &omap2_init_clk_clkdm, 1283 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN), 1284 .enable_bit = OMAP3430ES2_EN_SGX_SHIFT, 1285 .flags = CLOCK_IN_OMAP3430ES2, 1286 .clkdm_name = "sgx_clkdm", 1287 .recalc = &followparent_recalc, 1288 }; 1289 1290 /* CORE power domain */ 1291 1292 static struct clk d2d_26m_fck = { 1293 .name = "d2d_26m_fck", 1294 .parent = &sys_ck, 1295 .init = &omap2_init_clk_clkdm, 1296 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1297 .enable_bit = OMAP3430ES1_EN_D2D_SHIFT, 1298 .flags = CLOCK_IN_OMAP3430ES1, 1299 .clkdm_name = "d2d_clkdm", 1300 .recalc = &followparent_recalc, 1301 }; 1302 1303 static const struct clksel omap343x_gpt_clksel[] = { 1304 { .parent = &omap_32k_fck, .rates = gpt_32k_rates }, 1305 { .parent = &sys_ck, .rates = gpt_sys_rates }, 1306 { .parent = NULL} 1307 }; 1308 1309 static struct clk gpt10_fck = { 1310 .name = "gpt10_fck", 1311 .parent = &sys_ck, 1312 .init = &omap2_init_clksel_parent, 1313 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1314 .enable_bit = OMAP3430_EN_GPT10_SHIFT, 1315 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), 1316 .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK, 1317 .clksel = omap343x_gpt_clksel, 1318 .flags = CLOCK_IN_OMAP343X, 1319 .clkdm_name = "core_l4_clkdm", 1320 .recalc = &omap2_clksel_recalc, 1321 }; 1322 1323 static struct clk gpt11_fck = { 1324 .name = "gpt11_fck", 1325 .parent = &sys_ck, 1326 .init = &omap2_init_clksel_parent, 1327 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1328 .enable_bit = OMAP3430_EN_GPT11_SHIFT, 1329 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), 1330 .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK, 1331 .clksel = omap343x_gpt_clksel, 1332 .flags = CLOCK_IN_OMAP343X, 1333 .clkdm_name = "core_l4_clkdm", 1334 .recalc = &omap2_clksel_recalc, 1335 }; 1336 1337 static struct clk cpefuse_fck = { 1338 .name = "cpefuse_fck", 1339 .parent = &sys_ck, 1340 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), 1341 .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT, 1342 .flags = CLOCK_IN_OMAP3430ES2, 1343 .recalc = &followparent_recalc, 1344 }; 1345 1346 static struct clk ts_fck = { 1347 .name = "ts_fck", 1348 .parent = &omap_32k_fck, 1349 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), 1350 .enable_bit = OMAP3430ES2_EN_TS_SHIFT, 1351 .flags = CLOCK_IN_OMAP3430ES2, 1352 .recalc = &followparent_recalc, 1353 }; 1354 1355 static struct clk usbtll_fck = { 1356 .name = "usbtll_fck", 1357 .parent = &omap_120m_fck, 1358 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), 1359 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, 1360 .flags = CLOCK_IN_OMAP3430ES2, 1361 .recalc = &followparent_recalc, 1362 }; 1363 1364 /* CORE 96M FCLK-derived clocks */ 1365 1366 static struct clk core_96m_fck = { 1367 .name = "core_96m_fck", 1368 .parent = &omap_96m_fck, 1369 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 1370 PARENT_CONTROLS_CLOCK, 1371 .clkdm_name = "core_l4_clkdm", 1372 .recalc = &followparent_recalc, 1373 }; 1374 1375 static struct clk mmchs3_fck = { 1376 .name = "mmchs_fck", 1377 .id = 2, 1378 .parent = &core_96m_fck, 1379 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1380 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, 1381 .flags = CLOCK_IN_OMAP3430ES2, 1382 .clkdm_name = "core_l4_clkdm", 1383 .recalc = &followparent_recalc, 1384 }; 1385 1386 static struct clk mmchs2_fck = { 1387 .name = "mmchs_fck", 1388 .id = 1, 1389 .parent = &core_96m_fck, 1390 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1391 .enable_bit = OMAP3430_EN_MMC2_SHIFT, 1392 .flags = CLOCK_IN_OMAP343X, 1393 .clkdm_name = "core_l4_clkdm", 1394 .recalc = &followparent_recalc, 1395 }; 1396 1397 static struct clk mspro_fck = { 1398 .name = "mspro_fck", 1399 .parent = &core_96m_fck, 1400 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1401 .enable_bit = OMAP3430_EN_MSPRO_SHIFT, 1402 .flags = CLOCK_IN_OMAP343X, 1403 .clkdm_name = "core_l4_clkdm", 1404 .recalc = &followparent_recalc, 1405 }; 1406 1407 static struct clk mmchs1_fck = { 1408 .name = "mmchs_fck", 1409 .parent = &core_96m_fck, 1410 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1411 .enable_bit = OMAP3430_EN_MMC1_SHIFT, 1412 .flags = CLOCK_IN_OMAP343X, 1413 .clkdm_name = "core_l4_clkdm", 1414 .recalc = &followparent_recalc, 1415 }; 1416 1417 static struct clk i2c3_fck = { 1418 .name = "i2c_fck", 1419 .id = 3, 1420 .parent = &core_96m_fck, 1421 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1422 .enable_bit = OMAP3430_EN_I2C3_SHIFT, 1423 .flags = CLOCK_IN_OMAP343X, 1424 .clkdm_name = "core_l4_clkdm", 1425 .recalc = &followparent_recalc, 1426 }; 1427 1428 static struct clk i2c2_fck = { 1429 .name = "i2c_fck", 1430 .id = 2, 1431 .parent = &core_96m_fck, 1432 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1433 .enable_bit = OMAP3430_EN_I2C2_SHIFT, 1434 .flags = CLOCK_IN_OMAP343X, 1435 .clkdm_name = "core_l4_clkdm", 1436 .recalc = &followparent_recalc, 1437 }; 1438 1439 static struct clk i2c1_fck = { 1440 .name = "i2c_fck", 1441 .id = 1, 1442 .parent = &core_96m_fck, 1443 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1444 .enable_bit = OMAP3430_EN_I2C1_SHIFT, 1445 .flags = CLOCK_IN_OMAP343X, 1446 .clkdm_name = "core_l4_clkdm", 1447 .recalc = &followparent_recalc, 1448 }; 1449 1450 /* 1451 * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck; 1452 * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck. 1453 */ 1454 static const struct clksel_rate common_mcbsp_96m_rates[] = { 1455 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, 1456 { .div = 0 } 1457 }; 1458 1459 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = { 1460 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, 1461 { .div = 0 } 1462 }; 1463 1464 static const struct clksel mcbsp_15_clksel[] = { 1465 { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates }, 1466 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, 1467 { .parent = NULL } 1468 }; 1469 1470 static struct clk mcbsp5_fck = { 1471 .name = "mcbsp_fck", 1472 .id = 5, 1473 .init = &omap2_init_clksel_parent, 1474 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1475 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, 1476 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), 1477 .clksel_mask = OMAP2_MCBSP5_CLKS_MASK, 1478 .clksel = mcbsp_15_clksel, 1479 .flags = CLOCK_IN_OMAP343X, 1480 .clkdm_name = "core_l4_clkdm", 1481 .recalc = &omap2_clksel_recalc, 1482 }; 1483 1484 static struct clk mcbsp1_fck = { 1485 .name = "mcbsp_fck", 1486 .id = 1, 1487 .init = &omap2_init_clksel_parent, 1488 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1489 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, 1490 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), 1491 .clksel_mask = OMAP2_MCBSP1_CLKS_MASK, 1492 .clksel = mcbsp_15_clksel, 1493 .flags = CLOCK_IN_OMAP343X, 1494 .clkdm_name = "core_l4_clkdm", 1495 .recalc = &omap2_clksel_recalc, 1496 }; 1497 1498 /* CORE_48M_FCK-derived clocks */ 1499 1500 static struct clk core_48m_fck = { 1501 .name = "core_48m_fck", 1502 .parent = &omap_48m_fck, 1503 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 1504 PARENT_CONTROLS_CLOCK, 1505 .clkdm_name = "core_l4_clkdm", 1506 .recalc = &followparent_recalc, 1507 }; 1508 1509 static struct clk mcspi4_fck = { 1510 .name = "mcspi_fck", 1511 .id = 4, 1512 .parent = &core_48m_fck, 1513 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1514 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, 1515 .flags = CLOCK_IN_OMAP343X, 1516 .recalc = &followparent_recalc, 1517 }; 1518 1519 static struct clk mcspi3_fck = { 1520 .name = "mcspi_fck", 1521 .id = 3, 1522 .parent = &core_48m_fck, 1523 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1524 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, 1525 .flags = CLOCK_IN_OMAP343X, 1526 .recalc = &followparent_recalc, 1527 }; 1528 1529 static struct clk mcspi2_fck = { 1530 .name = "mcspi_fck", 1531 .id = 2, 1532 .parent = &core_48m_fck, 1533 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1534 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, 1535 .flags = CLOCK_IN_OMAP343X, 1536 .recalc = &followparent_recalc, 1537 }; 1538 1539 static struct clk mcspi1_fck = { 1540 .name = "mcspi_fck", 1541 .id = 1, 1542 .parent = &core_48m_fck, 1543 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1544 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, 1545 .flags = CLOCK_IN_OMAP343X, 1546 .recalc = &followparent_recalc, 1547 }; 1548 1549 static struct clk uart2_fck = { 1550 .name = "uart2_fck", 1551 .parent = &core_48m_fck, 1552 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1553 .enable_bit = OMAP3430_EN_UART2_SHIFT, 1554 .flags = CLOCK_IN_OMAP343X, 1555 .recalc = &followparent_recalc, 1556 }; 1557 1558 static struct clk uart1_fck = { 1559 .name = "uart1_fck", 1560 .parent = &core_48m_fck, 1561 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1562 .enable_bit = OMAP3430_EN_UART1_SHIFT, 1563 .flags = CLOCK_IN_OMAP343X, 1564 .recalc = &followparent_recalc, 1565 }; 1566 1567 static struct clk fshostusb_fck = { 1568 .name = "fshostusb_fck", 1569 .parent = &core_48m_fck, 1570 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1571 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT, 1572 .flags = CLOCK_IN_OMAP3430ES1, 1573 .recalc = &followparent_recalc, 1574 }; 1575 1576 /* CORE_12M_FCK based clocks */ 1577 1578 static struct clk core_12m_fck = { 1579 .name = "core_12m_fck", 1580 .parent = &omap_12m_fck, 1581 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 1582 PARENT_CONTROLS_CLOCK, 1583 .clkdm_name = "core_l4_clkdm", 1584 .recalc = &followparent_recalc, 1585 }; 1586 1587 static struct clk hdq_fck = { 1588 .name = "hdq_fck", 1589 .parent = &core_12m_fck, 1590 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1591 .enable_bit = OMAP3430_EN_HDQ_SHIFT, 1592 .flags = CLOCK_IN_OMAP343X, 1593 .recalc = &followparent_recalc, 1594 }; 1595 1596 /* DPLL3-derived clock */ 1597 1598 static const struct clksel_rate ssi_ssr_corex2_rates[] = { 1599 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, 1600 { .div = 2, .val = 2, .flags = RATE_IN_343X }, 1601 { .div = 3, .val = 3, .flags = RATE_IN_343X }, 1602 { .div = 4, .val = 4, .flags = RATE_IN_343X }, 1603 { .div = 6, .val = 6, .flags = RATE_IN_343X }, 1604 { .div = 8, .val = 8, .flags = RATE_IN_343X }, 1605 { .div = 0 } 1606 }; 1607 1608 static const struct clksel ssi_ssr_clksel[] = { 1609 { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates }, 1610 { .parent = NULL } 1611 }; 1612 1613 static struct clk ssi_ssr_fck = { 1614 .name = "ssi_ssr_fck", 1615 .init = &omap2_init_clksel_parent, 1616 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1617 .enable_bit = OMAP3430_EN_SSI_SHIFT, 1618 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), 1619 .clksel_mask = OMAP3430_CLKSEL_SSI_MASK, 1620 .clksel = ssi_ssr_clksel, 1621 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 1622 .clkdm_name = "core_l4_clkdm", 1623 .recalc = &omap2_clksel_recalc, 1624 }; 1625 1626 static struct clk ssi_sst_fck = { 1627 .name = "ssi_sst_fck", 1628 .parent = &ssi_ssr_fck, 1629 .fixed_div = 2, 1630 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, 1631 .recalc = &omap2_fixed_divisor_recalc, 1632 }; 1633 1634 1635 1636 /* CORE_L3_ICK based clocks */ 1637 1638 /* 1639 * XXX must add clk_enable/clk_disable for these if standard code won't 1640 * handle it 1641 */ 1642 static struct clk core_l3_ick = { 1643 .name = "core_l3_ick", 1644 .parent = &l3_ick, 1645 .init = &omap2_init_clk_clkdm, 1646 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 1647 PARENT_CONTROLS_CLOCK, 1648 .clkdm_name = "core_l3_clkdm", 1649 .recalc = &followparent_recalc, 1650 }; 1651 1652 static struct clk hsotgusb_ick = { 1653 .name = "hsotgusb_ick", 1654 .parent = &core_l3_ick, 1655 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1656 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT, 1657 .flags = CLOCK_IN_OMAP343X, 1658 .clkdm_name = "core_l3_clkdm", 1659 .recalc = &followparent_recalc, 1660 }; 1661 1662 static struct clk sdrc_ick = { 1663 .name = "sdrc_ick", 1664 .parent = &core_l3_ick, 1665 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1666 .enable_bit = OMAP3430_EN_SDRC_SHIFT, 1667 .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT, 1668 .clkdm_name = "core_l3_clkdm", 1669 .recalc = &followparent_recalc, 1670 }; 1671 1672 static struct clk gpmc_fck = { 1673 .name = "gpmc_fck", 1674 .parent = &core_l3_ick, 1675 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK | 1676 ENABLE_ON_INIT, 1677 .clkdm_name = "core_l3_clkdm", 1678 .recalc = &followparent_recalc, 1679 }; 1680 1681 /* SECURITY_L3_ICK based clocks */ 1682 1683 static struct clk security_l3_ick = { 1684 .name = "security_l3_ick", 1685 .parent = &l3_ick, 1686 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 1687 PARENT_CONTROLS_CLOCK, 1688 .recalc = &followparent_recalc, 1689 }; 1690 1691 static struct clk pka_ick = { 1692 .name = "pka_ick", 1693 .parent = &security_l3_ick, 1694 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1695 .enable_bit = OMAP3430_EN_PKA_SHIFT, 1696 .flags = CLOCK_IN_OMAP343X, 1697 .recalc = &followparent_recalc, 1698 }; 1699 1700 /* CORE_L4_ICK based clocks */ 1701 1702 static struct clk core_l4_ick = { 1703 .name = "core_l4_ick", 1704 .parent = &l4_ick, 1705 .init = &omap2_init_clk_clkdm, 1706 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 1707 PARENT_CONTROLS_CLOCK, 1708 .clkdm_name = "core_l4_clkdm", 1709 .recalc = &followparent_recalc, 1710 }; 1711 1712 static struct clk usbtll_ick = { 1713 .name = "usbtll_ick", 1714 .parent = &core_l4_ick, 1715 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), 1716 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, 1717 .flags = CLOCK_IN_OMAP3430ES2, 1718 .clkdm_name = "core_l4_clkdm", 1719 .recalc = &followparent_recalc, 1720 }; 1721 1722 static struct clk mmchs3_ick = { 1723 .name = "mmchs_ick", 1724 .id = 2, 1725 .parent = &core_l4_ick, 1726 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1727 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, 1728 .flags = CLOCK_IN_OMAP3430ES2, 1729 .clkdm_name = "core_l4_clkdm", 1730 .recalc = &followparent_recalc, 1731 }; 1732 1733 /* Intersystem Communication Registers - chassis mode only */ 1734 static struct clk icr_ick = { 1735 .name = "icr_ick", 1736 .parent = &core_l4_ick, 1737 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1738 .enable_bit = OMAP3430_EN_ICR_SHIFT, 1739 .flags = CLOCK_IN_OMAP343X, 1740 .clkdm_name = "core_l4_clkdm", 1741 .recalc = &followparent_recalc, 1742 }; 1743 1744 static struct clk aes2_ick = { 1745 .name = "aes2_ick", 1746 .parent = &core_l4_ick, 1747 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1748 .enable_bit = OMAP3430_EN_AES2_SHIFT, 1749 .flags = CLOCK_IN_OMAP343X, 1750 .clkdm_name = "core_l4_clkdm", 1751 .recalc = &followparent_recalc, 1752 }; 1753 1754 static struct clk sha12_ick = { 1755 .name = "sha12_ick", 1756 .parent = &core_l4_ick, 1757 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1758 .enable_bit = OMAP3430_EN_SHA12_SHIFT, 1759 .flags = CLOCK_IN_OMAP343X, 1760 .clkdm_name = "core_l4_clkdm", 1761 .recalc = &followparent_recalc, 1762 }; 1763 1764 static struct clk des2_ick = { 1765 .name = "des2_ick", 1766 .parent = &core_l4_ick, 1767 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1768 .enable_bit = OMAP3430_EN_DES2_SHIFT, 1769 .flags = CLOCK_IN_OMAP343X, 1770 .clkdm_name = "core_l4_clkdm", 1771 .recalc = &followparent_recalc, 1772 }; 1773 1774 static struct clk mmchs2_ick = { 1775 .name = "mmchs_ick", 1776 .id = 1, 1777 .parent = &core_l4_ick, 1778 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1779 .enable_bit = OMAP3430_EN_MMC2_SHIFT, 1780 .flags = CLOCK_IN_OMAP343X, 1781 .clkdm_name = "core_l4_clkdm", 1782 .recalc = &followparent_recalc, 1783 }; 1784 1785 static struct clk mmchs1_ick = { 1786 .name = "mmchs_ick", 1787 .parent = &core_l4_ick, 1788 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1789 .enable_bit = OMAP3430_EN_MMC1_SHIFT, 1790 .flags = CLOCK_IN_OMAP343X, 1791 .clkdm_name = "core_l4_clkdm", 1792 .recalc = &followparent_recalc, 1793 }; 1794 1795 static struct clk mspro_ick = { 1796 .name = "mspro_ick", 1797 .parent = &core_l4_ick, 1798 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1799 .enable_bit = OMAP3430_EN_MSPRO_SHIFT, 1800 .flags = CLOCK_IN_OMAP343X, 1801 .clkdm_name = "core_l4_clkdm", 1802 .recalc = &followparent_recalc, 1803 }; 1804 1805 static struct clk hdq_ick = { 1806 .name = "hdq_ick", 1807 .parent = &core_l4_ick, 1808 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1809 .enable_bit = OMAP3430_EN_HDQ_SHIFT, 1810 .flags = CLOCK_IN_OMAP343X, 1811 .clkdm_name = "core_l4_clkdm", 1812 .recalc = &followparent_recalc, 1813 }; 1814 1815 static struct clk mcspi4_ick = { 1816 .name = "mcspi_ick", 1817 .id = 4, 1818 .parent = &core_l4_ick, 1819 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1820 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, 1821 .flags = CLOCK_IN_OMAP343X, 1822 .clkdm_name = "core_l4_clkdm", 1823 .recalc = &followparent_recalc, 1824 }; 1825 1826 static struct clk mcspi3_ick = { 1827 .name = "mcspi_ick", 1828 .id = 3, 1829 .parent = &core_l4_ick, 1830 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1831 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, 1832 .flags = CLOCK_IN_OMAP343X, 1833 .clkdm_name = "core_l4_clkdm", 1834 .recalc = &followparent_recalc, 1835 }; 1836 1837 static struct clk mcspi2_ick = { 1838 .name = "mcspi_ick", 1839 .id = 2, 1840 .parent = &core_l4_ick, 1841 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1842 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, 1843 .flags = CLOCK_IN_OMAP343X, 1844 .clkdm_name = "core_l4_clkdm", 1845 .recalc = &followparent_recalc, 1846 }; 1847 1848 static struct clk mcspi1_ick = { 1849 .name = "mcspi_ick", 1850 .id = 1, 1851 .parent = &core_l4_ick, 1852 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1853 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, 1854 .flags = CLOCK_IN_OMAP343X, 1855 .clkdm_name = "core_l4_clkdm", 1856 .recalc = &followparent_recalc, 1857 }; 1858 1859 static struct clk i2c3_ick = { 1860 .name = "i2c_ick", 1861 .id = 3, 1862 .parent = &core_l4_ick, 1863 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1864 .enable_bit = OMAP3430_EN_I2C3_SHIFT, 1865 .flags = CLOCK_IN_OMAP343X, 1866 .clkdm_name = "core_l4_clkdm", 1867 .recalc = &followparent_recalc, 1868 }; 1869 1870 static struct clk i2c2_ick = { 1871 .name = "i2c_ick", 1872 .id = 2, 1873 .parent = &core_l4_ick, 1874 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1875 .enable_bit = OMAP3430_EN_I2C2_SHIFT, 1876 .flags = CLOCK_IN_OMAP343X, 1877 .clkdm_name = "core_l4_clkdm", 1878 .recalc = &followparent_recalc, 1879 }; 1880 1881 static struct clk i2c1_ick = { 1882 .name = "i2c_ick", 1883 .id = 1, 1884 .parent = &core_l4_ick, 1885 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1886 .enable_bit = OMAP3430_EN_I2C1_SHIFT, 1887 .flags = CLOCK_IN_OMAP343X, 1888 .clkdm_name = "core_l4_clkdm", 1889 .recalc = &followparent_recalc, 1890 }; 1891 1892 static struct clk uart2_ick = { 1893 .name = "uart2_ick", 1894 .parent = &core_l4_ick, 1895 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1896 .enable_bit = OMAP3430_EN_UART2_SHIFT, 1897 .flags = CLOCK_IN_OMAP343X, 1898 .clkdm_name = "core_l4_clkdm", 1899 .recalc = &followparent_recalc, 1900 }; 1901 1902 static struct clk uart1_ick = { 1903 .name = "uart1_ick", 1904 .parent = &core_l4_ick, 1905 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1906 .enable_bit = OMAP3430_EN_UART1_SHIFT, 1907 .flags = CLOCK_IN_OMAP343X, 1908 .clkdm_name = "core_l4_clkdm", 1909 .recalc = &followparent_recalc, 1910 }; 1911 1912 static struct clk gpt11_ick = { 1913 .name = "gpt11_ick", 1914 .parent = &core_l4_ick, 1915 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1916 .enable_bit = OMAP3430_EN_GPT11_SHIFT, 1917 .flags = CLOCK_IN_OMAP343X, 1918 .clkdm_name = "core_l4_clkdm", 1919 .recalc = &followparent_recalc, 1920 }; 1921 1922 static struct clk gpt10_ick = { 1923 .name = "gpt10_ick", 1924 .parent = &core_l4_ick, 1925 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1926 .enable_bit = OMAP3430_EN_GPT10_SHIFT, 1927 .flags = CLOCK_IN_OMAP343X, 1928 .clkdm_name = "core_l4_clkdm", 1929 .recalc = &followparent_recalc, 1930 }; 1931 1932 static struct clk mcbsp5_ick = { 1933 .name = "mcbsp_ick", 1934 .id = 5, 1935 .parent = &core_l4_ick, 1936 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1937 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, 1938 .flags = CLOCK_IN_OMAP343X, 1939 .clkdm_name = "core_l4_clkdm", 1940 .recalc = &followparent_recalc, 1941 }; 1942 1943 static struct clk mcbsp1_ick = { 1944 .name = "mcbsp_ick", 1945 .id = 1, 1946 .parent = &core_l4_ick, 1947 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1948 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, 1949 .flags = CLOCK_IN_OMAP343X, 1950 .clkdm_name = "core_l4_clkdm", 1951 .recalc = &followparent_recalc, 1952 }; 1953 1954 static struct clk fac_ick = { 1955 .name = "fac_ick", 1956 .parent = &core_l4_ick, 1957 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1958 .enable_bit = OMAP3430ES1_EN_FAC_SHIFT, 1959 .flags = CLOCK_IN_OMAP3430ES1, 1960 .clkdm_name = "core_l4_clkdm", 1961 .recalc = &followparent_recalc, 1962 }; 1963 1964 static struct clk mailboxes_ick = { 1965 .name = "mailboxes_ick", 1966 .parent = &core_l4_ick, 1967 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1968 .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT, 1969 .flags = CLOCK_IN_OMAP343X, 1970 .clkdm_name = "core_l4_clkdm", 1971 .recalc = &followparent_recalc, 1972 }; 1973 1974 static struct clk omapctrl_ick = { 1975 .name = "omapctrl_ick", 1976 .parent = &core_l4_ick, 1977 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1978 .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT, 1979 .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT, 1980 .recalc = &followparent_recalc, 1981 }; 1982 1983 /* SSI_L4_ICK based clocks */ 1984 1985 static struct clk ssi_l4_ick = { 1986 .name = "ssi_l4_ick", 1987 .parent = &l4_ick, 1988 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 1989 PARENT_CONTROLS_CLOCK, 1990 .clkdm_name = "core_l4_clkdm", 1991 .recalc = &followparent_recalc, 1992 }; 1993 1994 static struct clk ssi_ick = { 1995 .name = "ssi_ick", 1996 .parent = &ssi_l4_ick, 1997 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1998 .enable_bit = OMAP3430_EN_SSI_SHIFT, 1999 .flags = CLOCK_IN_OMAP343X, 2000 .clkdm_name = "core_l4_clkdm", 2001 .recalc = &followparent_recalc, 2002 }; 2003 2004 /* REVISIT: Technically the TRM claims that this is CORE_CLK based, 2005 * but l4_ick makes more sense to me */ 2006 2007 static const struct clksel usb_l4_clksel[] = { 2008 { .parent = &l4_ick, .rates = div2_rates }, 2009 { .parent = NULL }, 2010 }; 2011 2012 static struct clk usb_l4_ick = { 2013 .name = "usb_l4_ick", 2014 .parent = &l4_ick, 2015 .init = &omap2_init_clksel_parent, 2016 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2017 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT, 2018 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), 2019 .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK, 2020 .clksel = usb_l4_clksel, 2021 .flags = CLOCK_IN_OMAP3430ES1, 2022 .recalc = &omap2_clksel_recalc, 2023 }; 2024 2025 /* XXX MDM_INTC_ICK, SAD2D_ICK ?? */ 2026 2027 /* SECURITY_L4_ICK2 based clocks */ 2028 2029 static struct clk security_l4_ick2 = { 2030 .name = "security_l4_ick2", 2031 .parent = &l4_ick, 2032 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 2033 PARENT_CONTROLS_CLOCK, 2034 .recalc = &followparent_recalc, 2035 }; 2036 2037 static struct clk aes1_ick = { 2038 .name = "aes1_ick", 2039 .parent = &security_l4_ick2, 2040 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 2041 .enable_bit = OMAP3430_EN_AES1_SHIFT, 2042 .flags = CLOCK_IN_OMAP343X, 2043 .recalc = &followparent_recalc, 2044 }; 2045 2046 static struct clk rng_ick = { 2047 .name = "rng_ick", 2048 .parent = &security_l4_ick2, 2049 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 2050 .enable_bit = OMAP3430_EN_RNG_SHIFT, 2051 .flags = CLOCK_IN_OMAP343X, 2052 .recalc = &followparent_recalc, 2053 }; 2054 2055 static struct clk sha11_ick = { 2056 .name = "sha11_ick", 2057 .parent = &security_l4_ick2, 2058 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 2059 .enable_bit = OMAP3430_EN_SHA11_SHIFT, 2060 .flags = CLOCK_IN_OMAP343X, 2061 .recalc = &followparent_recalc, 2062 }; 2063 2064 static struct clk des1_ick = { 2065 .name = "des1_ick", 2066 .parent = &security_l4_ick2, 2067 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 2068 .enable_bit = OMAP3430_EN_DES1_SHIFT, 2069 .flags = CLOCK_IN_OMAP343X, 2070 .recalc = &followparent_recalc, 2071 }; 2072 2073 /* DSS */ 2074 static const struct clksel dss1_alwon_fck_clksel[] = { 2075 { .parent = &sys_ck, .rates = dpll_bypass_rates }, 2076 { .parent = &dpll4_m4x2_ck, .rates = dpll_locked_rates }, 2077 { .parent = NULL } 2078 }; 2079 2080 static struct clk dss1_alwon_fck = { 2081 .name = "dss1_alwon_fck", 2082 .parent = &dpll4_m4x2_ck, 2083 .init = &omap2_init_clksel_parent, 2084 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), 2085 .enable_bit = OMAP3430_EN_DSS1_SHIFT, 2086 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), 2087 .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, 2088 .clksel = dss1_alwon_fck_clksel, 2089 .flags = CLOCK_IN_OMAP343X, 2090 .clkdm_name = "dss_clkdm", 2091 .recalc = &omap2_clksel_recalc, 2092 }; 2093 2094 static struct clk dss_tv_fck = { 2095 .name = "dss_tv_fck", 2096 .parent = &omap_54m_fck, 2097 .init = &omap2_init_clk_clkdm, 2098 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), 2099 .enable_bit = OMAP3430_EN_TV_SHIFT, 2100 .flags = CLOCK_IN_OMAP343X, 2101 .clkdm_name = "dss_clkdm", 2102 .recalc = &followparent_recalc, 2103 }; 2104 2105 static struct clk dss_96m_fck = { 2106 .name = "dss_96m_fck", 2107 .parent = &omap_96m_fck, 2108 .init = &omap2_init_clk_clkdm, 2109 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), 2110 .enable_bit = OMAP3430_EN_TV_SHIFT, 2111 .flags = CLOCK_IN_OMAP343X, 2112 .clkdm_name = "dss_clkdm", 2113 .recalc = &followparent_recalc, 2114 }; 2115 2116 static struct clk dss2_alwon_fck = { 2117 .name = "dss2_alwon_fck", 2118 .parent = &sys_ck, 2119 .init = &omap2_init_clk_clkdm, 2120 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), 2121 .enable_bit = OMAP3430_EN_DSS2_SHIFT, 2122 .flags = CLOCK_IN_OMAP343X, 2123 .clkdm_name = "dss_clkdm", 2124 .recalc = &followparent_recalc, 2125 }; 2126 2127 static struct clk dss_ick = { 2128 /* Handles both L3 and L4 clocks */ 2129 .name = "dss_ick", 2130 .parent = &l4_ick, 2131 .init = &omap2_init_clk_clkdm, 2132 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), 2133 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT, 2134 .flags = CLOCK_IN_OMAP343X, 2135 .clkdm_name = "dss_clkdm", 2136 .recalc = &followparent_recalc, 2137 }; 2138 2139 /* CAM */ 2140 2141 static const struct clksel cam_mclk_clksel[] = { 2142 { .parent = &sys_ck, .rates = dpll_bypass_rates }, 2143 { .parent = &dpll4_m5x2_ck, .rates = dpll_locked_rates }, 2144 { .parent = NULL } 2145 }; 2146 2147 static struct clk cam_mclk = { 2148 .name = "cam_mclk", 2149 .parent = &dpll4_m5x2_ck, 2150 .init = &omap2_init_clksel_parent, 2151 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), 2152 .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, 2153 .clksel = cam_mclk_clksel, 2154 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN), 2155 .enable_bit = OMAP3430_EN_CAM_SHIFT, 2156 .flags = CLOCK_IN_OMAP343X, 2157 .clkdm_name = "cam_clkdm", 2158 .recalc = &omap2_clksel_recalc, 2159 }; 2160 2161 static struct clk cam_ick = { 2162 /* Handles both L3 and L4 clocks */ 2163 .name = "cam_ick", 2164 .parent = &l4_ick, 2165 .init = &omap2_init_clk_clkdm, 2166 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN), 2167 .enable_bit = OMAP3430_EN_CAM_SHIFT, 2168 .flags = CLOCK_IN_OMAP343X, 2169 .clkdm_name = "cam_clkdm", 2170 .recalc = &followparent_recalc, 2171 }; 2172 2173 /* USBHOST - 3430ES2 only */ 2174 2175 static struct clk usbhost_120m_fck = { 2176 .name = "usbhost_120m_fck", 2177 .parent = &omap_120m_fck, 2178 .init = &omap2_init_clk_clkdm, 2179 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), 2180 .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT, 2181 .flags = CLOCK_IN_OMAP3430ES2, 2182 .clkdm_name = "usbhost_clkdm", 2183 .recalc = &followparent_recalc, 2184 }; 2185 2186 static struct clk usbhost_48m_fck = { 2187 .name = "usbhost_48m_fck", 2188 .parent = &omap_48m_fck, 2189 .init = &omap2_init_clk_clkdm, 2190 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), 2191 .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT, 2192 .flags = CLOCK_IN_OMAP3430ES2, 2193 .clkdm_name = "usbhost_clkdm", 2194 .recalc = &followparent_recalc, 2195 }; 2196 2197 static struct clk usbhost_ick = { 2198 /* Handles both L3 and L4 clocks */ 2199 .name = "usbhost_ick", 2200 .parent = &l4_ick, 2201 .init = &omap2_init_clk_clkdm, 2202 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN), 2203 .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT, 2204 .flags = CLOCK_IN_OMAP3430ES2, 2205 .clkdm_name = "usbhost_clkdm", 2206 .recalc = &followparent_recalc, 2207 }; 2208 2209 static struct clk usbhost_sar_fck = { 2210 .name = "usbhost_sar_fck", 2211 .parent = &osc_sys_ck, 2212 .init = &omap2_init_clk_clkdm, 2213 .enable_reg = OMAP_PRM_REGADDR(OMAP3430ES2_USBHOST_MOD, PM_PWSTCTRL), 2214 .enable_bit = OMAP3430ES2_SAVEANDRESTORE_SHIFT, 2215 .flags = CLOCK_IN_OMAP3430ES2, 2216 .clkdm_name = "usbhost_clkdm", 2217 .recalc = &followparent_recalc, 2218 }; 2219 2220 /* WKUP */ 2221 2222 static const struct clksel_rate usim_96m_rates[] = { 2223 { .div = 2, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, 2224 { .div = 4, .val = 4, .flags = RATE_IN_343X }, 2225 { .div = 8, .val = 5, .flags = RATE_IN_343X }, 2226 { .div = 10, .val = 6, .flags = RATE_IN_343X }, 2227 { .div = 0 }, 2228 }; 2229 2230 static const struct clksel_rate usim_120m_rates[] = { 2231 { .div = 4, .val = 7, .flags = RATE_IN_343X | DEFAULT_RATE }, 2232 { .div = 8, .val = 8, .flags = RATE_IN_343X }, 2233 { .div = 16, .val = 9, .flags = RATE_IN_343X }, 2234 { .div = 20, .val = 10, .flags = RATE_IN_343X }, 2235 { .div = 0 }, 2236 }; 2237 2238 static const struct clksel usim_clksel[] = { 2239 { .parent = &omap_96m_fck, .rates = usim_96m_rates }, 2240 { .parent = &omap_120m_fck, .rates = usim_120m_rates }, 2241 { .parent = &sys_ck, .rates = div2_rates }, 2242 { .parent = NULL }, 2243 }; 2244 2245 /* 3430ES2 only */ 2246 static struct clk usim_fck = { 2247 .name = "usim_fck", 2248 .init = &omap2_init_clksel_parent, 2249 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), 2250 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, 2251 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), 2252 .clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK, 2253 .clksel = usim_clksel, 2254 .flags = CLOCK_IN_OMAP3430ES2, 2255 .recalc = &omap2_clksel_recalc, 2256 }; 2257 2258 /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */ 2259 static struct clk gpt1_fck = { 2260 .name = "gpt1_fck", 2261 .init = &omap2_init_clksel_parent, 2262 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), 2263 .enable_bit = OMAP3430_EN_GPT1_SHIFT, 2264 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), 2265 .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK, 2266 .clksel = omap343x_gpt_clksel, 2267 .flags = CLOCK_IN_OMAP343X, 2268 .clkdm_name = "wkup_clkdm", 2269 .recalc = &omap2_clksel_recalc, 2270 }; 2271 2272 static struct clk wkup_32k_fck = { 2273 .name = "wkup_32k_fck", 2274 .init = &omap2_init_clk_clkdm, 2275 .parent = &omap_32k_fck, 2276 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, 2277 .clkdm_name = "wkup_clkdm", 2278 .recalc = &followparent_recalc, 2279 }; 2280 2281 static struct clk gpio1_dbck = { 2282 .name = "gpio1_dbck", 2283 .parent = &wkup_32k_fck, 2284 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), 2285 .enable_bit = OMAP3430_EN_GPIO1_SHIFT, 2286 .flags = CLOCK_IN_OMAP343X, 2287 .clkdm_name = "wkup_clkdm", 2288 .recalc = &followparent_recalc, 2289 }; 2290 2291 static struct clk wdt2_fck = { 2292 .name = "wdt2_fck", 2293 .parent = &wkup_32k_fck, 2294 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), 2295 .enable_bit = OMAP3430_EN_WDT2_SHIFT, 2296 .flags = CLOCK_IN_OMAP343X, 2297 .clkdm_name = "wkup_clkdm", 2298 .recalc = &followparent_recalc, 2299 }; 2300 2301 static struct clk wkup_l4_ick = { 2302 .name = "wkup_l4_ick", 2303 .parent = &sys_ck, 2304 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, 2305 .clkdm_name = "wkup_clkdm", 2306 .recalc = &followparent_recalc, 2307 }; 2308 2309 /* 3430ES2 only */ 2310 /* Never specifically named in the TRM, so we have to infer a likely name */ 2311 static struct clk usim_ick = { 2312 .name = "usim_ick", 2313 .parent = &wkup_l4_ick, 2314 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2315 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, 2316 .flags = CLOCK_IN_OMAP3430ES2, 2317 .clkdm_name = "wkup_clkdm", 2318 .recalc = &followparent_recalc, 2319 }; 2320 2321 static struct clk wdt2_ick = { 2322 .name = "wdt2_ick", 2323 .parent = &wkup_l4_ick, 2324 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2325 .enable_bit = OMAP3430_EN_WDT2_SHIFT, 2326 .flags = CLOCK_IN_OMAP343X, 2327 .clkdm_name = "wkup_clkdm", 2328 .recalc = &followparent_recalc, 2329 }; 2330 2331 static struct clk wdt1_ick = { 2332 .name = "wdt1_ick", 2333 .parent = &wkup_l4_ick, 2334 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2335 .enable_bit = OMAP3430_EN_WDT1_SHIFT, 2336 .flags = CLOCK_IN_OMAP343X, 2337 .clkdm_name = "wkup_clkdm", 2338 .recalc = &followparent_recalc, 2339 }; 2340 2341 static struct clk gpio1_ick = { 2342 .name = "gpio1_ick", 2343 .parent = &wkup_l4_ick, 2344 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2345 .enable_bit = OMAP3430_EN_GPIO1_SHIFT, 2346 .flags = CLOCK_IN_OMAP343X, 2347 .clkdm_name = "wkup_clkdm", 2348 .recalc = &followparent_recalc, 2349 }; 2350 2351 static struct clk omap_32ksync_ick = { 2352 .name = "omap_32ksync_ick", 2353 .parent = &wkup_l4_ick, 2354 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2355 .enable_bit = OMAP3430_EN_32KSYNC_SHIFT, 2356 .flags = CLOCK_IN_OMAP343X, 2357 .clkdm_name = "wkup_clkdm", 2358 .recalc = &followparent_recalc, 2359 }; 2360 2361 /* XXX This clock no longer exists in 3430 TRM rev F */ 2362 static struct clk gpt12_ick = { 2363 .name = "gpt12_ick", 2364 .parent = &wkup_l4_ick, 2365 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2366 .enable_bit = OMAP3430_EN_GPT12_SHIFT, 2367 .flags = CLOCK_IN_OMAP343X, 2368 .clkdm_name = "wkup_clkdm", 2369 .recalc = &followparent_recalc, 2370 }; 2371 2372 static struct clk gpt1_ick = { 2373 .name = "gpt1_ick", 2374 .parent = &wkup_l4_ick, 2375 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2376 .enable_bit = OMAP3430_EN_GPT1_SHIFT, 2377 .flags = CLOCK_IN_OMAP343X, 2378 .clkdm_name = "wkup_clkdm", 2379 .recalc = &followparent_recalc, 2380 }; 2381 2382 2383 2384 /* PER clock domain */ 2385 2386 static struct clk per_96m_fck = { 2387 .name = "per_96m_fck", 2388 .parent = &omap_96m_alwon_fck, 2389 .init = &omap2_init_clk_clkdm, 2390 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 2391 PARENT_CONTROLS_CLOCK, 2392 .clkdm_name = "per_clkdm", 2393 .recalc = &followparent_recalc, 2394 }; 2395 2396 static struct clk per_48m_fck = { 2397 .name = "per_48m_fck", 2398 .parent = &omap_48m_fck, 2399 .init = &omap2_init_clk_clkdm, 2400 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 2401 PARENT_CONTROLS_CLOCK, 2402 .clkdm_name = "per_clkdm", 2403 .recalc = &followparent_recalc, 2404 }; 2405 2406 static struct clk uart3_fck = { 2407 .name = "uart3_fck", 2408 .parent = &per_48m_fck, 2409 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2410 .enable_bit = OMAP3430_EN_UART3_SHIFT, 2411 .flags = CLOCK_IN_OMAP343X, 2412 .clkdm_name = "per_clkdm", 2413 .recalc = &followparent_recalc, 2414 }; 2415 2416 static struct clk gpt2_fck = { 2417 .name = "gpt2_fck", 2418 .init = &omap2_init_clksel_parent, 2419 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2420 .enable_bit = OMAP3430_EN_GPT2_SHIFT, 2421 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), 2422 .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK, 2423 .clksel = omap343x_gpt_clksel, 2424 .flags = CLOCK_IN_OMAP343X, 2425 .clkdm_name = "per_clkdm", 2426 .recalc = &omap2_clksel_recalc, 2427 }; 2428 2429 static struct clk gpt3_fck = { 2430 .name = "gpt3_fck", 2431 .init = &omap2_init_clksel_parent, 2432 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2433 .enable_bit = OMAP3430_EN_GPT3_SHIFT, 2434 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), 2435 .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK, 2436 .clksel = omap343x_gpt_clksel, 2437 .flags = CLOCK_IN_OMAP343X, 2438 .clkdm_name = "per_clkdm", 2439 .recalc = &omap2_clksel_recalc, 2440 }; 2441 2442 static struct clk gpt4_fck = { 2443 .name = "gpt4_fck", 2444 .init = &omap2_init_clksel_parent, 2445 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2446 .enable_bit = OMAP3430_EN_GPT4_SHIFT, 2447 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), 2448 .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK, 2449 .clksel = omap343x_gpt_clksel, 2450 .flags = CLOCK_IN_OMAP343X, 2451 .clkdm_name = "per_clkdm", 2452 .recalc = &omap2_clksel_recalc, 2453 }; 2454 2455 static struct clk gpt5_fck = { 2456 .name = "gpt5_fck", 2457 .init = &omap2_init_clksel_parent, 2458 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2459 .enable_bit = OMAP3430_EN_GPT5_SHIFT, 2460 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), 2461 .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK, 2462 .clksel = omap343x_gpt_clksel, 2463 .flags = CLOCK_IN_OMAP343X, 2464 .clkdm_name = "per_clkdm", 2465 .recalc = &omap2_clksel_recalc, 2466 }; 2467 2468 static struct clk gpt6_fck = { 2469 .name = "gpt6_fck", 2470 .init = &omap2_init_clksel_parent, 2471 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2472 .enable_bit = OMAP3430_EN_GPT6_SHIFT, 2473 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), 2474 .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK, 2475 .clksel = omap343x_gpt_clksel, 2476 .flags = CLOCK_IN_OMAP343X, 2477 .clkdm_name = "per_clkdm", 2478 .recalc = &omap2_clksel_recalc, 2479 }; 2480 2481 static struct clk gpt7_fck = { 2482 .name = "gpt7_fck", 2483 .init = &omap2_init_clksel_parent, 2484 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2485 .enable_bit = OMAP3430_EN_GPT7_SHIFT, 2486 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), 2487 .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK, 2488 .clksel = omap343x_gpt_clksel, 2489 .flags = CLOCK_IN_OMAP343X, 2490 .clkdm_name = "per_clkdm", 2491 .recalc = &omap2_clksel_recalc, 2492 }; 2493 2494 static struct clk gpt8_fck = { 2495 .name = "gpt8_fck", 2496 .init = &omap2_init_clksel_parent, 2497 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2498 .enable_bit = OMAP3430_EN_GPT8_SHIFT, 2499 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), 2500 .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK, 2501 .clksel = omap343x_gpt_clksel, 2502 .flags = CLOCK_IN_OMAP343X, 2503 .clkdm_name = "per_clkdm", 2504 .recalc = &omap2_clksel_recalc, 2505 }; 2506 2507 static struct clk gpt9_fck = { 2508 .name = "gpt9_fck", 2509 .init = &omap2_init_clksel_parent, 2510 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2511 .enable_bit = OMAP3430_EN_GPT9_SHIFT, 2512 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), 2513 .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK, 2514 .clksel = omap343x_gpt_clksel, 2515 .flags = CLOCK_IN_OMAP343X, 2516 .clkdm_name = "per_clkdm", 2517 .recalc = &omap2_clksel_recalc, 2518 }; 2519 2520 static struct clk per_32k_alwon_fck = { 2521 .name = "per_32k_alwon_fck", 2522 .parent = &omap_32k_fck, 2523 .clkdm_name = "per_clkdm", 2524 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, 2525 .recalc = &followparent_recalc, 2526 }; 2527 2528 static struct clk gpio6_dbck = { 2529 .name = "gpio6_dbck", 2530 .parent = &per_32k_alwon_fck, 2531 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2532 .enable_bit = OMAP3430_EN_GPIO6_SHIFT, 2533 .flags = CLOCK_IN_OMAP343X, 2534 .clkdm_name = "per_clkdm", 2535 .recalc = &followparent_recalc, 2536 }; 2537 2538 static struct clk gpio5_dbck = { 2539 .name = "gpio5_dbck", 2540 .parent = &per_32k_alwon_fck, 2541 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2542 .enable_bit = OMAP3430_EN_GPIO5_SHIFT, 2543 .flags = CLOCK_IN_OMAP343X, 2544 .clkdm_name = "per_clkdm", 2545 .recalc = &followparent_recalc, 2546 }; 2547 2548 static struct clk gpio4_dbck = { 2549 .name = "gpio4_dbck", 2550 .parent = &per_32k_alwon_fck, 2551 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2552 .enable_bit = OMAP3430_EN_GPIO4_SHIFT, 2553 .flags = CLOCK_IN_OMAP343X, 2554 .clkdm_name = "per_clkdm", 2555 .recalc = &followparent_recalc, 2556 }; 2557 2558 static struct clk gpio3_dbck = { 2559 .name = "gpio3_dbck", 2560 .parent = &per_32k_alwon_fck, 2561 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2562 .enable_bit = OMAP3430_EN_GPIO3_SHIFT, 2563 .flags = CLOCK_IN_OMAP343X, 2564 .clkdm_name = "per_clkdm", 2565 .recalc = &followparent_recalc, 2566 }; 2567 2568 static struct clk gpio2_dbck = { 2569 .name = "gpio2_dbck", 2570 .parent = &per_32k_alwon_fck, 2571 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2572 .enable_bit = OMAP3430_EN_GPIO2_SHIFT, 2573 .flags = CLOCK_IN_OMAP343X, 2574 .clkdm_name = "per_clkdm", 2575 .recalc = &followparent_recalc, 2576 }; 2577 2578 static struct clk wdt3_fck = { 2579 .name = "wdt3_fck", 2580 .parent = &per_32k_alwon_fck, 2581 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2582 .enable_bit = OMAP3430_EN_WDT3_SHIFT, 2583 .flags = CLOCK_IN_OMAP343X, 2584 .clkdm_name = "per_clkdm", 2585 .recalc = &followparent_recalc, 2586 }; 2587 2588 static struct clk per_l4_ick = { 2589 .name = "per_l4_ick", 2590 .parent = &l4_ick, 2591 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 2592 PARENT_CONTROLS_CLOCK, 2593 .clkdm_name = "per_clkdm", 2594 .recalc = &followparent_recalc, 2595 }; 2596 2597 static struct clk gpio6_ick = { 2598 .name = "gpio6_ick", 2599 .parent = &per_l4_ick, 2600 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2601 .enable_bit = OMAP3430_EN_GPIO6_SHIFT, 2602 .flags = CLOCK_IN_OMAP343X, 2603 .clkdm_name = "per_clkdm", 2604 .recalc = &followparent_recalc, 2605 }; 2606 2607 static struct clk gpio5_ick = { 2608 .name = "gpio5_ick", 2609 .parent = &per_l4_ick, 2610 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2611 .enable_bit = OMAP3430_EN_GPIO5_SHIFT, 2612 .flags = CLOCK_IN_OMAP343X, 2613 .clkdm_name = "per_clkdm", 2614 .recalc = &followparent_recalc, 2615 }; 2616 2617 static struct clk gpio4_ick = { 2618 .name = "gpio4_ick", 2619 .parent = &per_l4_ick, 2620 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2621 .enable_bit = OMAP3430_EN_GPIO4_SHIFT, 2622 .flags = CLOCK_IN_OMAP343X, 2623 .clkdm_name = "per_clkdm", 2624 .recalc = &followparent_recalc, 2625 }; 2626 2627 static struct clk gpio3_ick = { 2628 .name = "gpio3_ick", 2629 .parent = &per_l4_ick, 2630 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2631 .enable_bit = OMAP3430_EN_GPIO3_SHIFT, 2632 .flags = CLOCK_IN_OMAP343X, 2633 .clkdm_name = "per_clkdm", 2634 .recalc = &followparent_recalc, 2635 }; 2636 2637 static struct clk gpio2_ick = { 2638 .name = "gpio2_ick", 2639 .parent = &per_l4_ick, 2640 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2641 .enable_bit = OMAP3430_EN_GPIO2_SHIFT, 2642 .flags = CLOCK_IN_OMAP343X, 2643 .clkdm_name = "per_clkdm", 2644 .recalc = &followparent_recalc, 2645 }; 2646 2647 static struct clk wdt3_ick = { 2648 .name = "wdt3_ick", 2649 .parent = &per_l4_ick, 2650 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2651 .enable_bit = OMAP3430_EN_WDT3_SHIFT, 2652 .flags = CLOCK_IN_OMAP343X, 2653 .clkdm_name = "per_clkdm", 2654 .recalc = &followparent_recalc, 2655 }; 2656 2657 static struct clk uart3_ick = { 2658 .name = "uart3_ick", 2659 .parent = &per_l4_ick, 2660 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2661 .enable_bit = OMAP3430_EN_UART3_SHIFT, 2662 .flags = CLOCK_IN_OMAP343X, 2663 .clkdm_name = "per_clkdm", 2664 .recalc = &followparent_recalc, 2665 }; 2666 2667 static struct clk gpt9_ick = { 2668 .name = "gpt9_ick", 2669 .parent = &per_l4_ick, 2670 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2671 .enable_bit = OMAP3430_EN_GPT9_SHIFT, 2672 .flags = CLOCK_IN_OMAP343X, 2673 .clkdm_name = "per_clkdm", 2674 .recalc = &followparent_recalc, 2675 }; 2676 2677 static struct clk gpt8_ick = { 2678 .name = "gpt8_ick", 2679 .parent = &per_l4_ick, 2680 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2681 .enable_bit = OMAP3430_EN_GPT8_SHIFT, 2682 .flags = CLOCK_IN_OMAP343X, 2683 .clkdm_name = "per_clkdm", 2684 .recalc = &followparent_recalc, 2685 }; 2686 2687 static struct clk gpt7_ick = { 2688 .name = "gpt7_ick", 2689 .parent = &per_l4_ick, 2690 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2691 .enable_bit = OMAP3430_EN_GPT7_SHIFT, 2692 .flags = CLOCK_IN_OMAP343X, 2693 .clkdm_name = "per_clkdm", 2694 .recalc = &followparent_recalc, 2695 }; 2696 2697 static struct clk gpt6_ick = { 2698 .name = "gpt6_ick", 2699 .parent = &per_l4_ick, 2700 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2701 .enable_bit = OMAP3430_EN_GPT6_SHIFT, 2702 .flags = CLOCK_IN_OMAP343X, 2703 .clkdm_name = "per_clkdm", 2704 .recalc = &followparent_recalc, 2705 }; 2706 2707 static struct clk gpt5_ick = { 2708 .name = "gpt5_ick", 2709 .parent = &per_l4_ick, 2710 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2711 .enable_bit = OMAP3430_EN_GPT5_SHIFT, 2712 .flags = CLOCK_IN_OMAP343X, 2713 .clkdm_name = "per_clkdm", 2714 .recalc = &followparent_recalc, 2715 }; 2716 2717 static struct clk gpt4_ick = { 2718 .name = "gpt4_ick", 2719 .parent = &per_l4_ick, 2720 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2721 .enable_bit = OMAP3430_EN_GPT4_SHIFT, 2722 .flags = CLOCK_IN_OMAP343X, 2723 .clkdm_name = "per_clkdm", 2724 .recalc = &followparent_recalc, 2725 }; 2726 2727 static struct clk gpt3_ick = { 2728 .name = "gpt3_ick", 2729 .parent = &per_l4_ick, 2730 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2731 .enable_bit = OMAP3430_EN_GPT3_SHIFT, 2732 .flags = CLOCK_IN_OMAP343X, 2733 .clkdm_name = "per_clkdm", 2734 .recalc = &followparent_recalc, 2735 }; 2736 2737 static struct clk gpt2_ick = { 2738 .name = "gpt2_ick", 2739 .parent = &per_l4_ick, 2740 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2741 .enable_bit = OMAP3430_EN_GPT2_SHIFT, 2742 .flags = CLOCK_IN_OMAP343X, 2743 .clkdm_name = "per_clkdm", 2744 .recalc = &followparent_recalc, 2745 }; 2746 2747 static struct clk mcbsp2_ick = { 2748 .name = "mcbsp_ick", 2749 .id = 2, 2750 .parent = &per_l4_ick, 2751 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2752 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, 2753 .flags = CLOCK_IN_OMAP343X, 2754 .clkdm_name = "per_clkdm", 2755 .recalc = &followparent_recalc, 2756 }; 2757 2758 static struct clk mcbsp3_ick = { 2759 .name = "mcbsp_ick", 2760 .id = 3, 2761 .parent = &per_l4_ick, 2762 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2763 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, 2764 .flags = CLOCK_IN_OMAP343X, 2765 .clkdm_name = "per_clkdm", 2766 .recalc = &followparent_recalc, 2767 }; 2768 2769 static struct clk mcbsp4_ick = { 2770 .name = "mcbsp_ick", 2771 .id = 4, 2772 .parent = &per_l4_ick, 2773 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2774 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, 2775 .flags = CLOCK_IN_OMAP343X, 2776 .clkdm_name = "per_clkdm", 2777 .recalc = &followparent_recalc, 2778 }; 2779 2780 static const struct clksel mcbsp_234_clksel[] = { 2781 { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates }, 2782 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, 2783 { .parent = NULL } 2784 }; 2785 2786 static struct clk mcbsp2_fck = { 2787 .name = "mcbsp_fck", 2788 .id = 2, 2789 .init = &omap2_init_clksel_parent, 2790 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2791 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, 2792 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), 2793 .clksel_mask = OMAP2_MCBSP2_CLKS_MASK, 2794 .clksel = mcbsp_234_clksel, 2795 .flags = CLOCK_IN_OMAP343X, 2796 .clkdm_name = "per_clkdm", 2797 .recalc = &omap2_clksel_recalc, 2798 }; 2799 2800 static struct clk mcbsp3_fck = { 2801 .name = "mcbsp_fck", 2802 .id = 3, 2803 .init = &omap2_init_clksel_parent, 2804 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2805 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, 2806 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), 2807 .clksel_mask = OMAP2_MCBSP3_CLKS_MASK, 2808 .clksel = mcbsp_234_clksel, 2809 .flags = CLOCK_IN_OMAP343X, 2810 .clkdm_name = "per_clkdm", 2811 .recalc = &omap2_clksel_recalc, 2812 }; 2813 2814 static struct clk mcbsp4_fck = { 2815 .name = "mcbsp_fck", 2816 .id = 4, 2817 .init = &omap2_init_clksel_parent, 2818 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2819 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, 2820 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), 2821 .clksel_mask = OMAP2_MCBSP4_CLKS_MASK, 2822 .clksel = mcbsp_234_clksel, 2823 .flags = CLOCK_IN_OMAP343X, 2824 .clkdm_name = "per_clkdm", 2825 .recalc = &omap2_clksel_recalc, 2826 }; 2827 2828 /* EMU clocks */ 2829 2830 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */ 2831 2832 static const struct clksel_rate emu_src_sys_rates[] = { 2833 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, 2834 { .div = 0 }, 2835 }; 2836 2837 static const struct clksel_rate emu_src_core_rates[] = { 2838 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, 2839 { .div = 0 }, 2840 }; 2841 2842 static const struct clksel_rate emu_src_per_rates[] = { 2843 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, 2844 { .div = 0 }, 2845 }; 2846 2847 static const struct clksel_rate emu_src_mpu_rates[] = { 2848 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, 2849 { .div = 0 }, 2850 }; 2851 2852 static const struct clksel emu_src_clksel[] = { 2853 { .parent = &sys_ck, .rates = emu_src_sys_rates }, 2854 { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates }, 2855 { .parent = &emu_per_alwon_ck, .rates = emu_src_per_rates }, 2856 { .parent = &emu_mpu_alwon_ck, .rates = emu_src_mpu_rates }, 2857 { .parent = NULL }, 2858 }; 2859 2860 /* 2861 * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only 2862 * to switch the source of some of the EMU clocks. 2863 * XXX Are there CLKEN bits for these EMU clks? 2864 */ 2865 static struct clk emu_src_ck = { 2866 .name = "emu_src_ck", 2867 .init = &omap2_init_clksel_parent, 2868 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), 2869 .clksel_mask = OMAP3430_MUX_CTRL_MASK, 2870 .clksel = emu_src_clksel, 2871 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, 2872 .clkdm_name = "emu_clkdm", 2873 .recalc = &omap2_clksel_recalc, 2874 }; 2875 2876 static const struct clksel_rate pclk_emu_rates[] = { 2877 { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, 2878 { .div = 3, .val = 3, .flags = RATE_IN_343X }, 2879 { .div = 4, .val = 4, .flags = RATE_IN_343X }, 2880 { .div = 6, .val = 6, .flags = RATE_IN_343X }, 2881 { .div = 0 }, 2882 }; 2883 2884 static const struct clksel pclk_emu_clksel[] = { 2885 { .parent = &emu_src_ck, .rates = pclk_emu_rates }, 2886 { .parent = NULL }, 2887 }; 2888 2889 static struct clk pclk_fck = { 2890 .name = "pclk_fck", 2891 .init = &omap2_init_clksel_parent, 2892 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), 2893 .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK, 2894 .clksel = pclk_emu_clksel, 2895 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, 2896 .clkdm_name = "emu_clkdm", 2897 .recalc = &omap2_clksel_recalc, 2898 }; 2899 2900 static const struct clksel_rate pclkx2_emu_rates[] = { 2901 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, 2902 { .div = 2, .val = 2, .flags = RATE_IN_343X }, 2903 { .div = 3, .val = 3, .flags = RATE_IN_343X }, 2904 { .div = 0 }, 2905 }; 2906 2907 static const struct clksel pclkx2_emu_clksel[] = { 2908 { .parent = &emu_src_ck, .rates = pclkx2_emu_rates }, 2909 { .parent = NULL }, 2910 }; 2911 2912 static struct clk pclkx2_fck = { 2913 .name = "pclkx2_fck", 2914 .init = &omap2_init_clksel_parent, 2915 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), 2916 .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK, 2917 .clksel = pclkx2_emu_clksel, 2918 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, 2919 .clkdm_name = "emu_clkdm", 2920 .recalc = &omap2_clksel_recalc, 2921 }; 2922 2923 static const struct clksel atclk_emu_clksel[] = { 2924 { .parent = &emu_src_ck, .rates = div2_rates }, 2925 { .parent = NULL }, 2926 }; 2927 2928 static struct clk atclk_fck = { 2929 .name = "atclk_fck", 2930 .init = &omap2_init_clksel_parent, 2931 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), 2932 .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK, 2933 .clksel = atclk_emu_clksel, 2934 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, 2935 .clkdm_name = "emu_clkdm", 2936 .recalc = &omap2_clksel_recalc, 2937 }; 2938 2939 static struct clk traceclk_src_fck = { 2940 .name = "traceclk_src_fck", 2941 .init = &omap2_init_clksel_parent, 2942 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), 2943 .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK, 2944 .clksel = emu_src_clksel, 2945 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, 2946 .clkdm_name = "emu_clkdm", 2947 .recalc = &omap2_clksel_recalc, 2948 }; 2949 2950 static const struct clksel_rate traceclk_rates[] = { 2951 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, 2952 { .div = 2, .val = 2, .flags = RATE_IN_343X }, 2953 { .div = 4, .val = 4, .flags = RATE_IN_343X }, 2954 { .div = 0 }, 2955 }; 2956 2957 static const struct clksel traceclk_clksel[] = { 2958 { .parent = &traceclk_src_fck, .rates = traceclk_rates }, 2959 { .parent = NULL }, 2960 }; 2961 2962 static struct clk traceclk_fck = { 2963 .name = "traceclk_fck", 2964 .init = &omap2_init_clksel_parent, 2965 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), 2966 .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK, 2967 .clksel = traceclk_clksel, 2968 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED, 2969 .clkdm_name = "emu_clkdm", 2970 .recalc = &omap2_clksel_recalc, 2971 }; 2972 2973 /* SR clocks */ 2974 2975 /* SmartReflex fclk (VDD1) */ 2976 static struct clk sr1_fck = { 2977 .name = "sr1_fck", 2978 .parent = &sys_ck, 2979 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), 2980 .enable_bit = OMAP3430_EN_SR1_SHIFT, 2981 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 2982 .recalc = &followparent_recalc, 2983 }; 2984 2985 /* SmartReflex fclk (VDD2) */ 2986 static struct clk sr2_fck = { 2987 .name = "sr2_fck", 2988 .parent = &sys_ck, 2989 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), 2990 .enable_bit = OMAP3430_EN_SR2_SHIFT, 2991 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 2992 .recalc = &followparent_recalc, 2993 }; 2994 2995 static struct clk sr_l4_ick = { 2996 .name = "sr_l4_ick", 2997 .parent = &l4_ick, 2998 .flags = CLOCK_IN_OMAP343X, 2999 .clkdm_name = "core_l4_clkdm", 3000 .recalc = &followparent_recalc, 3001 }; 3002 3003 /* SECURE_32K_FCK clocks */ 3004 3005 /* XXX This clock no longer exists in 3430 TRM rev F */ 3006 static struct clk gpt12_fck = { 3007 .name = "gpt12_fck", 3008 .parent = &secure_32k_fck, 3009 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED, 3010 .recalc = &followparent_recalc, 3011 }; 3012 3013 static struct clk wdt1_fck = { 3014 .name = "wdt1_fck", 3015 .parent = &secure_32k_fck, 3016 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED, 3017 .recalc = &followparent_recalc, 3018 }; 3019 3020 static struct clk *onchip_34xx_clks[] __initdata = { 3021 &omap_32k_fck, 3022 &virt_12m_ck, 3023 &virt_13m_ck, 3024 &virt_16_8m_ck, 3025 &virt_19_2m_ck, 3026 &virt_26m_ck, 3027 &virt_38_4m_ck, 3028 &osc_sys_ck, 3029 &sys_ck, 3030 &sys_altclk, 3031 &mcbsp_clks, 3032 &sys_clkout1, 3033 &dpll1_ck, 3034 &dpll1_x2_ck, 3035 &dpll1_x2m2_ck, 3036 &dpll2_ck, 3037 &dpll2_m2_ck, 3038 &dpll3_ck, 3039 &core_ck, 3040 &dpll3_x2_ck, 3041 &dpll3_m2_ck, 3042 &dpll3_m2x2_ck, 3043 &dpll3_m3_ck, 3044 &dpll3_m3x2_ck, 3045 &emu_core_alwon_ck, 3046 &dpll4_ck, 3047 &dpll4_x2_ck, 3048 &omap_96m_alwon_fck, 3049 &omap_96m_fck, 3050 &cm_96m_fck, 3051 &virt_omap_54m_fck, 3052 &omap_54m_fck, 3053 &omap_48m_fck, 3054 &omap_12m_fck, 3055 &dpll4_m2_ck, 3056 &dpll4_m2x2_ck, 3057 &dpll4_m3_ck, 3058 &dpll4_m3x2_ck, 3059 &dpll4_m4_ck, 3060 &dpll4_m4x2_ck, 3061 &dpll4_m5_ck, 3062 &dpll4_m5x2_ck, 3063 &dpll4_m6_ck, 3064 &dpll4_m6x2_ck, 3065 &emu_per_alwon_ck, 3066 &dpll5_ck, 3067 &dpll5_m2_ck, 3068 &omap_120m_fck, 3069 &clkout2_src_ck, 3070 &sys_clkout2, 3071 &corex2_fck, 3072 &dpll1_fck, 3073 &mpu_ck, 3074 &arm_fck, 3075 &emu_mpu_alwon_ck, 3076 &dpll2_fck, 3077 &iva2_ck, 3078 &l3_ick, 3079 &l4_ick, 3080 &rm_ick, 3081 &gfx_l3_ck, 3082 &gfx_l3_fck, 3083 &gfx_l3_ick, 3084 &gfx_cg1_ck, 3085 &gfx_cg2_ck, 3086 &sgx_fck, 3087 &sgx_ick, 3088 &d2d_26m_fck, 3089 &gpt10_fck, 3090 &gpt11_fck, 3091 &cpefuse_fck, 3092 &ts_fck, 3093 &usbtll_fck, 3094 &core_96m_fck, 3095 &mmchs3_fck, 3096 &mmchs2_fck, 3097 &mspro_fck, 3098 &mmchs1_fck, 3099 &i2c3_fck, 3100 &i2c2_fck, 3101 &i2c1_fck, 3102 &mcbsp5_fck, 3103 &mcbsp1_fck, 3104 &core_48m_fck, 3105 &mcspi4_fck, 3106 &mcspi3_fck, 3107 &mcspi2_fck, 3108 &mcspi1_fck, 3109 &uart2_fck, 3110 &uart1_fck, 3111 &fshostusb_fck, 3112 &core_12m_fck, 3113 &hdq_fck, 3114 &ssi_ssr_fck, 3115 &ssi_sst_fck, 3116 &core_l3_ick, 3117 &hsotgusb_ick, 3118 &sdrc_ick, 3119 &gpmc_fck, 3120 &security_l3_ick, 3121 &pka_ick, 3122 &core_l4_ick, 3123 &usbtll_ick, 3124 &mmchs3_ick, 3125 &icr_ick, 3126 &aes2_ick, 3127 &sha12_ick, 3128 &des2_ick, 3129 &mmchs2_ick, 3130 &mmchs1_ick, 3131 &mspro_ick, 3132 &hdq_ick, 3133 &mcspi4_ick, 3134 &mcspi3_ick, 3135 &mcspi2_ick, 3136 &mcspi1_ick, 3137 &i2c3_ick, 3138 &i2c2_ick, 3139 &i2c1_ick, 3140 &uart2_ick, 3141 &uart1_ick, 3142 &gpt11_ick, 3143 &gpt10_ick, 3144 &mcbsp5_ick, 3145 &mcbsp1_ick, 3146 &fac_ick, 3147 &mailboxes_ick, 3148 &omapctrl_ick, 3149 &ssi_l4_ick, 3150 &ssi_ick, 3151 &usb_l4_ick, 3152 &security_l4_ick2, 3153 &aes1_ick, 3154 &rng_ick, 3155 &sha11_ick, 3156 &des1_ick, 3157 &dss1_alwon_fck, 3158 &dss_tv_fck, 3159 &dss_96m_fck, 3160 &dss2_alwon_fck, 3161 &dss_ick, 3162 &cam_mclk, 3163 &cam_ick, 3164 &usbhost_120m_fck, 3165 &usbhost_48m_fck, 3166 &usbhost_ick, 3167 &usbhost_sar_fck, 3168 &usim_fck, 3169 &gpt1_fck, 3170 &wkup_32k_fck, 3171 &gpio1_dbck, 3172 &wdt2_fck, 3173 &wkup_l4_ick, 3174 &usim_ick, 3175 &wdt2_ick, 3176 &wdt1_ick, 3177 &gpio1_ick, 3178 &omap_32ksync_ick, 3179 &gpt12_ick, 3180 &gpt1_ick, 3181 &per_96m_fck, 3182 &per_48m_fck, 3183 &uart3_fck, 3184 &gpt2_fck, 3185 &gpt3_fck, 3186 &gpt4_fck, 3187 &gpt5_fck, 3188 &gpt6_fck, 3189 &gpt7_fck, 3190 &gpt8_fck, 3191 &gpt9_fck, 3192 &per_32k_alwon_fck, 3193 &gpio6_dbck, 3194 &gpio5_dbck, 3195 &gpio4_dbck, 3196 &gpio3_dbck, 3197 &gpio2_dbck, 3198 &wdt3_fck, 3199 &per_l4_ick, 3200 &gpio6_ick, 3201 &gpio5_ick, 3202 &gpio4_ick, 3203 &gpio3_ick, 3204 &gpio2_ick, 3205 &wdt3_ick, 3206 &uart3_ick, 3207 &gpt9_ick, 3208 &gpt8_ick, 3209 &gpt7_ick, 3210 &gpt6_ick, 3211 &gpt5_ick, 3212 &gpt4_ick, 3213 &gpt3_ick, 3214 &gpt2_ick, 3215 &mcbsp2_ick, 3216 &mcbsp3_ick, 3217 &mcbsp4_ick, 3218 &mcbsp2_fck, 3219 &mcbsp3_fck, 3220 &mcbsp4_fck, 3221 &emu_src_ck, 3222 &pclk_fck, 3223 &pclkx2_fck, 3224 &atclk_fck, 3225 &traceclk_src_fck, 3226 &traceclk_fck, 3227 &sr1_fck, 3228 &sr2_fck, 3229 &sr_l4_ick, 3230 &secure_32k_fck, 3231 &gpt12_fck, 3232 &wdt1_fck, 3233 }; 3234 3235 #endif 3236