1 /* linux/arch/arm/mach-s3c2412/s3c2412.c
2 *
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * http://armlinux.simtec.co.uk/.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #include <linux/kernel.h>
14 #include <linux/types.h>
15 #include <linux/interrupt.h>
16 #include <linux/list.h>
17 #include <linux/timer.h>
18 #include <linux/init.h>
19 #include <linux/clk.h>
20 #include <linux/delay.h>
21 #include <linux/sysdev.h>
22 #include <linux/serial_core.h>
23 #include <linux/platform_device.h>
24 #include <linux/io.h>
25
26 #include <asm/mach/arch.h>
27 #include <asm/mach/map.h>
28 #include <asm/mach/irq.h>
29
30 #include <mach/hardware.h>
31 #include <asm/proc-fns.h>
32 #include <asm/irq.h>
33
34 #include <mach/reset.h>
35 #include <mach/idle.h>
36
37 #include <plat/cpu-freq.h>
38
39 #include <mach/regs-clock.h>
40 #include <plat/regs-serial.h>
41 #include <mach/regs-power.h>
42 #include <mach/regs-gpio.h>
43 #include <mach/regs-gpioj.h>
44 #include <mach/regs-dsc.h>
45 #include <plat/regs-spi.h>
46 #include <mach/regs-s3c2412.h>
47
48 #include <plat/s3c2412.h>
49 #include <plat/cpu.h>
50 #include <plat/devs.h>
51 #include <plat/clock.h>
52 #include <plat/pm.h>
53 #include <plat/pll.h>
54
55 #ifndef CONFIG_CPU_S3C2412_ONLY
56 void __iomem *s3c24xx_va_gpio2 = S3C24XX_VA_GPIO;
57
s3c2412_init_gpio2(void)58 static inline void s3c2412_init_gpio2(void)
59 {
60 s3c24xx_va_gpio2 = S3C24XX_VA_GPIO + 0x10;
61 }
62 #else
63 #define s3c2412_init_gpio2() do { } while(0)
64 #endif
65
66 /* Initial IO mappings */
67
68 static struct map_desc s3c2412_iodesc[] __initdata = {
69 IODESC_ENT(CLKPWR),
70 IODESC_ENT(TIMER),
71 IODESC_ENT(WATCHDOG),
72 };
73
74 /* uart registration process */
75
s3c2412_init_uarts(struct s3c2410_uartcfg * cfg,int no)76 void __init s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no)
77 {
78 s3c24xx_init_uartdevs("s3c2412-uart", s3c2410_uart_resources, cfg, no);
79
80 /* rename devices that are s3c2412/s3c2413 specific */
81 s3c_device_sdi.name = "s3c2412-sdi";
82 s3c_device_lcd.name = "s3c2412-lcd";
83 s3c_device_nand.name = "s3c2412-nand";
84
85 /* alter IRQ of SDI controller */
86
87 s3c_device_sdi.resource[1].start = IRQ_S3C2412_SDI;
88 s3c_device_sdi.resource[1].end = IRQ_S3C2412_SDI;
89
90 /* spi channel related changes, s3c2412/13 specific */
91 s3c_device_spi0.name = "s3c2412-spi";
92 s3c_device_spi0.resource[0].end = S3C24XX_PA_SPI + 0x24;
93 s3c_device_spi1.name = "s3c2412-spi";
94 s3c_device_spi1.resource[0].start = S3C24XX_PA_SPI + S3C2412_SPI1;
95 s3c_device_spi1.resource[0].end = S3C24XX_PA_SPI + S3C2412_SPI1 + 0x24;
96
97 }
98
99 /* s3c2412_idle
100 *
101 * use the standard idle call by ensuring the idle mode
102 * in power config, then issuing the idle co-processor
103 * instruction
104 */
105
s3c2412_idle(void)106 static void s3c2412_idle(void)
107 {
108 unsigned long tmp;
109
110 /* ensure our idle mode is to go to idle */
111
112 tmp = __raw_readl(S3C2412_PWRCFG);
113 tmp &= ~S3C2412_PWRCFG_STANDBYWFI_MASK;
114 tmp |= S3C2412_PWRCFG_STANDBYWFI_IDLE;
115 __raw_writel(tmp, S3C2412_PWRCFG);
116
117 cpu_do_idle();
118 }
119
s3c2412_hard_reset(void)120 static void s3c2412_hard_reset(void)
121 {
122 /* errata "Watch-dog/Software Reset Problem" specifies that
123 * this reset must be done with the SYSCLK sourced from
124 * EXTCLK instead of FOUT to avoid a glitch in the reset
125 * mechanism.
126 *
127 * See the watchdog section of the S3C2412 manual for more
128 * information on this fix.
129 */
130
131 __raw_writel(0x00, S3C2412_CLKSRC);
132 __raw_writel(S3C2412_SWRST_RESET, S3C2412_SWRST);
133
134 mdelay(1);
135 }
136
137 /* s3c2412_map_io
138 *
139 * register the standard cpu IO areas, and any passed in from the
140 * machine specific initialisation.
141 */
142
s3c2412_map_io(void)143 void __init s3c2412_map_io(void)
144 {
145 /* move base of IO */
146
147 s3c2412_init_gpio2();
148
149 /* set our idle function */
150
151 s3c24xx_idle = s3c2412_idle;
152
153 /* set custom reset hook */
154
155 s3c24xx_reset_hook = s3c2412_hard_reset;
156
157 /* register our io-tables */
158
159 iotable_init(s3c2412_iodesc, ARRAY_SIZE(s3c2412_iodesc));
160 }
161
s3c2412_setup_clocks(void)162 void __init_or_cpufreq s3c2412_setup_clocks(void)
163 {
164 struct clk *xtal_clk;
165 unsigned long tmp;
166 unsigned long xtal;
167 unsigned long fclk;
168 unsigned long hclk;
169 unsigned long pclk;
170
171 xtal_clk = clk_get(NULL, "xtal");
172 xtal = clk_get_rate(xtal_clk);
173 clk_put(xtal_clk);
174
175 /* now we've got our machine bits initialised, work out what
176 * clocks we've got */
177
178 fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal * 2);
179
180 clk_mpll.rate = fclk;
181
182 tmp = __raw_readl(S3C2410_CLKDIVN);
183
184 /* work out clock scalings */
185
186 hclk = fclk / ((tmp & S3C2412_CLKDIVN_HDIVN_MASK) + 1);
187 hclk /= ((tmp & S3C2412_CLKDIVN_ARMDIVN) ? 2 : 1);
188 pclk = hclk / ((tmp & S3C2412_CLKDIVN_PDIVN) ? 2 : 1);
189
190 /* print brieft summary of clocks, etc */
191
192 printk("S3C2412: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
193 print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));
194
195 s3c24xx_setup_clocks(fclk, hclk, pclk);
196 }
197
s3c2412_init_clocks(int xtal)198 void __init s3c2412_init_clocks(int xtal)
199 {
200 /* initialise the clocks here, to allow other things like the
201 * console to use them
202 */
203
204 s3c24xx_register_baseclocks(xtal);
205 s3c2412_setup_clocks();
206 s3c2412_baseclk_add();
207 }
208
209 /* need to register class before we actually register the device, and
210 * we also need to ensure that it has been initialised before any of the
211 * drivers even try to use it (even if not on an s3c2412 based system)
212 * as a driver which may support both 2410 and 2440 may try and use it.
213 */
214
215 struct sysdev_class s3c2412_sysclass = {
216 .name = "s3c2412-core",
217 };
218
s3c2412_core_init(void)219 static int __init s3c2412_core_init(void)
220 {
221 return sysdev_class_register(&s3c2412_sysclass);
222 }
223
224 core_initcall(s3c2412_core_init);
225
226 static struct sys_device s3c2412_sysdev = {
227 .cls = &s3c2412_sysclass,
228 };
229
s3c2412_init(void)230 int __init s3c2412_init(void)
231 {
232 printk("S3C2412: Initialising architecture\n");
233
234 return sysdev_register(&s3c2412_sysdev);
235 }
236