1 /* 2 * Copyright (C) 1997,1998 Russell King 3 * Copyright (C) 1999 ARM Limited 4 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. 5 * Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #ifndef __ASM_ARCH_MXC_MX1_H__ 13 #define __ASM_ARCH_MXC_MX1_H__ 14 15 #ifndef __ASM_ARCH_MXC_HARDWARE_H__ 16 #error "Do not include directly." 17 #endif 18 19 #include <mach/vmalloc.h> 20 21 /* 22 * Memory map 23 */ 24 #define IMX_IO_PHYS 0x00200000 25 #define IMX_IO_SIZE 0x00100000 26 #define IMX_IO_BASE VMALLOC_END 27 28 #define IMX_CS0_PHYS 0x10000000 29 #define IMX_CS0_SIZE 0x02000000 30 31 #define IMX_CS1_PHYS 0x12000000 32 #define IMX_CS1_SIZE 0x01000000 33 34 #define IMX_CS2_PHYS 0x13000000 35 #define IMX_CS2_SIZE 0x01000000 36 37 #define IMX_CS3_PHYS 0x14000000 38 #define IMX_CS3_SIZE 0x01000000 39 40 #define IMX_CS4_PHYS 0x15000000 41 #define IMX_CS4_SIZE 0x01000000 42 43 #define IMX_CS5_PHYS 0x16000000 44 #define IMX_CS5_SIZE 0x01000000 45 46 /* 47 * Register BASEs, based on OFFSETs 48 */ 49 #define AIPI1_BASE_ADDR (0x00000 + IMX_IO_PHYS) 50 #define WDT_BASE_ADDR (0x01000 + IMX_IO_PHYS) 51 #define TIM1_BASE_ADDR (0x02000 + IMX_IO_PHYS) 52 #define TIM2_BASE_ADDR (0x03000 + IMX_IO_PHYS) 53 #define RTC_BASE_ADDR (0x04000 + IMX_IO_PHYS) 54 #define LCDC_BASE_ADDR (0x05000 + IMX_IO_PHYS) 55 #define UART1_BASE_ADDR (0x06000 + IMX_IO_PHYS) 56 #define UART2_BASE_ADDR (0x07000 + IMX_IO_PHYS) 57 #define PWM_BASE_ADDR (0x08000 + IMX_IO_PHYS) 58 #define DMA_BASE_ADDR (0x09000 + IMX_IO_PHYS) 59 #define AIPI2_BASE_ADDR (0x10000 + IMX_IO_PHYS) 60 #define SIM_BASE_ADDR (0x11000 + IMX_IO_PHYS) 61 #define USBD_BASE_ADDR (0x12000 + IMX_IO_PHYS) 62 #define SPI1_BASE_ADDR (0x13000 + IMX_IO_PHYS) 63 #define MMC_BASE_ADDR (0x14000 + IMX_IO_PHYS) 64 #define ASP_BASE_ADDR (0x15000 + IMX_IO_PHYS) 65 #define BTA_BASE_ADDR (0x16000 + IMX_IO_PHYS) 66 #define I2C_BASE_ADDR (0x17000 + IMX_IO_PHYS) 67 #define SSI_BASE_ADDR (0x18000 + IMX_IO_PHYS) 68 #define SPI2_BASE_ADDR (0x19000 + IMX_IO_PHYS) 69 #define MSHC_BASE_ADDR (0x1A000 + IMX_IO_PHYS) 70 #define CCM_BASE_ADDR (0x1B000 + IMX_IO_PHYS) 71 #define SCM_BASE_ADDR (0x1B804 + IMX_IO_PHYS) 72 #define GPIO_BASE_ADDR (0x1C000 + IMX_IO_PHYS) 73 #define EIM_BASE_ADDR (0x20000 + IMX_IO_PHYS) 74 #define SDRAMC_BASE_ADDR (0x21000 + IMX_IO_PHYS) 75 #define MMA_BASE_ADDR (0x22000 + IMX_IO_PHYS) 76 #define AVIC_BASE_ADDR (0x23000 + IMX_IO_PHYS) 77 #define CSI_BASE_ADDR (0x24000 + IMX_IO_PHYS) 78 79 /* macro to get at IO space when running virtually */ 80 #define IO_ADDRESS(x) ((x) - IMX_IO_PHYS + IMX_IO_BASE) 81 82 /* define macros needed for entry-macro.S */ 83 #define AVIC_IO_ADDRESS(x) IO_ADDRESS(x) 84 85 /* fixed interrput numbers */ 86 #define INT_SOFTINT 0 87 #define CSI_INT 6 88 #define DSPA_MAC_INT 7 89 #define DSPA_INT 8 90 #define COMP_INT 9 91 #define MSHC_XINT 10 92 #define GPIO_INT_PORTA 11 93 #define GPIO_INT_PORTB 12 94 #define GPIO_INT_PORTC 13 95 #define LCDC_INT 14 96 #define SIM_INT 15 97 #define SIM_DATA_INT 16 98 #define RTC_INT 17 99 #define RTC_SAMINT 18 100 #define UART2_MINT_PFERR 19 101 #define UART2_MINT_RTS 20 102 #define UART2_MINT_DTR 21 103 #define UART2_MINT_UARTC 22 104 #define UART2_MINT_TX 23 105 #define UART2_MINT_RX 24 106 #define UART1_MINT_PFERR 25 107 #define UART1_MINT_RTS 26 108 #define UART1_MINT_DTR 27 109 #define UART1_MINT_UARTC 28 110 #define UART1_MINT_TX 29 111 #define UART1_MINT_RX 30 112 #define VOICE_DAC_INT 31 113 #define VOICE_ADC_INT 32 114 #define PEN_DATA_INT 33 115 #define PWM_INT 34 116 #define SDHC_INT 35 117 #define I2C_INT 39 118 #define CSPI_INT 41 119 #define SSI_TX_INT 42 120 #define SSI_TX_ERR_INT 43 121 #define SSI_RX_INT 44 122 #define SSI_RX_ERR_INT 45 123 #define TOUCH_INT 46 124 #define USBD_INT0 47 125 #define USBD_INT1 48 126 #define USBD_INT2 49 127 #define USBD_INT3 50 128 #define USBD_INT4 51 129 #define USBD_INT5 52 130 #define USBD_INT6 53 131 #define BTSYS_INT 55 132 #define BTTIM_INT 56 133 #define BTWUI_INT 57 134 #define TIM2_INT 58 135 #define TIM1_INT 59 136 #define DMA_ERR 60 137 #define DMA_INT 61 138 #define GPIO_INT_PORTD 62 139 #define WDT_INT 63 140 141 /* gpio and gpio based interrupt handling */ 142 #define GPIO_DR 0x1C 143 #define GPIO_GDIR 0x00 144 #define GPIO_PSR 0x24 145 #define GPIO_ICR1 0x28 146 #define GPIO_ICR2 0x2C 147 #define GPIO_IMR 0x30 148 #define GPIO_ISR 0x34 149 #define GPIO_INT_LOW_LEV 0x3 150 #define GPIO_INT_HIGH_LEV 0x2 151 #define GPIO_INT_RISE_EDGE 0x0 152 #define GPIO_INT_FALL_EDGE 0x1 153 #define GPIO_INT_NONE 0x4 154 155 /* DMA */ 156 #define DMA_REQ_UART3_T 2 157 #define DMA_REQ_UART3_R 3 158 #define DMA_REQ_SSI2_T 4 159 #define DMA_REQ_SSI2_R 5 160 #define DMA_REQ_CSI_STAT 6 161 #define DMA_REQ_CSI_R 7 162 #define DMA_REQ_MSHC 8 163 #define DMA_REQ_DSPA_DCT_DOUT 9 164 #define DMA_REQ_DSPA_DCT_DIN 10 165 #define DMA_REQ_DSPA_MAC 11 166 #define DMA_REQ_EXT 12 167 #define DMA_REQ_SDHC 13 168 #define DMA_REQ_SPI1_R 14 169 #define DMA_REQ_SPI1_T 15 170 #define DMA_REQ_SSI_T 16 171 #define DMA_REQ_SSI_R 17 172 #define DMA_REQ_ASP_DAC 18 173 #define DMA_REQ_ASP_ADC 19 174 #define DMA_REQ_USP_EP(x) (20 + (x)) 175 #define DMA_REQ_SPI2_R 26 176 #define DMA_REQ_SPI2_T 27 177 #define DMA_REQ_UART2_T 28 178 #define DMA_REQ_UART2_R 29 179 #define DMA_REQ_UART1_T 30 180 #define DMA_REQ_UART1_R 31 181 182 /* mandatory for CONFIG_LL_DEBUG */ 183 #define MXC_LL_UART_PADDR UART1_BASE_ADDR 184 #define MXC_LL_UART_VADDR IO_ADDRESS(UART1_BASE_ADDR) 185 186 #endif /* __ASM_ARCH_MXC_MX1_H__ */ 187