1 /*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20 #include <linux/module.h>
21 #include <linux/irq.h>
22 #include <linux/io.h>
23 #include <mach/common.h>
24 #include <asm/mach/irq.h>
25 #include <mach/hardware.h>
26
27 #define AVIC_BASE IO_ADDRESS(AVIC_BASE_ADDR)
28 #define AVIC_INTCNTL (AVIC_BASE + 0x00) /* int control reg */
29 #define AVIC_NIMASK (AVIC_BASE + 0x04) /* int mask reg */
30 #define AVIC_INTENNUM (AVIC_BASE + 0x08) /* int enable number reg */
31 #define AVIC_INTDISNUM (AVIC_BASE + 0x0C) /* int disable number reg */
32 #define AVIC_INTENABLEH (AVIC_BASE + 0x10) /* int enable reg high */
33 #define AVIC_INTENABLEL (AVIC_BASE + 0x14) /* int enable reg low */
34 #define AVIC_INTTYPEH (AVIC_BASE + 0x18) /* int type reg high */
35 #define AVIC_INTTYPEL (AVIC_BASE + 0x1C) /* int type reg low */
36 #define AVIC_NIPRIORITY(x) (AVIC_BASE + (0x20 + 4 * (7 - (x)))) /* int priority */
37 #define AVIC_NIVECSR (AVIC_BASE + 0x40) /* norm int vector/status */
38 #define AVIC_FIVECSR (AVIC_BASE + 0x44) /* fast int vector/status */
39 #define AVIC_INTSRCH (AVIC_BASE + 0x48) /* int source reg high */
40 #define AVIC_INTSRCL (AVIC_BASE + 0x4C) /* int source reg low */
41 #define AVIC_INTFRCH (AVIC_BASE + 0x50) /* int force reg high */
42 #define AVIC_INTFRCL (AVIC_BASE + 0x54) /* int force reg low */
43 #define AVIC_NIPNDH (AVIC_BASE + 0x58) /* norm int pending high */
44 #define AVIC_NIPNDL (AVIC_BASE + 0x5C) /* norm int pending low */
45 #define AVIC_FIPNDH (AVIC_BASE + 0x60) /* fast int pending high */
46 #define AVIC_FIPNDL (AVIC_BASE + 0x64) /* fast int pending low */
47
48 #define SYSTEM_PREV_REG IO_ADDRESS(IIM_BASE_ADDR + 0x20)
49 #define SYSTEM_SREV_REG IO_ADDRESS(IIM_BASE_ADDR + 0x24)
50 #define IIM_PROD_REV_SH 3
51 #define IIM_PROD_REV_LEN 5
52
53 #ifdef CONFIG_MXC_IRQ_PRIOR
imx_irq_set_priority(unsigned char irq,unsigned char prio)54 void imx_irq_set_priority(unsigned char irq, unsigned char prio)
55 {
56 unsigned int temp;
57 unsigned int mask = 0x0F << irq % 8 * 4;
58
59 if (irq > 63)
60 return;
61
62 temp = __raw_readl(AVIC_NIPRIORITY(irq / 8));
63 temp &= ~mask;
64 temp |= prio & mask;
65
66 __raw_writel(temp, AVIC_NIPRIORITY(irq / 8));
67 }
68 EXPORT_SYMBOL(imx_irq_set_priority);
69 #endif
70
71 #ifdef CONFIG_FIQ
mxc_set_irq_fiq(unsigned int irq,unsigned int type)72 int mxc_set_irq_fiq(unsigned int irq, unsigned int type)
73 {
74 unsigned int irqt;
75
76 if (irq >= MXC_INTERNAL_IRQS)
77 return -EINVAL;
78
79 if (irq < MXC_INTERNAL_IRQS / 2) {
80 irqt = __raw_readl(AVIC_INTTYPEL) & ~(1 << irq);
81 __raw_writel(irqt | (!!type << irq), AVIC_INTTYPEL);
82 } else {
83 irq -= MXC_INTERNAL_IRQS / 2;
84 irqt = __raw_readl(AVIC_INTTYPEH) & ~(1 << irq);
85 __raw_writel(irqt | (!!type << irq), AVIC_INTTYPEH);
86 }
87
88 return 0;
89 }
90 EXPORT_SYMBOL(mxc_set_irq_fiq);
91 #endif /* CONFIG_FIQ */
92
93 /* Disable interrupt number "irq" in the AVIC */
mxc_mask_irq(unsigned int irq)94 static void mxc_mask_irq(unsigned int irq)
95 {
96 __raw_writel(irq, AVIC_INTDISNUM);
97 }
98
99 /* Enable interrupt number "irq" in the AVIC */
mxc_unmask_irq(unsigned int irq)100 static void mxc_unmask_irq(unsigned int irq)
101 {
102 __raw_writel(irq, AVIC_INTENNUM);
103 }
104
105 static struct irq_chip mxc_avic_chip = {
106 .ack = mxc_mask_irq,
107 .mask = mxc_mask_irq,
108 .unmask = mxc_unmask_irq,
109 };
110
111 /*
112 * This function initializes the AVIC hardware and disables all the
113 * interrupts. It registers the interrupt enable and disable functions
114 * to the kernel for each interrupt source.
115 */
mxc_init_irq(void)116 void __init mxc_init_irq(void)
117 {
118 int i;
119
120 /* put the AVIC into the reset value with
121 * all interrupts disabled
122 */
123 __raw_writel(0, AVIC_INTCNTL);
124 __raw_writel(0x1f, AVIC_NIMASK);
125
126 /* disable all interrupts */
127 __raw_writel(0, AVIC_INTENABLEH);
128 __raw_writel(0, AVIC_INTENABLEL);
129
130 /* all IRQ no FIQ */
131 __raw_writel(0, AVIC_INTTYPEH);
132 __raw_writel(0, AVIC_INTTYPEL);
133 for (i = 0; i < MXC_INTERNAL_IRQS; i++) {
134 set_irq_chip(i, &mxc_avic_chip);
135 set_irq_handler(i, handle_level_irq);
136 set_irq_flags(i, IRQF_VALID);
137 }
138
139 /* Set default priority value (0) for all IRQ's */
140 for (i = 0; i < 8; i++)
141 __raw_writel(0, AVIC_NIPRIORITY(i));
142
143 /* init architectures chained interrupt handler */
144 mxc_register_gpios();
145
146 #ifdef CONFIG_FIQ
147 /* Initialize FIQ */
148 init_FIQ();
149 #endif
150
151 printk(KERN_INFO "MXC IRQ initialized\n");
152 }
153