1 /*
2 * arch/arm/plat-orion/gpio.c
3 *
4 * Marvell Orion SoC GPIO handling.
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/irq.h>
14 #include <linux/module.h>
15 #include <linux/spinlock.h>
16 #include <linux/bitops.h>
17 #include <linux/io.h>
18 #include <asm/gpio.h>
19
20 static DEFINE_SPINLOCK(gpio_lock);
21 static const char *gpio_label[GPIO_MAX]; /* non null for allocated GPIOs */
22 static unsigned long gpio_valid[BITS_TO_LONGS(GPIO_MAX)];
23
__set_direction(unsigned pin,int input)24 static inline void __set_direction(unsigned pin, int input)
25 {
26 u32 u;
27
28 u = readl(GPIO_IO_CONF(pin));
29 if (input)
30 u |= 1 << (pin & 31);
31 else
32 u &= ~(1 << (pin & 31));
33 writel(u, GPIO_IO_CONF(pin));
34 }
35
__set_level(unsigned pin,int high)36 static void __set_level(unsigned pin, int high)
37 {
38 u32 u;
39
40 u = readl(GPIO_OUT(pin));
41 if (high)
42 u |= 1 << (pin & 31);
43 else
44 u &= ~(1 << (pin & 31));
45 writel(u, GPIO_OUT(pin));
46 }
47
48
49 /*
50 * GENERIC_GPIO primitives.
51 */
gpio_direction_input(unsigned pin)52 int gpio_direction_input(unsigned pin)
53 {
54 unsigned long flags;
55
56 if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) {
57 pr_debug("%s: invalid GPIO %d\n", __func__, pin);
58 return -EINVAL;
59 }
60
61 spin_lock_irqsave(&gpio_lock, flags);
62
63 /*
64 * Some callers might not have used gpio_request(),
65 * so flag this pin as requested now.
66 */
67 if (gpio_label[pin] == NULL)
68 gpio_label[pin] = "?";
69
70 /*
71 * Configure GPIO direction.
72 */
73 __set_direction(pin, 1);
74
75 spin_unlock_irqrestore(&gpio_lock, flags);
76
77 return 0;
78 }
79 EXPORT_SYMBOL(gpio_direction_input);
80
gpio_direction_output(unsigned pin,int value)81 int gpio_direction_output(unsigned pin, int value)
82 {
83 unsigned long flags;
84 u32 u;
85
86 if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) {
87 pr_debug("%s: invalid GPIO %d\n", __func__, pin);
88 return -EINVAL;
89 }
90
91 spin_lock_irqsave(&gpio_lock, flags);
92
93 /*
94 * Some callers might not have used gpio_request(),
95 * so flag this pin as requested now.
96 */
97 if (gpio_label[pin] == NULL)
98 gpio_label[pin] = "?";
99
100 /*
101 * Disable blinking.
102 */
103 u = readl(GPIO_BLINK_EN(pin));
104 u &= ~(1 << (pin & 31));
105 writel(u, GPIO_BLINK_EN(pin));
106
107 /*
108 * Configure GPIO output value.
109 */
110 __set_level(pin, value);
111
112 /*
113 * Configure GPIO direction.
114 */
115 __set_direction(pin, 0);
116
117 spin_unlock_irqrestore(&gpio_lock, flags);
118
119 return 0;
120 }
121 EXPORT_SYMBOL(gpio_direction_output);
122
gpio_get_value(unsigned pin)123 int gpio_get_value(unsigned pin)
124 {
125 int val;
126
127 if (readl(GPIO_IO_CONF(pin)) & (1 << (pin & 31)))
128 val = readl(GPIO_DATA_IN(pin)) ^ readl(GPIO_IN_POL(pin));
129 else
130 val = readl(GPIO_OUT(pin));
131
132 return (val >> (pin & 31)) & 1;
133 }
134 EXPORT_SYMBOL(gpio_get_value);
135
gpio_set_value(unsigned pin,int value)136 void gpio_set_value(unsigned pin, int value)
137 {
138 unsigned long flags;
139 u32 u;
140
141 spin_lock_irqsave(&gpio_lock, flags);
142
143 /*
144 * Disable blinking.
145 */
146 u = readl(GPIO_BLINK_EN(pin));
147 u &= ~(1 << (pin & 31));
148 writel(u, GPIO_BLINK_EN(pin));
149
150 /*
151 * Configure GPIO output value.
152 */
153 __set_level(pin, value);
154
155 spin_unlock_irqrestore(&gpio_lock, flags);
156 }
157 EXPORT_SYMBOL(gpio_set_value);
158
gpio_request(unsigned pin,const char * label)159 int gpio_request(unsigned pin, const char *label)
160 {
161 unsigned long flags;
162 int ret;
163
164 if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) {
165 pr_debug("%s: invalid GPIO %d\n", __func__, pin);
166 return -EINVAL;
167 }
168
169 spin_lock_irqsave(&gpio_lock, flags);
170 if (gpio_label[pin] == NULL) {
171 gpio_label[pin] = label ? label : "?";
172 ret = 0;
173 } else {
174 pr_debug("%s: GPIO %d already used as %s\n",
175 __func__, pin, gpio_label[pin]);
176 ret = -EBUSY;
177 }
178 spin_unlock_irqrestore(&gpio_lock, flags);
179
180 return ret;
181 }
182 EXPORT_SYMBOL(gpio_request);
183
gpio_free(unsigned pin)184 void gpio_free(unsigned pin)
185 {
186 if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) {
187 pr_debug("%s: invalid GPIO %d\n", __func__, pin);
188 return;
189 }
190
191 if (gpio_label[pin] == NULL)
192 pr_warning("%s: GPIO %d already freed\n", __func__, pin);
193 else
194 gpio_label[pin] = NULL;
195 }
196 EXPORT_SYMBOL(gpio_free);
197
198
199 /*
200 * Orion-specific GPIO API extensions.
201 */
orion_gpio_set_unused(unsigned pin)202 void __init orion_gpio_set_unused(unsigned pin)
203 {
204 /*
205 * Configure as output, drive low.
206 */
207 __set_level(pin, 0);
208 __set_direction(pin, 0);
209 }
210
orion_gpio_set_valid(unsigned pin,int valid)211 void __init orion_gpio_set_valid(unsigned pin, int valid)
212 {
213 if (valid)
214 __set_bit(pin, gpio_valid);
215 else
216 __clear_bit(pin, gpio_valid);
217 }
218
orion_gpio_set_blink(unsigned pin,int blink)219 void orion_gpio_set_blink(unsigned pin, int blink)
220 {
221 unsigned long flags;
222 u32 u;
223
224 spin_lock_irqsave(&gpio_lock, flags);
225
226 /*
227 * Set output value to zero.
228 */
229 __set_level(pin, 0);
230
231 u = readl(GPIO_BLINK_EN(pin));
232 if (blink)
233 u |= 1 << (pin & 31);
234 else
235 u &= ~(1 << (pin & 31));
236 writel(u, GPIO_BLINK_EN(pin));
237
238 spin_unlock_irqrestore(&gpio_lock, flags);
239 }
240 EXPORT_SYMBOL(orion_gpio_set_blink);
241
242
243 /*****************************************************************************
244 * Orion GPIO IRQ
245 *
246 * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same
247 * value of the line or the opposite value.
248 *
249 * Level IRQ handlers: DATA_IN is used directly as cause register.
250 * Interrupt are masked by LEVEL_MASK registers.
251 * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE.
252 * Interrupt are masked by EDGE_MASK registers.
253 * Both-edge handlers: Similar to regular Edge handlers, but also swaps
254 * the polarity to catch the next line transaction.
255 * This is a race condition that might not perfectly
256 * work on some use cases.
257 *
258 * Every eight GPIO lines are grouped (OR'ed) before going up to main
259 * cause register.
260 *
261 * EDGE cause mask
262 * data-in /--------| |-----| |----\
263 * -----| |----- ---- to main cause reg
264 * X \----------------| |----/
265 * polarity LEVEL mask
266 *
267 ****************************************************************************/
268
gpio_irq_ack(u32 irq)269 static void gpio_irq_ack(u32 irq)
270 {
271 int type = irq_desc[irq].status & IRQ_TYPE_SENSE_MASK;
272 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
273 int pin = irq_to_gpio(irq);
274 writel(~(1 << (pin & 31)), GPIO_EDGE_CAUSE(pin));
275 }
276 }
277
gpio_irq_mask(u32 irq)278 static void gpio_irq_mask(u32 irq)
279 {
280 int pin = irq_to_gpio(irq);
281 int type = irq_desc[irq].status & IRQ_TYPE_SENSE_MASK;
282 u32 reg = (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) ?
283 GPIO_EDGE_MASK(pin) : GPIO_LEVEL_MASK(pin);
284 u32 u = readl(reg);
285 u &= ~(1 << (pin & 31));
286 writel(u, reg);
287 }
288
gpio_irq_unmask(u32 irq)289 static void gpio_irq_unmask(u32 irq)
290 {
291 int pin = irq_to_gpio(irq);
292 int type = irq_desc[irq].status & IRQ_TYPE_SENSE_MASK;
293 u32 reg = (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) ?
294 GPIO_EDGE_MASK(pin) : GPIO_LEVEL_MASK(pin);
295 u32 u = readl(reg);
296 u |= 1 << (pin & 31);
297 writel(u, reg);
298 }
299
gpio_irq_set_type(u32 irq,u32 type)300 static int gpio_irq_set_type(u32 irq, u32 type)
301 {
302 int pin = irq_to_gpio(irq);
303 struct irq_desc *desc;
304 u32 u;
305
306 u = readl(GPIO_IO_CONF(pin)) & (1 << (pin & 31));
307 if (!u) {
308 printk(KERN_ERR "orion gpio_irq_set_type failed "
309 "(irq %d, pin %d).\n", irq, pin);
310 return -EINVAL;
311 }
312
313 desc = irq_desc + irq;
314
315 /*
316 * Set edge/level type.
317 */
318 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
319 desc->handle_irq = handle_edge_irq;
320 } else if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
321 desc->handle_irq = handle_level_irq;
322 } else {
323 printk(KERN_ERR "failed to set irq=%d (type=%d)\n", irq, type);
324 return -EINVAL;
325 }
326
327 /*
328 * Configure interrupt polarity.
329 */
330 if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH) {
331 u = readl(GPIO_IN_POL(pin));
332 u &= ~(1 << (pin & 31));
333 writel(u, GPIO_IN_POL(pin));
334 } else if (type == IRQ_TYPE_EDGE_FALLING || type == IRQ_TYPE_LEVEL_LOW) {
335 u = readl(GPIO_IN_POL(pin));
336 u |= 1 << (pin & 31);
337 writel(u, GPIO_IN_POL(pin));
338 } else if (type == IRQ_TYPE_EDGE_BOTH) {
339 u32 v;
340
341 v = readl(GPIO_IN_POL(pin)) ^ readl(GPIO_DATA_IN(pin));
342
343 /*
344 * set initial polarity based on current input level
345 */
346 u = readl(GPIO_IN_POL(pin));
347 if (v & (1 << (pin & 31)))
348 u |= 1 << (pin & 31); /* falling */
349 else
350 u &= ~(1 << (pin & 31)); /* rising */
351 writel(u, GPIO_IN_POL(pin));
352 }
353
354 desc->status = (desc->status & ~IRQ_TYPE_SENSE_MASK) | type;
355
356 return 0;
357 }
358
359 struct irq_chip orion_gpio_irq_chip = {
360 .name = "orion_gpio",
361 .ack = gpio_irq_ack,
362 .mask = gpio_irq_mask,
363 .unmask = gpio_irq_unmask,
364 .set_type = gpio_irq_set_type,
365 };
366
orion_gpio_irq_handler(int pinoff)367 void orion_gpio_irq_handler(int pinoff)
368 {
369 u32 cause;
370 int pin;
371
372 cause = readl(GPIO_DATA_IN(pinoff)) & readl(GPIO_LEVEL_MASK(pinoff));
373 cause |= readl(GPIO_EDGE_CAUSE(pinoff)) & readl(GPIO_EDGE_MASK(pinoff));
374
375 for (pin = pinoff; pin < pinoff + 8; pin++) {
376 int irq = gpio_to_irq(pin);
377 struct irq_desc *desc = irq_desc + irq;
378
379 if (!(cause & (1 << (pin & 31))))
380 continue;
381
382 if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
383 /* Swap polarity (race with GPIO line) */
384 u32 polarity;
385
386 polarity = readl(GPIO_IN_POL(pin));
387 polarity ^= 1 << (pin & 31);
388 writel(polarity, GPIO_IN_POL(pin));
389 }
390 desc_handle_irq(irq, desc);
391 }
392 }
393