1 /* 2 * File: include/asm-blackfin/mach-bf518/blackfin.h 3 * Based on: 4 * Author: 5 * 6 * Created: 7 * Description: 8 * 9 * Rev: 10 * 11 * Modified: 12 * 13 * 14 * Bugs: Enter bugs at http://blackfin.uclinux.org/ 15 * 16 * This program is free software; you can redistribute it and/or modify 17 * it under the terms of the GNU General Public License as published by 18 * the Free Software Foundation; either version 2, or (at your option) 19 * any later version. 20 * 21 * This program is distributed in the hope that it will be useful, 22 * but WITHOUT ANY WARRANTY; without even the implied warranty of 23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24 * GNU General Public License for more details. 25 * 26 * You should have received a copy of the GNU General Public License 27 * along with this program; see the file COPYING. 28 * If not, write to the Free Software Foundation, 29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 30 */ 31 32 #ifndef _MACH_BLACKFIN_H_ 33 #define _MACH_BLACKFIN_H_ 34 35 #define BF518_FAMILY 36 37 #include "bf518.h" 38 #include "mem_map.h" 39 #include "defBF512.h" 40 #include "anomaly.h" 41 42 #if defined(CONFIG_BF518) 43 #include "defBF518.h" 44 #endif 45 46 #if defined(CONFIG_BF516) 47 #include "defBF516.h" 48 #endif 49 50 #if defined(CONFIG_BF514) 51 #include "defBF514.h" 52 #endif 53 54 #if defined(CONFIG_BF512) 55 #include "defBF512.h" 56 #endif 57 58 #if !defined(__ASSEMBLY__) 59 #include "cdefBF512.h" 60 61 #if defined(CONFIG_BF518) 62 #include "cdefBF518.h" 63 #endif 64 65 #if defined(CONFIG_BF516) 66 #include "cdefBF516.h" 67 #endif 68 69 #if defined(CONFIG_BF514) 70 #include "cdefBF514.h" 71 #endif 72 #endif 73 74 /* UART_IIR Register */ 75 #define STATUS(x) ((x << 1) & 0x06) 76 #define STATUS_P1 0x02 77 #define STATUS_P0 0x01 78 79 #define BFIN_UART_NR_PORTS 2 80 81 #define OFFSET_THR 0x00 /* Transmit Holding register */ 82 #define OFFSET_RBR 0x00 /* Receive Buffer register */ 83 #define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ 84 #define OFFSET_IER 0x04 /* Interrupt Enable Register */ 85 #define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */ 86 #define OFFSET_IIR 0x08 /* Interrupt Identification Register */ 87 #define OFFSET_LCR 0x0C /* Line Control Register */ 88 #define OFFSET_MCR 0x10 /* Modem Control Register */ 89 #define OFFSET_LSR 0x14 /* Line Status Register */ 90 #define OFFSET_MSR 0x18 /* Modem Status Register */ 91 #define OFFSET_SCR 0x1C /* SCR Scratch Register */ 92 #define OFFSET_GCTL 0x24 /* Global Control Register */ 93 94 /* DPMC*/ 95 #define bfin_read_STOPCK_OFF() bfin_read_STOPCK() 96 #define bfin_write_STOPCK_OFF(val) bfin_write_STOPCK(val) 97 #define STOPCK_OFF STOPCK 98 99 /* PLL_DIV Masks */ 100 #define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */ 101 #define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */ 102 #define CCLK_DIV4 CSEL_DIV4 /* CCLK = VCO / 4 */ 103 #define CCLK_DIV8 CSEL_DIV8 /* CCLK = VCO / 8 */ 104 105 #endif 106