1 /* 2 * File: include/asm-blackfin/mach-bf518/defBF518.h 3 * Based on: 4 * Author: 5 * 6 * Created: 7 * Description: 8 * 9 * Rev: 10 * 11 * Modified: 12 * 13 * Bugs: Enter bugs at http://blackfin.uclinux.org/ 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License as published by 17 * the Free Software Foundation; either version 2, or (at your option) 18 * any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; see the file COPYING. 27 * If not, write to the Free Software Foundation, 28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 29 */ 30 31 #ifndef _DEF_BF518_H 32 #define _DEF_BF518_H 33 34 /* Include all Core registers and bit definitions */ 35 #include <asm/def_LPBlackfin.h> 36 37 /* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF518 */ 38 39 /* Include defBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */ 40 #include "defBF51x_base.h" 41 42 /* The following are the #defines needed by ADSP-BF518 that are not in the common header */ 43 /* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */ 44 45 #define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */ 46 #define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */ 47 #define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */ 48 #define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */ 49 #define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */ 50 #define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */ 51 #define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */ 52 #define EMAC_FLC 0xFFC0301C /* Flow Control Register */ 53 #define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */ 54 #define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */ 55 #define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */ 56 #define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */ 57 #define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */ 58 #define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */ 59 #define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */ 60 #define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */ 61 #define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */ 62 #define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */ 63 #define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */ 64 65 #define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */ 66 #define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */ 67 #define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */ 68 #define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */ 69 #define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */ 70 #define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */ 71 #define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */ 72 #define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */ 73 74 #define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */ 75 #define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */ 76 #define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */ 77 #define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */ 78 #define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */ 79 80 #define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */ 81 #define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */ 82 #define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */ 83 #define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */ 84 #define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */ 85 #define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */ 86 #define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */ 87 #define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */ 88 #define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */ 89 #define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */ 90 #define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */ 91 #define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */ 92 #define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */ 93 #define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */ 94 #define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */ 95 #define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */ 96 #define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */ 97 #define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */ 98 #define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */ 99 #define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 < x < 128 */ 100 #define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */ 101 #define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */ 102 #define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */ 103 #define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */ 104 105 #define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */ 106 #define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */ 107 #define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */ 108 #define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */ 109 #define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */ 110 #define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */ 111 #define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */ 112 #define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */ 113 #define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */ 114 #define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */ 115 #define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */ 116 #define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */ 117 #define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */ 118 #define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */ 119 #define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */ 120 #define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */ 121 #define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */ 122 #define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 < x < 128 */ 123 #define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */ 124 #define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */ 125 #define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */ 126 #define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */ 127 #define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */ 128 129 /* Listing for IEEE-Supported Count Registers */ 130 131 #define FramesReceivedOK EMAC_RXC_OK /* RX Frame Successful Count */ 132 #define FrameCheckSequenceErrors EMAC_RXC_FCS /* RX Frame FCS Failure Count */ 133 #define AlignmentErrors EMAC_RXC_ALIGN /* RX Alignment Error Count */ 134 #define OctetsReceivedOK EMAC_RXC_OCTET /* RX Octets Successfully Received Count */ 135 #define FramesLostDueToIntMACRcvError EMAC_RXC_DMAOVF /* Internal MAC Sublayer Error RX Frame Count */ 136 #define UnicastFramesReceivedOK EMAC_RXC_UNICST /* Unicast RX Frame Count */ 137 #define MulticastFramesReceivedOK EMAC_RXC_MULTI /* Multicast RX Frame Count */ 138 #define BroadcastFramesReceivedOK EMAC_RXC_BROAD /* Broadcast RX Frame Count */ 139 #define InRangeLengthErrors EMAC_RXC_LNERRI /* RX Frame In Range Error Count */ 140 #define OutOfRangeLengthField EMAC_RXC_LNERRO /* RX Frame Out Of Range Error Count */ 141 #define FrameTooLongErrors EMAC_RXC_LONG /* RX Frame Too Long Count */ 142 #define MACControlFramesReceived EMAC_RXC_MACCTL /* MAC Control RX Frame Count */ 143 #define UnsupportedOpcodesReceived EMAC_RXC_OPCODE /* Unsupported Op-Code RX Frame Count */ 144 #define PAUSEMACCtrlFramesReceived EMAC_RXC_PAUSE /* MAC Control Pause RX Frame Count */ 145 #define FramesReceivedAll EMAC_RXC_ALLFRM /* Overall RX Frame Count */ 146 #define OctetsReceivedAll EMAC_RXC_ALLOCT /* Overall RX Octet Count */ 147 #define TypedFramesReceived EMAC_RXC_TYPED /* Type/Length Consistent RX Frame Count */ 148 #define FramesLenLt64Received EMAC_RXC_SHORT /* RX Frame Fragment Count - Byte Count x < 64 */ 149 #define FramesLenEq64Received EMAC_RXC_EQ64 /* Good RX Frame Count - Byte Count x = 64 */ 150 #define FramesLen65_127Received EMAC_RXC_LT128 /* Good RX Frame Count - Byte Count 64 < x < 128 */ 151 #define FramesLen128_255Received EMAC_RXC_LT256 /* Good RX Frame Count - Byte Count 128 <= x < 256 */ 152 #define FramesLen256_511Received EMAC_RXC_LT512 /* Good RX Frame Count - Byte Count 256 <= x < 512 */ 153 #define FramesLen512_1023Received EMAC_RXC_LT1024 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */ 154 #define FramesLen1024_MaxReceived EMAC_RXC_GE1024 /* Good RX Frame Count - Byte Count x >= 1024 */ 155 156 #define FramesTransmittedOK EMAC_TXC_OK /* TX Frame Successful Count */ 157 #define SingleCollisionFrames EMAC_TXC_1COL /* TX Frames Successful After Single Collision Count */ 158 #define MultipleCollisionFrames EMAC_TXC_GT1COL /* TX Frames Successful After Multiple Collisions Count */ 159 #define OctetsTransmittedOK EMAC_TXC_OCTET /* TX Octets Successfully Received Count */ 160 #define FramesWithDeferredXmissions EMAC_TXC_DEFER /* TX Frame Delayed Due To Busy Count */ 161 #define LateCollisions EMAC_TXC_LATECL /* Late TX Collisions Count */ 162 #define FramesAbortedDueToXSColls EMAC_TXC_XS_COL /* TX Frame Failed Due To Excessive Collisions Count */ 163 #define FramesLostDueToIntMacXmitError EMAC_TXC_DMAUND /* Internal MAC Sublayer Error TX Frame Count */ 164 #define CarrierSenseErrors EMAC_TXC_CRSERR /* Carrier Sense Deasserted During TX Frame Count */ 165 #define UnicastFramesXmittedOK EMAC_TXC_UNICST /* Unicast TX Frame Count */ 166 #define MulticastFramesXmittedOK EMAC_TXC_MULTI /* Multicast TX Frame Count */ 167 #define BroadcastFramesXmittedOK EMAC_TXC_BROAD /* Broadcast TX Frame Count */ 168 #define FramesWithExcessiveDeferral EMAC_TXC_XS_DFR /* TX Frames With Excessive Deferral Count */ 169 #define MACControlFramesTransmitted EMAC_TXC_MACCTL /* MAC Control TX Frame Count */ 170 #define FramesTransmittedAll EMAC_TXC_ALLFRM /* Overall TX Frame Count */ 171 #define OctetsTransmittedAll EMAC_TXC_ALLOCT /* Overall TX Octet Count */ 172 #define FramesLenEq64Transmitted EMAC_TXC_EQ64 /* Good TX Frame Count - Byte Count x = 64 */ 173 #define FramesLen65_127Transmitted EMAC_TXC_LT128 /* Good TX Frame Count - Byte Count 64 < x < 128 */ 174 #define FramesLen128_255Transmitted EMAC_TXC_LT256 /* Good TX Frame Count - Byte Count 128 <= x < 256 */ 175 #define FramesLen256_511Transmitted EMAC_TXC_LT512 /* Good TX Frame Count - Byte Count 256 <= x < 512 */ 176 #define FramesLen512_1023Transmitted EMAC_TXC_LT1024 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */ 177 #define FramesLen1024_MaxTransmitted EMAC_TXC_GE1024 /* Good TX Frame Count - Byte Count x >= 1024 */ 178 #define TxAbortedFrames EMAC_TXC_ABORT /* Total TX Frames Aborted Count */ 179 180 /*********************************************************************************** 181 ** System MMR Register Bits And Macros 182 ** 183 ** Disclaimer: All macros are intended to make C and Assembly code more readable. 184 ** Use these macros carefully, as any that do left shifts for field 185 ** depositing will result in the lower order bits being destroyed. Any 186 ** macro that shifts left to properly position the bit-field should be 187 ** used as part of an OR to initialize a register and NOT as a dynamic 188 ** modifier UNLESS the lower order bits are saved and ORed back in when 189 ** the macro is used. 190 *************************************************************************************/ 191 192 /************************ ETHERNET 10/100 CONTROLLER MASKS ************************/ 193 194 /* EMAC_OPMODE Masks */ 195 196 #define RE 0x00000001 /* Receiver Enable */ 197 #define ASTP 0x00000002 /* Enable Automatic Pad Stripping On RX Frames */ 198 #define HU 0x00000010 /* Hash Filter Unicast Address */ 199 #define HM 0x00000020 /* Hash Filter Multicast Address */ 200 #define PAM 0x00000040 /* Pass-All-Multicast Mode Enable */ 201 #define PR 0x00000080 /* Promiscuous Mode Enable */ 202 #define IFE 0x00000100 /* Inverse Filtering Enable */ 203 #define DBF 0x00000200 /* Disable Broadcast Frame Reception */ 204 #define PBF 0x00000400 /* Pass Bad Frames Enable */ 205 #define PSF 0x00000800 /* Pass Short Frames Enable */ 206 #define RAF 0x00001000 /* Receive-All Mode */ 207 #define TE 0x00010000 /* Transmitter Enable */ 208 #define DTXPAD 0x00020000 /* Disable Automatic TX Padding */ 209 #define DTXCRC 0x00040000 /* Disable Automatic TX CRC Generation */ 210 #define DC 0x00080000 /* Deferral Check */ 211 #define BOLMT 0x00300000 /* Back-Off Limit */ 212 #define BOLMT_10 0x00000000 /* 10-bit range */ 213 #define BOLMT_8 0x00100000 /* 8-bit range */ 214 #define BOLMT_4 0x00200000 /* 4-bit range */ 215 #define BOLMT_1 0x00300000 /* 1-bit range */ 216 #define DRTY 0x00400000 /* Disable TX Retry On Collision */ 217 #define LCTRE 0x00800000 /* Enable TX Retry On Late Collision */ 218 #define RMII 0x01000000 /* RMII/MII* Mode */ 219 #define RMII_10 0x02000000 /* Speed Select for RMII Port (10MBit/100MBit*) */ 220 #define FDMODE 0x04000000 /* Duplex Mode Enable (Full/Half*) */ 221 #define LB 0x08000000 /* Internal Loopback Enable */ 222 #define DRO 0x10000000 /* Disable Receive Own Frames (Half-Duplex Mode) */ 223 224 /* EMAC_STAADD Masks */ 225 226 #define STABUSY 0x00000001 /* Initiate Station Mgt Reg Access / STA Busy Stat */ 227 #define STAOP 0x00000002 /* Station Management Operation Code (Write/Read*) */ 228 #define STADISPRE 0x00000004 /* Disable Preamble Generation */ 229 #define STAIE 0x00000008 /* Station Mgt. Transfer Done Interrupt Enable */ 230 #define REGAD 0x000007C0 /* STA Register Address */ 231 #define PHYAD 0x0000F800 /* PHY Device Address */ 232 233 #define SET_REGAD(x) (((x)&0x1F)<< 6 ) /* Set STA Register Address */ 234 #define SET_PHYAD(x) (((x)&0x1F)<< 11 ) /* Set PHY Device Address */ 235 236 /* EMAC_STADAT Mask */ 237 238 #define STADATA 0x0000FFFF /* Station Management Data */ 239 240 /* EMAC_FLC Masks */ 241 242 #define FLCBUSY 0x00000001 /* Send Flow Ctrl Frame / Flow Ctrl Busy Status */ 243 #define FLCE 0x00000002 /* Flow Control Enable */ 244 #define PCF 0x00000004 /* Pass Control Frames */ 245 #define BKPRSEN 0x00000008 /* Enable Backpressure */ 246 #define FLCPAUSE 0xFFFF0000 /* Pause Time */ 247 248 #define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time */ 249 250 /* EMAC_WKUP_CTL Masks */ 251 252 #define CAPWKFRM 0x00000001 /* Capture Wake-Up Frames */ 253 #define MPKE 0x00000002 /* Magic Packet Enable */ 254 #define RWKE 0x00000004 /* Remote Wake-Up Frame Enable */ 255 #define GUWKE 0x00000008 /* Global Unicast Wake Enable */ 256 #define MPKS 0x00000020 /* Magic Packet Received Status */ 257 #define RWKS 0x00000F00 /* Wake-Up Frame Received Status, Filters 3:0 */ 258 259 /* EMAC_WKUP_FFCMD Masks */ 260 261 #define WF0_E 0x00000001 /* Enable Wake-Up Filter 0 */ 262 #define WF0_T 0x00000008 /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*) */ 263 #define WF1_E 0x00000100 /* Enable Wake-Up Filter 1 */ 264 #define WF1_T 0x00000800 /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*) */ 265 #define WF2_E 0x00010000 /* Enable Wake-Up Filter 2 */ 266 #define WF2_T 0x00080000 /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*) */ 267 #define WF3_E 0x01000000 /* Enable Wake-Up Filter 3 */ 268 #define WF3_T 0x08000000 /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*) */ 269 270 /* EMAC_WKUP_FFOFF Masks */ 271 272 #define WF0_OFF 0x000000FF /* Wake-Up Filter 0 Pattern Offset */ 273 #define WF1_OFF 0x0000FF00 /* Wake-Up Filter 1 Pattern Offset */ 274 #define WF2_OFF 0x00FF0000 /* Wake-Up Filter 2 Pattern Offset */ 275 #define WF3_OFF 0xFF000000 /* Wake-Up Filter 3 Pattern Offset */ 276 277 #define SET_WF0_OFF(x) (((x)&0xFF)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */ 278 #define SET_WF1_OFF(x) (((x)&0xFF)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */ 279 #define SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */ 280 #define SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */ 281 /* Set ALL Offsets */ 282 #define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3))) 283 284 /* EMAC_WKUP_FFCRC0 Masks */ 285 286 #define WF0_CRC 0x0000FFFF /* Wake-Up Filter 0 Pattern CRC */ 287 #define WF1_CRC 0xFFFF0000 /* Wake-Up Filter 1 Pattern CRC */ 288 289 #define SET_WF0_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 0 Target CRC */ 290 #define SET_WF1_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 1 Target CRC */ 291 292 /* EMAC_WKUP_FFCRC1 Masks */ 293 294 #define WF2_CRC 0x0000FFFF /* Wake-Up Filter 2 Pattern CRC */ 295 #define WF3_CRC 0xFFFF0000 /* Wake-Up Filter 3 Pattern CRC */ 296 297 #define SET_WF2_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 2 Target CRC */ 298 #define SET_WF3_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 3 Target CRC */ 299 300 /* EMAC_SYSCTL Masks */ 301 302 #define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */ 303 #define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */ 304 #define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */ 305 #define TXDWA 0x00000010 /* Transmit Frame DMA Word Alignment (Odd/Even*) */ 306 #define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */ 307 308 #define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */ 309 310 /* EMAC_SYSTAT Masks */ 311 312 #define PHYINT 0x00000001 /* PHY_INT Interrupt Status */ 313 #define MMCINT 0x00000002 /* MMC Counter Interrupt Status */ 314 #define RXFSINT 0x00000004 /* RX Frame-Status Interrupt Status */ 315 #define TXFSINT 0x00000008 /* TX Frame-Status Interrupt Status */ 316 #define WAKEDET 0x00000010 /* Wake-Up Detected Status */ 317 #define RXDMAERR 0x00000020 /* RX DMA Direction Error Status */ 318 #define TXDMAERR 0x00000040 /* TX DMA Direction Error Status */ 319 #define STMDONE 0x00000080 /* Station Mgt. Transfer Done Interrupt Status */ 320 321 /* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */ 322 323 #define RX_FRLEN 0x000007FF /* Frame Length In Bytes */ 324 #define RX_COMP 0x00001000 /* RX Frame Complete */ 325 #define RX_OK 0x00002000 /* RX Frame Received With No Errors */ 326 #define RX_LONG 0x00004000 /* RX Frame Too Long Error */ 327 #define RX_ALIGN 0x00008000 /* RX Frame Alignment Error */ 328 #define RX_CRC 0x00010000 /* RX Frame CRC Error */ 329 #define RX_LEN 0x00020000 /* RX Frame Length Error */ 330 #define RX_FRAG 0x00040000 /* RX Frame Fragment Error */ 331 #define RX_ADDR 0x00080000 /* RX Frame Address Filter Failed Error */ 332 #define RX_DMAO 0x00100000 /* RX Frame DMA Overrun Error */ 333 #define RX_PHY 0x00200000 /* RX Frame PHY Error */ 334 #define RX_LATE 0x00400000 /* RX Frame Late Collision Error */ 335 #define RX_RANGE 0x00800000 /* RX Frame Length Field Out of Range Error */ 336 #define RX_MULTI 0x01000000 /* RX Multicast Frame Indicator */ 337 #define RX_BROAD 0x02000000 /* RX Broadcast Frame Indicator */ 338 #define RX_CTL 0x04000000 /* RX Control Frame Indicator */ 339 #define RX_UCTL 0x08000000 /* Unsupported RX Control Frame Indicator */ 340 #define RX_TYPE 0x10000000 /* RX Typed Frame Indicator */ 341 #define RX_VLAN1 0x20000000 /* RX VLAN1 Frame Indicator */ 342 #define RX_VLAN2 0x40000000 /* RX VLAN2 Frame Indicator */ 343 #define RX_ACCEPT 0x80000000 /* RX Frame Accepted Indicator */ 344 345 /* EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks */ 346 347 #define TX_COMP 0x00000001 /* TX Frame Complete */ 348 #define TX_OK 0x00000002 /* TX Frame Sent With No Errors */ 349 #define TX_ECOLL 0x00000004 /* TX Frame Excessive Collision Error */ 350 #define TX_LATE 0x00000008 /* TX Frame Late Collision Error */ 351 #define TX_DMAU 0x00000010 /* TX Frame DMA Underrun Error (STAT) */ 352 #define TX_MACE 0x00000010 /* Internal MAC Error Detected (STKY and IRQE) */ 353 #define TX_EDEFER 0x00000020 /* TX Frame Excessive Deferral Error */ 354 #define TX_BROAD 0x00000040 /* TX Broadcast Frame Indicator */ 355 #define TX_MULTI 0x00000080 /* TX Multicast Frame Indicator */ 356 #define TX_CCNT 0x00000F00 /* TX Frame Collision Count */ 357 #define TX_DEFER 0x00001000 /* TX Frame Deferred Indicator */ 358 #define TX_CRS 0x00002000 /* TX Frame Carrier Sense Not Asserted Error */ 359 #define TX_LOSS 0x00004000 /* TX Frame Carrier Lost During TX Error */ 360 #define TX_RETRY 0x00008000 /* TX Frame Successful After Retry */ 361 #define TX_FRLEN 0x07FF0000 /* TX Frame Length (Bytes) */ 362 363 /* EMAC_MMC_CTL Masks */ 364 #define RSTC 0x00000001 /* Reset All Counters */ 365 #define CROLL 0x00000002 /* Counter Roll-Over Enable */ 366 #define CCOR 0x00000004 /* Counter Clear-On-Read Mode Enable */ 367 #define MMCE 0x00000008 /* Enable MMC Counter Operation */ 368 369 /* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */ 370 #define RX_OK_CNT 0x00000001 /* RX Frames Received With No Errors */ 371 #define RX_FCS_CNT 0x00000002 /* RX Frames W/Frame Check Sequence Errors */ 372 #define RX_ALIGN_CNT 0x00000004 /* RX Frames With Alignment Errors */ 373 #define RX_OCTET_CNT 0x00000008 /* RX Octets Received OK */ 374 #define RX_LOST_CNT 0x00000010 /* RX Frames Lost Due To Internal MAC RX Error */ 375 #define RX_UNI_CNT 0x00000020 /* Unicast RX Frames Received OK */ 376 #define RX_MULTI_CNT 0x00000040 /* Multicast RX Frames Received OK */ 377 #define RX_BROAD_CNT 0x00000080 /* Broadcast RX Frames Received OK */ 378 #define RX_IRL_CNT 0x00000100 /* RX Frames With In-Range Length Errors */ 379 #define RX_ORL_CNT 0x00000200 /* RX Frames With Out-Of-Range Length Errors */ 380 #define RX_LONG_CNT 0x00000400 /* RX Frames With Frame Too Long Errors */ 381 #define RX_MACCTL_CNT 0x00000800 /* MAC Control RX Frames Received */ 382 #define RX_OPCODE_CTL 0x00001000 /* Unsupported Op-Code RX Frames Received */ 383 #define RX_PAUSE_CNT 0x00002000 /* PAUSEMAC Control RX Frames Received */ 384 #define RX_ALLF_CNT 0x00004000 /* All RX Frames Received */ 385 #define RX_ALLO_CNT 0x00008000 /* All RX Octets Received */ 386 #define RX_TYPED_CNT 0x00010000 /* Typed RX Frames Received */ 387 #define RX_SHORT_CNT 0x00020000 /* RX Frame Fragments (< 64 Bytes) Received */ 388 #define RX_EQ64_CNT 0x00040000 /* 64-Byte RX Frames Received */ 389 #define RX_LT128_CNT 0x00080000 /* 65-127-Byte RX Frames Received */ 390 #define RX_LT256_CNT 0x00100000 /* 128-255-Byte RX Frames Received */ 391 #define RX_LT512_CNT 0x00200000 /* 256-511-Byte RX Frames Received */ 392 #define RX_LT1024_CNT 0x00400000 /* 512-1023-Byte RX Frames Received */ 393 #define RX_GE1024_CNT 0x00800000 /* 1024-Max-Byte RX Frames Received */ 394 395 /* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */ 396 397 #define TX_OK_CNT 0x00000001 /* TX Frames Sent OK */ 398 #define TX_SCOLL_CNT 0x00000002 /* TX Frames With Single Collisions */ 399 #define TX_MCOLL_CNT 0x00000004 /* TX Frames With Multiple Collisions */ 400 #define TX_OCTET_CNT 0x00000008 /* TX Octets Sent OK */ 401 #define TX_DEFER_CNT 0x00000010 /* TX Frames With Deferred Transmission */ 402 #define TX_LATE_CNT 0x00000020 /* TX Frames With Late Collisions */ 403 #define TX_ABORTC_CNT 0x00000040 /* TX Frames Aborted Due To Excess Collisions */ 404 #define TX_LOST_CNT 0x00000080 /* TX Frames Lost Due To Internal MAC TX Error */ 405 #define TX_CRS_CNT 0x00000100 /* TX Frames With Carrier Sense Errors */ 406 #define TX_UNI_CNT 0x00000200 /* Unicast TX Frames Sent */ 407 #define TX_MULTI_CNT 0x00000400 /* Multicast TX Frames Sent */ 408 #define TX_BROAD_CNT 0x00000800 /* Broadcast TX Frames Sent */ 409 #define TX_EXDEF_CTL 0x00001000 /* TX Frames With Excessive Deferral */ 410 #define TX_MACCTL_CNT 0x00002000 /* MAC Control TX Frames Sent */ 411 #define TX_ALLF_CNT 0x00004000 /* All TX Frames Sent */ 412 #define TX_ALLO_CNT 0x00008000 /* All TX Octets Sent */ 413 #define TX_EQ64_CNT 0x00010000 /* 64-Byte TX Frames Sent */ 414 #define TX_LT128_CNT 0x00020000 /* 65-127-Byte TX Frames Sent */ 415 #define TX_LT256_CNT 0x00040000 /* 128-255-Byte TX Frames Sent */ 416 #define TX_LT512_CNT 0x00080000 /* 256-511-Byte TX Frames Sent */ 417 #define TX_LT1024_CNT 0x00100000 /* 512-1023-Byte TX Frames Sent */ 418 #define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */ 419 #define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */ 420 421 /* SDH Registers */ 422 423 #define SDH_PWR_CTL 0xFFC03900 /* SDH Power Control */ 424 #define SDH_CLK_CTL 0xFFC03904 /* SDH Clock Control */ 425 #define SDH_ARGUMENT 0xFFC03908 /* SDH Argument */ 426 #define SDH_COMMAND 0xFFC0390C /* SDH Command */ 427 #define SDH_RESP_CMD 0xFFC03910 /* SDH Response Command */ 428 #define SDH_RESPONSE0 0xFFC03914 /* SDH Response0 */ 429 #define SDH_RESPONSE1 0xFFC03918 /* SDH Response1 */ 430 #define SDH_RESPONSE2 0xFFC0391C /* SDH Response2 */ 431 #define SDH_RESPONSE3 0xFFC03920 /* SDH Response3 */ 432 #define SDH_DATA_TIMER 0xFFC03924 /* SDH Data Timer */ 433 #define SDH_DATA_LGTH 0xFFC03928 /* SDH Data Length */ 434 #define SDH_DATA_CTL 0xFFC0392C /* SDH Data Control */ 435 #define SDH_DATA_CNT 0xFFC03930 /* SDH Data Counter */ 436 #define SDH_STATUS 0xFFC03934 /* SDH Status */ 437 #define SDH_STATUS_CLR 0xFFC03938 /* SDH Status Clear */ 438 #define SDH_MASK0 0xFFC0393C /* SDH Interrupt0 Mask */ 439 #define SDH_MASK1 0xFFC03940 /* SDH Interrupt1 Mask */ 440 #define SDH_FIFO_CNT 0xFFC03948 /* SDH FIFO Counter */ 441 #define SDH_FIFO 0xFFC03980 /* SDH Data FIFO */ 442 #define SDH_E_STATUS 0xFFC039C0 /* SDH Exception Status */ 443 #define SDH_E_MASK 0xFFC039C4 /* SDH Exception Mask */ 444 #define SDH_CFG 0xFFC039C8 /* SDH Configuration */ 445 #define SDH_RD_WAIT_EN 0xFFC039CC /* SDH Read Wait Enable */ 446 #define SDH_PID0 0xFFC039D0 /* SDH Peripheral Identification0 */ 447 #define SDH_PID1 0xFFC039D4 /* SDH Peripheral Identification1 */ 448 #define SDH_PID2 0xFFC039D8 /* SDH Peripheral Identification2 */ 449 #define SDH_PID3 0xFFC039DC /* SDH Peripheral Identification3 */ 450 #define SDH_PID4 0xFFC039E0 /* SDH Peripheral Identification4 */ 451 #define SDH_PID5 0xFFC039E4 /* SDH Peripheral Identification5 */ 452 #define SDH_PID6 0xFFC039E8 /* SDH Peripheral Identification6 */ 453 #define SDH_PID7 0xFFC039EC /* SDH Peripheral Identification7 */ 454 455 /* Removable Storage Interface Registers */ 456 457 #define RSI_PWR_CONTROL 0xFFC03800 /* RSI Power Control Register */ 458 #define RSI_CLK_CONTROL 0xFFC03804 /* RSI Clock Control Register */ 459 #define RSI_ARGUMENT 0xFFC03808 /* RSI Argument Register */ 460 #define RSI_COMMAND 0xFFC0380C /* RSI Command Register */ 461 #define RSI_RESP_CMD 0xFFC03810 /* RSI Response Command Register */ 462 #define RSI_RESPONSE0 0xFFC03814 /* RSI Response Register */ 463 #define RSI_RESPONSE1 0xFFC03818 /* RSI Response Register */ 464 #define RSI_RESPONSE2 0xFFC0381C /* RSI Response Register */ 465 #define RSI_RESPONSE3 0xFFC03820 /* RSI Response Register */ 466 #define RSI_DATA_TIMER 0xFFC03824 /* RSI Data Timer Register */ 467 #define RSI_DATA_LGTH 0xFFC03828 /* RSI Data Length Register */ 468 #define RSI_DATA_CONTROL 0xFFC0382C /* RSI Data Control Register */ 469 #define RSI_DATA_CNT 0xFFC03830 /* RSI Data Counter Register */ 470 #define RSI_STATUS 0xFFC03834 /* RSI Status Register */ 471 #define RSI_STATUSCL 0xFFC03838 /* RSI Status Clear Register */ 472 #define RSI_MASK0 0xFFC0383C /* RSI Interrupt 0 Mask Register */ 473 #define RSI_MASK1 0xFFC03840 /* RSI Interrupt 1 Mask Register */ 474 #define RSI_FIFO_CNT 0xFFC03848 /* RSI FIFO Counter Register */ 475 #define RSI_CEATA_CONTROL 0xFFC0384C /* RSI CEATA Register */ 476 #define RSI_FIFO 0xFFC03880 /* RSI Data FIFO Register */ 477 #define RSI_ESTAT 0xFFC038C0 /* RSI Exception Status Register */ 478 #define RSI_EMASK 0xFFC038C4 /* RSI Exception Mask Register */ 479 #define RSI_CONFIG 0xFFC038C8 /* RSI Configuration Register */ 480 #define RSI_RD_WAIT_EN 0xFFC038CC /* RSI Read Wait Enable Register */ 481 #define RSI_PID0 0xFFC03FE0 /* RSI Peripheral ID Register 0 */ 482 #define RSI_PID1 0xFFC03FE4 /* RSI Peripheral ID Register 1 */ 483 #define RSI_PID2 0xFFC03FE8 /* RSI Peripheral ID Register 2 */ 484 #define RSI_PID3 0xFFC03FEC /* RSI Peripheral ID Register 3 */ 485 #define RSI_PID4 0xFFC03FF0 /* RSI Peripheral ID Register 4 */ 486 #define RSI_PID5 0xFFC03FF4 /* RSI Peripheral ID Register 5 */ 487 #define RSI_PID6 0xFFC03FF8 /* RSI Peripheral ID Register 6 */ 488 #define RSI_PID7 0xFFC03FFC /* RSI Peripheral ID Register 7 */ 489 490 /* PTP TSYNC Registers */ 491 492 #define EMAC_PTP_CTL 0xFFC030A0 /* PTP Block Control */ 493 #define EMAC_PTP_IE 0xFFC030A4 /* PTP Block Interrupt Enable */ 494 #define EMAC_PTP_ISTAT 0xFFC030A8 /* PTP Block Interrupt Status */ 495 #define EMAC_PTP_FOFF 0xFFC030AC /* PTP Filter offset Register */ 496 #define EMAC_PTP_FV1 0xFFC030B0 /* PTP Filter Value Register 1 */ 497 #define EMAC_PTP_FV2 0xFFC030B4 /* PTP Filter Value Register 2 */ 498 #define EMAC_PTP_FV3 0xFFC030B8 /* PTP Filter Value Register 3 */ 499 #define EMAC_PTP_ADDEND 0xFFC030BC /* PTP Addend for Frequency Compensation */ 500 #define EMAC_PTP_ACCR 0xFFC030C0 /* PTP Accumulator for Frequency Compensation */ 501 #define EMAC_PTP_OFFSET 0xFFC030C4 /* PTP Time Offset Register */ 502 #define EMAC_PTP_TIMELO 0xFFC030C8 /* PTP Precision Clock Time Low */ 503 #define EMAC_PTP_TIMEHI 0xFFC030CC /* PTP Precision Clock Time High */ 504 #define EMAC_PTP_RXSNAPLO 0xFFC030D0 /* PTP Receive Snapshot Register Low */ 505 #define EMAC_PTP_RXSNAPHI 0xFFC030D4 /* PTP Receive Snapshot Register High */ 506 #define EMAC_PTP_TXSNAPLO 0xFFC030D8 /* PTP Transmit Snapshot Register Low */ 507 #define EMAC_PTP_TXSNAPHI 0xFFC030DC /* PTP Transmit Snapshot Register High */ 508 #define EMAC_PTP_ALARMLO 0xFFC030E0 /* PTP Alarm time Low */ 509 #define EMAC_PTP_ALARMHI 0xFFC030E4 /* PTP Alarm time High */ 510 #define EMAC_PTP_ID_OFF 0xFFC030E8 /* PTP Capture ID offset register */ 511 #define EMAC_PTP_ID_SNAP 0xFFC030EC /* PTP Capture ID register */ 512 #define EMAC_PTP_PPS_STARTLO 0xFFC030F0 /* PPS Start Time Low */ 513 #define EMAC_PTP_PPS_STARTHI 0xFFC030F4 /* PPS Start Time High */ 514 #define EMAC_PTP_PPS_PERIOD 0xFFC030F8 /* PPS Count Register */ 515 516 /* ********************************************************** */ 517 /* SINGLE BIT MACRO PAIRS (bit mask and negated one) */ 518 /* and MULTI BIT READ MACROS */ 519 /* ********************************************************** */ 520 521 /* Bit masks for SDH_COMMAND */ 522 523 #define CMD_IDX 0x3f /* Command Index */ 524 #define CMD_RSP 0x40 /* Response */ 525 #define CMD_L_RSP 0x80 /* Long Response */ 526 #define CMD_INT_E 0x100 /* Command Interrupt */ 527 #define CMD_PEND_E 0x200 /* Command Pending */ 528 #define CMD_E 0x400 /* Command Enable */ 529 530 /* Bit masks for SDH_PWR_CTL */ 531 532 #define PWR_ON 0x3 /* Power On */ 533 #if 0 534 #define TBD 0x3c /* TBD */ 535 #endif 536 #define SD_CMD_OD 0x40 /* Open Drain Output */ 537 #define ROD_CTL 0x80 /* Rod Control */ 538 539 /* Bit masks for SDH_CLK_CTL */ 540 541 #define CLKDIV 0xff /* MC_CLK Divisor */ 542 #define CLK_E 0x100 /* MC_CLK Bus Clock Enable */ 543 #define PWR_SV_E 0x200 /* Power Save Enable */ 544 #define CLKDIV_BYPASS 0x400 /* Bypass Divisor */ 545 #define WIDE_BUS 0x800 /* Wide Bus Mode Enable */ 546 547 /* Bit masks for SDH_RESP_CMD */ 548 549 #define RESP_CMD 0x3f /* Response Command */ 550 551 /* Bit masks for SDH_DATA_CTL */ 552 553 #define DTX_E 0x1 /* Data Transfer Enable */ 554 #define DTX_DIR 0x2 /* Data Transfer Direction */ 555 #define DTX_MODE 0x4 /* Data Transfer Mode */ 556 #define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */ 557 #define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */ 558 559 /* Bit masks for SDH_STATUS */ 560 561 #define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */ 562 #define DAT_CRC_FAIL 0x2 /* Data CRC Fail */ 563 #define CMD_TIME_OUT 0x4 /* CMD Time Out */ 564 #define DAT_TIME_OUT 0x8 /* Data Time Out */ 565 #define TX_UNDERRUN 0x10 /* Transmit Underrun */ 566 #define RX_OVERRUN 0x20 /* Receive Overrun */ 567 #define CMD_RESP_END 0x40 /* CMD Response End */ 568 #define CMD_SENT 0x80 /* CMD Sent */ 569 #define DAT_END 0x100 /* Data End */ 570 #define START_BIT_ERR 0x200 /* Start Bit Error */ 571 #define DAT_BLK_END 0x400 /* Data Block End */ 572 #define CMD_ACT 0x800 /* CMD Active */ 573 #define TX_ACT 0x1000 /* Transmit Active */ 574 #define RX_ACT 0x2000 /* Receive Active */ 575 #define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */ 576 #define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */ 577 #define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */ 578 #define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */ 579 #define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */ 580 #define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */ 581 #define TX_DAT_RDY 0x100000 /* Transmit Data Available */ 582 #define RX_FIFO_RDY 0x200000 /* Receive Data Available */ 583 584 /* Bit masks for SDH_STATUS_CLR */ 585 586 #define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */ 587 #define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */ 588 #define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */ 589 #define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */ 590 #define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */ 591 #define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */ 592 #define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */ 593 #define CMD_SENT_STAT 0x80 /* CMD Sent Status */ 594 #define DAT_END_STAT 0x100 /* Data End Status */ 595 #define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */ 596 #define DAT_BLK_END_STAT 0x400 /* Data Block End Status */ 597 598 /* Bit masks for SDH_MASK0 */ 599 600 #define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */ 601 #define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */ 602 #define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */ 603 #define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */ 604 #define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */ 605 #define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */ 606 #define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */ 607 #define CMD_SENT_MASK 0x80 /* CMD Sent Mask */ 608 #define DAT_END_MASK 0x100 /* Data End Mask */ 609 #define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */ 610 #define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */ 611 #define CMD_ACT_MASK 0x800 /* CMD Active Mask */ 612 #define TX_ACT_MASK 0x1000 /* Transmit Active Mask */ 613 #define RX_ACT_MASK 0x2000 /* Receive Active Mask */ 614 #define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */ 615 #define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */ 616 #define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */ 617 #define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */ 618 #define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */ 619 #define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */ 620 #define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */ 621 #define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */ 622 623 /* Bit masks for SDH_FIFO_CNT */ 624 625 #define FIFO_COUNT 0x7fff /* FIFO Count */ 626 627 /* Bit masks for SDH_E_STATUS */ 628 629 #define SDIO_INT_DET 0x2 /* SDIO Int Detected */ 630 #define SD_CARD_DET 0x10 /* SD Card Detect */ 631 632 /* Bit masks for SDH_E_MASK */ 633 634 #define SDIO_MSK 0x2 /* Mask SDIO Int Detected */ 635 #define SCD_MSK 0x40 /* Mask Card Detect */ 636 637 /* Bit masks for SDH_CFG */ 638 639 #define CLKS_EN 0x1 /* Clocks Enable */ 640 #define SD4E 0x4 /* SDIO 4-Bit Enable */ 641 #define MWE 0x8 /* Moving Window Enable */ 642 #define SD_RST 0x10 /* SDMMC Reset */ 643 #define PUP_SDDAT 0x20 /* Pull-up SD_DAT */ 644 #define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */ 645 #define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */ 646 647 /* Bit masks for SDH_RD_WAIT_EN */ 648 649 #define RWR 0x1 /* Read Wait Request */ 650 651 #endif /* _DEF_BF518_H */ 652