1 /* 2 * File: include/asm-blackfin/mach-bf533/anomaly.h 3 * Bugs: Enter bugs at http://blackfin.uclinux.org/ 4 * 5 * Copyright (C) 2004-2009 Analog Devices Inc. 6 * Licensed under the GPL-2 or later. 7 */ 8 9 /* This file shoule be up to date with: 10 * - Revision E, 09/18/2008; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List 11 */ 12 13 #ifndef _MACH_ANOMALY_H_ 14 #define _MACH_ANOMALY_H_ 15 16 /* We do not support 0.1 or 0.2 silicon - sorry */ 17 #if __SILICON_REVISION__ < 3 18 # error will not work on BF533 silicon version 0.0, 0.1, or 0.2 19 #endif 20 21 #if defined(__ADSPBF531__) 22 # define ANOMALY_BF531 1 23 #else 24 # define ANOMALY_BF531 0 25 #endif 26 #if defined(__ADSPBF532__) 27 # define ANOMALY_BF532 1 28 #else 29 # define ANOMALY_BF532 0 30 #endif 31 #if defined(__ADSPBF533__) 32 # define ANOMALY_BF533 1 33 #else 34 # define ANOMALY_BF533 0 35 #endif 36 37 /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot 2 Not Supported */ 38 #define ANOMALY_05000074 (1) 39 /* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */ 40 #define ANOMALY_05000099 (__SILICON_REVISION__ < 5) 41 /* Watchpoint Status Register (WPSTAT) Bits Are Set on Every Corresponding Match */ 42 #define ANOMALY_05000105 (1) 43 /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ 44 #define ANOMALY_05000119 (1) 45 /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ 46 #define ANOMALY_05000122 (1) 47 /* Instruction DMA Can Cause Data Cache Fills to Fail (Boot Implications) */ 48 #define ANOMALY_05000158 (__SILICON_REVISION__ < 5) 49 /* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */ 50 #define ANOMALY_05000166 (1) 51 /* Turning Serial Ports on with External Frame Syncs */ 52 #define ANOMALY_05000167 (1) 53 /* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */ 54 #define ANOMALY_05000179 (__SILICON_REVISION__ < 5) 55 /* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */ 56 #define ANOMALY_05000180 (1) 57 /* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */ 58 #define ANOMALY_05000183 (__SILICON_REVISION__ < 4) 59 /* False Protection Exceptions */ 60 #define ANOMALY_05000189 (__SILICON_REVISION__ < 4) 61 /* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */ 62 #define ANOMALY_05000193 (__SILICON_REVISION__ < 4) 63 /* Restarting SPORT in Specific Modes May Cause Data Corruption */ 64 #define ANOMALY_05000194 (__SILICON_REVISION__ < 4) 65 /* Failing MMR Accesses When Stalled by Preceding Memory Read */ 66 #define ANOMALY_05000198 (__SILICON_REVISION__ < 5) 67 /* Current DMA Address Shows Wrong Value During Carry Fix */ 68 #define ANOMALY_05000199 (__SILICON_REVISION__ < 4) 69 /* SPORT TFS and DT Are Incorrectly Driven During Inactive Channels in Certain Conditions */ 70 #define ANOMALY_05000200 (__SILICON_REVISION__ < 5) 71 /* Receive Frame Sync Not Ignored During Active Frames in SPORT Multi-Channel Mode */ 72 #define ANOMALY_05000201 (__SILICON_REVISION__ < 4) 73 /* Possible Infinite Stall with Specific Dual-DAG Situation */ 74 #define ANOMALY_05000202 (__SILICON_REVISION__ < 5) 75 /* Specific Sequence That Can Cause DMA Error or DMA Stopping */ 76 #define ANOMALY_05000203 (__SILICON_REVISION__ < 4) 77 /* Incorrect data read with write-through cache and allocate cache lines on reads only mode */ 78 #define ANOMALY_05000204 (__SILICON_REVISION__ < 4 && ANOMALY_BF533) 79 /* Recovery from "Brown-Out" Condition */ 80 #define ANOMALY_05000207 (__SILICON_REVISION__ < 4) 81 /* VSTAT Status Bit in PLL_STAT Register Is Not Functional */ 82 #define ANOMALY_05000208 (1) 83 /* Speed Path in Computational Unit Affects Certain Instructions */ 84 #define ANOMALY_05000209 (__SILICON_REVISION__ < 4) 85 /* UART TX Interrupt Masked Erroneously */ 86 #define ANOMALY_05000215 (__SILICON_REVISION__ < 5) 87 /* NMI Event at Boot Time Results in Unpredictable State */ 88 #define ANOMALY_05000219 (1) 89 /* Incorrect Pulse-Width of UART Start Bit */ 90 #define ANOMALY_05000225 (__SILICON_REVISION__ < 5) 91 /* Scratchpad Memory Bank Reads May Return Incorrect Data */ 92 #define ANOMALY_05000227 (__SILICON_REVISION__ < 5) 93 /* SPI Slave Boot Mode Modifies Registers from Reset Value */ 94 #define ANOMALY_05000229 (1) 95 /* UART Receiver is Less Robust Against Baudrate Differences in Certain Conditions */ 96 #define ANOMALY_05000230 (__SILICON_REVISION__ < 5) 97 /* UART STB Bit Incorrectly Affects Receiver Setting */ 98 #define ANOMALY_05000231 (__SILICON_REVISION__ < 5) 99 /* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */ 100 #define ANOMALY_05000233 (__SILICON_REVISION__ < 6) 101 /* Incorrect Revision Number in DSPID Register */ 102 #define ANOMALY_05000234 (__SILICON_REVISION__ == 4) 103 /* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */ 104 #define ANOMALY_05000242 (__SILICON_REVISION__ < 5) 105 /* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */ 106 #define ANOMALY_05000244 (__SILICON_REVISION__ < 5) 107 /* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */ 108 #define ANOMALY_05000245 (1) 109 /* Data CPLBs Should Prevent Spurious Hardware Errors */ 110 #define ANOMALY_05000246 (__SILICON_REVISION__ < 5) 111 /* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */ 112 #define ANOMALY_05000250 (__SILICON_REVISION__ == 4) 113 /* Maximum External Clock Speed for Timers */ 114 #define ANOMALY_05000253 (__SILICON_REVISION__ < 5) 115 /* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */ 116 #define ANOMALY_05000254 (__SILICON_REVISION__ > 4) 117 /* Entering Hibernate State with RTC Seconds Interrupt Not Functional */ 118 #define ANOMALY_05000255 (__SILICON_REVISION__ < 5) 119 /* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */ 120 #define ANOMALY_05000257 (__SILICON_REVISION__ < 5) 121 /* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */ 122 #define ANOMALY_05000258 (__SILICON_REVISION__ < 5) 123 /* ICPLB_STATUS MMR Register May Be Corrupted */ 124 #define ANOMALY_05000260 (__SILICON_REVISION__ < 5) 125 /* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */ 126 #define ANOMALY_05000261 (__SILICON_REVISION__ < 5) 127 /* Stores To Data Cache May Be Lost */ 128 #define ANOMALY_05000262 (__SILICON_REVISION__ < 5) 129 /* Hardware Loop Corrupted When Taking an ICPLB Exception */ 130 #define ANOMALY_05000263 (__SILICON_REVISION__ < 5) 131 /* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */ 132 #define ANOMALY_05000264 (__SILICON_REVISION__ < 5) 133 /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ 134 #define ANOMALY_05000265 (1) 135 /* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */ 136 #define ANOMALY_05000269 (__SILICON_REVISION__ < 5) 137 /* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */ 138 #define ANOMALY_05000270 (__SILICON_REVISION__ < 5) 139 /* Spontaneous Reset of Internal Voltage Regulator */ 140 #define ANOMALY_05000271 (__SILICON_REVISION__ < 4) 141 /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ 142 #define ANOMALY_05000272 (1) 143 /* Writes to Synchronous SDRAM Memory May Be Lost */ 144 #define ANOMALY_05000273 (__SILICON_REVISION__ < 6) 145 /* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */ 146 #define ANOMALY_05000276 (1) 147 /* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */ 148 #define ANOMALY_05000277 (__SILICON_REVISION__ < 6) 149 /* Disabling Peripherals with DMA Running May Cause DMA System Instability */ 150 #define ANOMALY_05000278 (__SILICON_REVISION__ < 6) 151 /* False Hardware Error Exception When ISR Context Is Not Restored */ 152 #define ANOMALY_05000281 (__SILICON_REVISION__ < 6) 153 /* Memory DMA Corruption with 32-Bit Data and Traffic Control */ 154 #define ANOMALY_05000282 (__SILICON_REVISION__ < 6) 155 /* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */ 156 #define ANOMALY_05000283 (__SILICON_REVISION__ < 6) 157 /* SPORTs May Receive Bad Data If FIFOs Fill Up */ 158 #define ANOMALY_05000288 (__SILICON_REVISION__ < 6) 159 /* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */ 160 #define ANOMALY_05000301 (__SILICON_REVISION__ < 6) 161 /* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */ 162 #define ANOMALY_05000302 (__SILICON_REVISION__ < 5) 163 /* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */ 164 #define ANOMALY_05000305 (__SILICON_REVISION__ < 5) 165 /* New Feature: Additional PPI Frame Sync Sampling Options (Not Available On Older Silicon) */ 166 #define ANOMALY_05000306 (__SILICON_REVISION__ < 5) 167 /* SCKELOW Bit Does Not Maintain State Through Hibernate */ 168 #define ANOMALY_05000307 (1) 169 /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ 170 #define ANOMALY_05000310 (1) 171 /* Erroneous Flag (GPIO) Pin Operations under Specific Sequences */ 172 #define ANOMALY_05000311 (__SILICON_REVISION__ < 6) 173 /* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ 174 #define ANOMALY_05000312 (__SILICON_REVISION__ < 6) 175 /* PPI Is Level-Sensitive on First Transfer */ 176 #define ANOMALY_05000313 (__SILICON_REVISION__ < 6) 177 /* Killed System MMR Write Completes Erroneously On Next System MMR Access */ 178 #define ANOMALY_05000315 (__SILICON_REVISION__ < 6) 179 /* Internal Voltage Regulator Values of 1.05V, 1.10V and 1.15V Not Allowed for LQFP Packages */ 180 #define ANOMALY_05000319 ((ANOMALY_BF531 || ANOMALY_BF532) && __SILICON_REVISION__ < 6) 181 /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ 182 #define ANOMALY_05000357 (__SILICON_REVISION__ < 6) 183 /* UART Break Signal Issues */ 184 #define ANOMALY_05000363 (__SILICON_REVISION__ < 5) 185 /* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ 186 #define ANOMALY_05000366 (1) 187 /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ 188 #define ANOMALY_05000371 (__SILICON_REVISION__ < 6) 189 /* PPI Does Not Start Properly In Specific Mode */ 190 #define ANOMALY_05000400 (__SILICON_REVISION__ == 5) 191 /* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */ 192 #define ANOMALY_05000402 (__SILICON_REVISION__ == 5) 193 /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ 194 #define ANOMALY_05000403 (1) 195 /* Speculative Fetches Can Cause Undesired External FIFO Operations */ 196 #define ANOMALY_05000416 (1) 197 /* Multichannel SPORT Channel Misalignment Under Specific Configuration */ 198 #define ANOMALY_05000425 (1) 199 /* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */ 200 #define ANOMALY_05000426 (1) 201 /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ 202 #define ANOMALY_05000443 (1) 203 204 /* These anomalies have been "phased" out of analog.com anomaly sheets and are 205 * here to show running on older silicon just isn't feasible. 206 */ 207 208 /* Watchpoints (Hardware Breakpoints) are not supported */ 209 #define ANOMALY_05000067 (__SILICON_REVISION__ < 3) 210 /* Reserved bits in SYSCFG register not set at power on */ 211 #define ANOMALY_05000109 (__SILICON_REVISION__ < 3) 212 /* Trace Buffers may record discontinuities into emulation mode and/or exception, NMI, reset handlers */ 213 #define ANOMALY_05000116 (__SILICON_REVISION__ < 3) 214 /* DTEST_COMMAND initiated memory access may be incorrect if data cache or DMA is active */ 215 #define ANOMALY_05000123 (__SILICON_REVISION__ < 3) 216 /* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */ 217 #define ANOMALY_05000124 (__SILICON_REVISION__ < 3) 218 /* Erroneous exception when enabling cache */ 219 #define ANOMALY_05000125 (__SILICON_REVISION__ < 3) 220 /* SPI clock polarity and phase bits incorrect during booting */ 221 #define ANOMALY_05000126 (__SILICON_REVISION__ < 3) 222 /* DMEM_CONTROL is not set on Reset */ 223 #define ANOMALY_05000137 (__SILICON_REVISION__ < 3) 224 /* SPI boot will not complete if there is a zero fill block in the loader file */ 225 #define ANOMALY_05000138 (__SILICON_REVISION__ < 3) 226 /* Allowing the SPORT RX FIFO to fill will cause an overflow */ 227 #define ANOMALY_05000140 (__SILICON_REVISION__ < 3) 228 /* An Infinite Stall occurs with a particular sequence of consecutive dual dag events */ 229 #define ANOMALY_05000141 (__SILICON_REVISION__ < 3) 230 /* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */ 231 #define ANOMALY_05000142 (__SILICON_REVISION__ < 3) 232 /* A read from external memory may return a wrong value with data cache enabled */ 233 #define ANOMALY_05000143 (__SILICON_REVISION__ < 3) 234 /* DMA and TESTSET conflict when both are accessing external memory */ 235 #define ANOMALY_05000144 (__SILICON_REVISION__ < 3) 236 /* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */ 237 #define ANOMALY_05000145 (__SILICON_REVISION__ < 3) 238 /* MDMA may lose the first few words of a descriptor chain */ 239 #define ANOMALY_05000146 (__SILICON_REVISION__ < 3) 240 /* The source MDMA descriptor may stop with a DMA Error */ 241 #define ANOMALY_05000147 (__SILICON_REVISION__ < 3) 242 /* When booting from a 16-bit asynchronous memory device, the upper 8-bits of each word must be 0x00 */ 243 #define ANOMALY_05000148 (__SILICON_REVISION__ < 3) 244 /* Frame Delay in SPORT Multichannel Mode */ 245 #define ANOMALY_05000153 (__SILICON_REVISION__ < 3) 246 /* SPORT TFS signal is active in Multi-channel mode outside of valid channels */ 247 #define ANOMALY_05000154 (__SILICON_REVISION__ < 3) 248 /* Timer1 can not be used for PWMOUT mode when a certain PPI mode is in use */ 249 #define ANOMALY_05000155 (__SILICON_REVISION__ < 3) 250 /* A killed 32-bit System MMR write will lead to the next system MMR access thinking it should be 32-bit. */ 251 #define ANOMALY_05000157 (__SILICON_REVISION__ < 3) 252 /* SPORT transmit data is not gated by external frame sync in certain conditions */ 253 #define ANOMALY_05000163 (__SILICON_REVISION__ < 3) 254 /* SDRAM auto-refresh and subsequent Power Ups */ 255 #define ANOMALY_05000168 (__SILICON_REVISION__ < 3) 256 /* DATA CPLB page miss can result in lost write-through cache data writes */ 257 #define ANOMALY_05000169 (__SILICON_REVISION__ < 3) 258 /* DMA vs Core accesses to external memory */ 259 #define ANOMALY_05000173 (__SILICON_REVISION__ < 3) 260 /* Cache Fill Buffer Data lost */ 261 #define ANOMALY_05000174 (__SILICON_REVISION__ < 3) 262 /* Overlapping Sequencer and Memory Stalls */ 263 #define ANOMALY_05000175 (__SILICON_REVISION__ < 3) 264 /* Multiplication of (-1) by (-1) followed by an accumulator saturation */ 265 #define ANOMALY_05000176 (__SILICON_REVISION__ < 3) 266 /* Disabling the PPI resets the PPI configuration registers */ 267 #define ANOMALY_05000181 (__SILICON_REVISION__ < 3) 268 /* PPI TX Mode with 2 External Frame Syncs */ 269 #define ANOMALY_05000185 (__SILICON_REVISION__ < 3) 270 /* PPI does not invert the Driving PPICLK edge in Transmit Modes */ 271 #define ANOMALY_05000191 (__SILICON_REVISION__ < 3) 272 /* In PPI Transmit Modes with External Frame Syncs POLC */ 273 #define ANOMALY_05000192 (__SILICON_REVISION__ < 3) 274 /* Internal Voltage Regulator may not start up */ 275 #define ANOMALY_05000206 (__SILICON_REVISION__ < 3) 276 277 /* Anomalies that don't exist on this proc */ 278 #define ANOMALY_05000266 (0) 279 #define ANOMALY_05000323 (0) 280 #define ANOMALY_05000353 (1) 281 #define ANOMALY_05000380 (0) 282 #define ANOMALY_05000386 (1) 283 #define ANOMALY_05000412 (0) 284 #define ANOMALY_05000432 (0) 285 #define ANOMALY_05000435 (0) 286 #define ANOMALY_05000447 (0) 287 #define ANOMALY_05000448 (0) 288 289 #endif 290