1 /*
2 * File: arch/blackfin/mach-bf538/dma.c
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description: This file contains the simple DMA Implementation for Blackfin
8 *
9 * Modified:
10 * Copyright 2008 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29 #include <linux/module.h>
30
31 #include <asm/blackfin.h>
32 #include <asm/dma.h>
33
34 struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = {
35 (struct dma_register *) DMA0_NEXT_DESC_PTR,
36 (struct dma_register *) DMA1_NEXT_DESC_PTR,
37 (struct dma_register *) DMA2_NEXT_DESC_PTR,
38 (struct dma_register *) DMA3_NEXT_DESC_PTR,
39 (struct dma_register *) DMA4_NEXT_DESC_PTR,
40 (struct dma_register *) DMA5_NEXT_DESC_PTR,
41 (struct dma_register *) DMA6_NEXT_DESC_PTR,
42 (struct dma_register *) DMA7_NEXT_DESC_PTR,
43 (struct dma_register *) DMA8_NEXT_DESC_PTR,
44 (struct dma_register *) DMA9_NEXT_DESC_PTR,
45 (struct dma_register *) DMA10_NEXT_DESC_PTR,
46 (struct dma_register *) DMA11_NEXT_DESC_PTR,
47 (struct dma_register *) DMA12_NEXT_DESC_PTR,
48 (struct dma_register *) DMA13_NEXT_DESC_PTR,
49 (struct dma_register *) DMA14_NEXT_DESC_PTR,
50 (struct dma_register *) DMA15_NEXT_DESC_PTR,
51 (struct dma_register *) DMA16_NEXT_DESC_PTR,
52 (struct dma_register *) DMA17_NEXT_DESC_PTR,
53 (struct dma_register *) DMA18_NEXT_DESC_PTR,
54 (struct dma_register *) DMA19_NEXT_DESC_PTR,
55 (struct dma_register *) MDMA0_D0_NEXT_DESC_PTR,
56 (struct dma_register *) MDMA0_S0_NEXT_DESC_PTR,
57 (struct dma_register *) MDMA0_D1_NEXT_DESC_PTR,
58 (struct dma_register *) MDMA0_S1_NEXT_DESC_PTR,
59 (struct dma_register *) MDMA1_D0_NEXT_DESC_PTR,
60 (struct dma_register *) MDMA1_S0_NEXT_DESC_PTR,
61 (struct dma_register *) MDMA1_D1_NEXT_DESC_PTR,
62 (struct dma_register *) MDMA1_S1_NEXT_DESC_PTR,
63 };
64 EXPORT_SYMBOL(dma_io_base_addr);
65
channel2irq(unsigned int channel)66 int channel2irq(unsigned int channel)
67 {
68 int ret_irq = -1;
69
70 switch (channel) {
71 case CH_PPI:
72 ret_irq = IRQ_PPI;
73 break;
74
75 case CH_UART0_RX:
76 ret_irq = IRQ_UART0_RX;
77 break;
78
79 case CH_UART0_TX:
80 ret_irq = IRQ_UART0_TX;
81 break;
82
83 case CH_UART1_RX:
84 ret_irq = IRQ_UART1_RX;
85 break;
86
87 case CH_UART1_TX:
88 ret_irq = IRQ_UART1_TX;
89 break;
90
91 case CH_UART2_RX:
92 ret_irq = IRQ_UART2_RX;
93 break;
94
95 case CH_UART2_TX:
96 ret_irq = IRQ_UART2_TX;
97 break;
98
99 case CH_SPORT0_RX:
100 ret_irq = IRQ_SPORT0_RX;
101 break;
102
103 case CH_SPORT0_TX:
104 ret_irq = IRQ_SPORT0_TX;
105 break;
106
107 case CH_SPORT1_RX:
108 ret_irq = IRQ_SPORT1_RX;
109 break;
110
111 case CH_SPORT1_TX:
112 ret_irq = IRQ_SPORT1_TX;
113 break;
114
115 case CH_SPORT2_RX:
116 ret_irq = IRQ_SPORT2_RX;
117 break;
118
119 case CH_SPORT2_TX:
120 ret_irq = IRQ_SPORT2_TX;
121 break;
122
123 case CH_SPORT3_RX:
124 ret_irq = IRQ_SPORT3_RX;
125 break;
126
127 case CH_SPORT3_TX:
128 ret_irq = IRQ_SPORT3_TX;
129 break;
130
131 case CH_SPI0:
132 ret_irq = IRQ_SPI0;
133 break;
134
135 case CH_SPI1:
136 ret_irq = IRQ_SPI1;
137 break;
138
139 case CH_SPI2:
140 ret_irq = IRQ_SPI2;
141 break;
142
143 case CH_MEM_STREAM0_SRC:
144 case CH_MEM_STREAM0_DEST:
145 ret_irq = IRQ_MEM0_DMA0;
146 break;
147 case CH_MEM_STREAM1_SRC:
148 case CH_MEM_STREAM1_DEST:
149 ret_irq = IRQ_MEM0_DMA1;
150 break;
151 case CH_MEM_STREAM2_SRC:
152 case CH_MEM_STREAM2_DEST:
153 ret_irq = IRQ_MEM1_DMA0;
154 break;
155 case CH_MEM_STREAM3_SRC:
156 case CH_MEM_STREAM3_DEST:
157 ret_irq = IRQ_MEM1_DMA1;
158 break;
159 }
160 return ret_irq;
161 }
162