1 #include <linux/types.h>
2 #include <asm/delay.h>
3 #include <irq.h>
4 #include <hwregs/intr_vect.h>
5 #include <hwregs/intr_vect_defs.h>
6 #include <asm/tlbflush.h>
7 #include <asm/mmu_context.h>
8 #include <hwregs/asm/mmu_defs_asm.h>
9 #include <hwregs/supp_reg.h>
10 #include <asm/atomic.h>
11
12 #include <linux/err.h>
13 #include <linux/init.h>
14 #include <linux/timex.h>
15 #include <linux/sched.h>
16 #include <linux/kernel.h>
17 #include <linux/cpumask.h>
18 #include <linux/interrupt.h>
19 #include <linux/module.h>
20
21 #define IPI_SCHEDULE 1
22 #define IPI_CALL 2
23 #define IPI_FLUSH_TLB 4
24 #define IPI_BOOT 8
25
26 #define FLUSH_ALL (void*)0xffffffff
27
28 /* Vector of locks used for various atomic operations */
29 spinlock_t cris_atomic_locks[] = { [0 ... LOCK_COUNT - 1] = SPIN_LOCK_UNLOCKED};
30
31 /* CPU masks */
32 cpumask_t phys_cpu_present_map = CPU_MASK_NONE;
33 EXPORT_SYMBOL(phys_cpu_present_map);
34
35 /* Variables used during SMP boot */
36 volatile int cpu_now_booting = 0;
37 volatile struct thread_info *smp_init_current_idle_thread;
38
39 /* Variables used during IPI */
40 static DEFINE_SPINLOCK(call_lock);
41 static DEFINE_SPINLOCK(tlbstate_lock);
42
43 struct call_data_struct {
44 void (*func) (void *info);
45 void *info;
46 int wait;
47 };
48
49 static struct call_data_struct * call_data;
50
51 static struct mm_struct* flush_mm;
52 static struct vm_area_struct* flush_vma;
53 static unsigned long flush_addr;
54
55 extern int setup_irq(int, struct irqaction *);
56
57 /* Mode registers */
58 static unsigned long irq_regs[NR_CPUS] = {
59 regi_irq,
60 regi_irq2
61 };
62
63 static irqreturn_t crisv32_ipi_interrupt(int irq, void *dev_id);
64 static int send_ipi(int vector, int wait, cpumask_t cpu_mask);
65 static struct irqaction irq_ipi = {
66 .handler = crisv32_ipi_interrupt,
67 .flags = IRQF_DISABLED,
68 .mask = CPU_MASK_NONE,
69 .name = "ipi",
70 };
71
72 extern void cris_mmu_init(void);
73 extern void cris_timer_init(void);
74
75 /* SMP initialization */
smp_prepare_cpus(unsigned int max_cpus)76 void __init smp_prepare_cpus(unsigned int max_cpus)
77 {
78 int i;
79
80 /* From now on we can expect IPIs so set them up */
81 setup_irq(IPI_INTR_VECT, &irq_ipi);
82
83 /* Mark all possible CPUs as present */
84 for (i = 0; i < max_cpus; i++)
85 cpu_set(i, phys_cpu_present_map);
86 }
87
smp_prepare_boot_cpu(void)88 void __devinit smp_prepare_boot_cpu(void)
89 {
90 /* PGD pointer has moved after per_cpu initialization so
91 * update the MMU.
92 */
93 pgd_t **pgd;
94 pgd = (pgd_t**)&per_cpu(current_pgd, smp_processor_id());
95
96 SUPP_BANK_SEL(1);
97 SUPP_REG_WR(RW_MM_TLB_PGD, pgd);
98 SUPP_BANK_SEL(2);
99 SUPP_REG_WR(RW_MM_TLB_PGD, pgd);
100
101 cpu_set(0, cpu_online_map);
102 cpu_set(0, phys_cpu_present_map);
103 cpu_set(0, cpu_possible_map);
104 }
105
smp_cpus_done(unsigned int max_cpus)106 void __init smp_cpus_done(unsigned int max_cpus)
107 {
108 }
109
110 /* Bring one cpu online.*/
111 static int __init
smp_boot_one_cpu(int cpuid)112 smp_boot_one_cpu(int cpuid)
113 {
114 unsigned timeout;
115 struct task_struct *idle;
116 cpumask_t cpu_mask = CPU_MASK_NONE;
117
118 idle = fork_idle(cpuid);
119 if (IS_ERR(idle))
120 panic("SMP: fork failed for CPU:%d", cpuid);
121
122 task_thread_info(idle)->cpu = cpuid;
123
124 /* Information to the CPU that is about to boot */
125 smp_init_current_idle_thread = task_thread_info(idle);
126 cpu_now_booting = cpuid;
127
128 /* Kick it */
129 cpu_set(cpuid, cpu_online_map);
130 cpu_set(cpuid, cpu_mask);
131 send_ipi(IPI_BOOT, 0, cpu_mask);
132 cpu_clear(cpuid, cpu_online_map);
133
134 /* Wait for CPU to come online */
135 for (timeout = 0; timeout < 10000; timeout++) {
136 if(cpu_online(cpuid)) {
137 cpu_now_booting = 0;
138 smp_init_current_idle_thread = NULL;
139 return 0; /* CPU online */
140 }
141 udelay(100);
142 barrier();
143 }
144
145 put_task_struct(idle);
146 idle = NULL;
147
148 printk(KERN_CRIT "SMP: CPU:%d is stuck.\n", cpuid);
149 return -1;
150 }
151
152 /* Secondary CPUs starts using C here. Here we need to setup CPU
153 * specific stuff such as the local timer and the MMU. */
smp_callin(void)154 void __init smp_callin(void)
155 {
156 extern void cpu_idle(void);
157
158 int cpu = cpu_now_booting;
159 reg_intr_vect_rw_mask vect_mask = {0};
160
161 /* Initialise the idle task for this CPU */
162 atomic_inc(&init_mm.mm_count);
163 current->active_mm = &init_mm;
164
165 /* Set up MMU */
166 cris_mmu_init();
167 __flush_tlb_all();
168
169 /* Setup local timer. */
170 cris_timer_init();
171
172 /* Enable IRQ and idle */
173 REG_WR(intr_vect, irq_regs[cpu], rw_mask, vect_mask);
174 unmask_irq(IPI_INTR_VECT);
175 unmask_irq(TIMER0_INTR_VECT);
176 preempt_disable();
177 notify_cpu_starting(cpu);
178 local_irq_enable();
179
180 cpu_set(cpu, cpu_online_map);
181 cpu_idle();
182 }
183
184 /* Stop execution on this CPU.*/
stop_this_cpu(void * dummy)185 void stop_this_cpu(void* dummy)
186 {
187 local_irq_disable();
188 asm volatile("halt");
189 }
190
191 /* Other calls */
smp_send_stop(void)192 void smp_send_stop(void)
193 {
194 smp_call_function(stop_this_cpu, NULL, 0);
195 }
196
setup_profiling_timer(unsigned int multiplier)197 int setup_profiling_timer(unsigned int multiplier)
198 {
199 return -EINVAL;
200 }
201
202
203 /* cache_decay_ticks is used by the scheduler to decide if a process
204 * is "hot" on one CPU. A higher value means a higher penalty to move
205 * a process to another CPU. Our cache is rather small so we report
206 * 1 tick.
207 */
208 unsigned long cache_decay_ticks = 1;
209
__cpu_up(unsigned int cpu)210 int __cpuinit __cpu_up(unsigned int cpu)
211 {
212 smp_boot_one_cpu(cpu);
213 return cpu_online(cpu) ? 0 : -ENOSYS;
214 }
215
smp_send_reschedule(int cpu)216 void smp_send_reschedule(int cpu)
217 {
218 cpumask_t cpu_mask = CPU_MASK_NONE;
219 cpu_set(cpu, cpu_mask);
220 send_ipi(IPI_SCHEDULE, 0, cpu_mask);
221 }
222
223 /* TLB flushing
224 *
225 * Flush needs to be done on the local CPU and on any other CPU that
226 * may have the same mapping. The mm->cpu_vm_mask is used to keep track
227 * of which CPUs that a specific process has been executed on.
228 */
flush_tlb_common(struct mm_struct * mm,struct vm_area_struct * vma,unsigned long addr)229 void flush_tlb_common(struct mm_struct* mm, struct vm_area_struct* vma, unsigned long addr)
230 {
231 unsigned long flags;
232 cpumask_t cpu_mask;
233
234 spin_lock_irqsave(&tlbstate_lock, flags);
235 cpu_mask = (mm == FLUSH_ALL ? CPU_MASK_ALL : mm->cpu_vm_mask);
236 cpu_clear(smp_processor_id(), cpu_mask);
237 flush_mm = mm;
238 flush_vma = vma;
239 flush_addr = addr;
240 send_ipi(IPI_FLUSH_TLB, 1, cpu_mask);
241 spin_unlock_irqrestore(&tlbstate_lock, flags);
242 }
243
flush_tlb_all(void)244 void flush_tlb_all(void)
245 {
246 __flush_tlb_all();
247 flush_tlb_common(FLUSH_ALL, FLUSH_ALL, 0);
248 }
249
flush_tlb_mm(struct mm_struct * mm)250 void flush_tlb_mm(struct mm_struct *mm)
251 {
252 __flush_tlb_mm(mm);
253 flush_tlb_common(mm, FLUSH_ALL, 0);
254 /* No more mappings in other CPUs */
255 cpus_clear(mm->cpu_vm_mask);
256 cpu_set(smp_processor_id(), mm->cpu_vm_mask);
257 }
258
flush_tlb_page(struct vm_area_struct * vma,unsigned long addr)259 void flush_tlb_page(struct vm_area_struct *vma,
260 unsigned long addr)
261 {
262 __flush_tlb_page(vma, addr);
263 flush_tlb_common(vma->vm_mm, vma, addr);
264 }
265
266 /* Inter processor interrupts
267 *
268 * The IPIs are used for:
269 * * Force a schedule on a CPU
270 * * FLush TLB on other CPUs
271 * * Call a function on other CPUs
272 */
273
send_ipi(int vector,int wait,cpumask_t cpu_mask)274 int send_ipi(int vector, int wait, cpumask_t cpu_mask)
275 {
276 int i = 0;
277 reg_intr_vect_rw_ipi ipi = REG_RD(intr_vect, irq_regs[i], rw_ipi);
278 int ret = 0;
279
280 /* Calculate CPUs to send to. */
281 cpus_and(cpu_mask, cpu_mask, cpu_online_map);
282
283 /* Send the IPI. */
284 for_each_cpu_mask(i, cpu_mask)
285 {
286 ipi.vector |= vector;
287 REG_WR(intr_vect, irq_regs[i], rw_ipi, ipi);
288 }
289
290 /* Wait for IPI to finish on other CPUS */
291 if (wait) {
292 for_each_cpu_mask(i, cpu_mask) {
293 int j;
294 for (j = 0 ; j < 1000; j++) {
295 ipi = REG_RD(intr_vect, irq_regs[i], rw_ipi);
296 if (!ipi.vector)
297 break;
298 udelay(100);
299 }
300
301 /* Timeout? */
302 if (ipi.vector) {
303 printk("SMP call timeout from %d to %d\n", smp_processor_id(), i);
304 ret = -ETIMEDOUT;
305 dump_stack();
306 }
307 }
308 }
309 return ret;
310 }
311
312 /*
313 * You must not call this function with disabled interrupts or from a
314 * hardware interrupt handler or from a bottom half handler.
315 */
smp_call_function(void (* func)(void * info),void * info,int wait)316 int smp_call_function(void (*func)(void *info), void *info, int wait)
317 {
318 cpumask_t cpu_mask = CPU_MASK_ALL;
319 struct call_data_struct data;
320 int ret;
321
322 cpu_clear(smp_processor_id(), cpu_mask);
323
324 WARN_ON(irqs_disabled());
325
326 data.func = func;
327 data.info = info;
328 data.wait = wait;
329
330 spin_lock(&call_lock);
331 call_data = &data;
332 ret = send_ipi(IPI_CALL, wait, cpu_mask);
333 spin_unlock(&call_lock);
334
335 return ret;
336 }
337
crisv32_ipi_interrupt(int irq,void * dev_id)338 irqreturn_t crisv32_ipi_interrupt(int irq, void *dev_id)
339 {
340 void (*func) (void *info) = call_data->func;
341 void *info = call_data->info;
342 reg_intr_vect_rw_ipi ipi;
343
344 ipi = REG_RD(intr_vect, irq_regs[smp_processor_id()], rw_ipi);
345
346 if (ipi.vector & IPI_CALL) {
347 func(info);
348 }
349 if (ipi.vector & IPI_FLUSH_TLB) {
350 if (flush_mm == FLUSH_ALL)
351 __flush_tlb_all();
352 else if (flush_vma == FLUSH_ALL)
353 __flush_tlb_mm(flush_mm);
354 else
355 __flush_tlb_page(flush_vma, flush_addr);
356 }
357
358 ipi.vector = 0;
359 REG_WR(intr_vect, irq_regs[smp_processor_id()], rw_ipi, ipi);
360
361 return IRQ_HANDLED;
362 }
363
364