1 #ifndef __timer_defs_asm_h 2 #define __timer_defs_asm_h 3 4 /* 5 * This file is autogenerated from 6 * file: timer.r 7 * 8 * by ../../../tools/rdesc/bin/rdes2c -asm -outfile timer_defs_asm.h timer.r 9 * Any changes here will be lost. 10 * 11 * -*- buffer-read-only: t -*- 12 */ 13 14 #ifndef REG_FIELD 15 #define REG_FIELD( scope, reg, field, value ) \ 16 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) 17 #define REG_FIELD_X_( value, shift ) ((value) << shift) 18 #endif 19 20 #ifndef REG_STATE 21 #define REG_STATE( scope, reg, field, symbolic_value ) \ 22 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) 23 #define REG_STATE_X_( k, shift ) (k << shift) 24 #endif 25 26 #ifndef REG_MASK 27 #define REG_MASK( scope, reg, field ) \ 28 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) 29 #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) 30 #endif 31 32 #ifndef REG_LSB 33 #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb 34 #endif 35 36 #ifndef REG_BIT 37 #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit 38 #endif 39 40 #ifndef REG_ADDR 41 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) 42 #define REG_ADDR_X_( inst, offs ) ((inst) + offs) 43 #endif 44 45 #ifndef REG_ADDR_VECT 46 #define REG_ADDR_VECT( scope, inst, reg, index ) \ 47 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ 48 STRIDE_##scope##_##reg ) 49 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ 50 ((inst) + offs + (index) * stride) 51 #endif 52 53 /* Register rw_tmr0_div, scope timer, type rw */ 54 #define reg_timer_rw_tmr0_div_offset 0 55 56 /* Register r_tmr0_data, scope timer, type r */ 57 #define reg_timer_r_tmr0_data_offset 4 58 59 /* Register rw_tmr0_ctrl, scope timer, type rw */ 60 #define reg_timer_rw_tmr0_ctrl___op___lsb 0 61 #define reg_timer_rw_tmr0_ctrl___op___width 2 62 #define reg_timer_rw_tmr0_ctrl___freq___lsb 2 63 #define reg_timer_rw_tmr0_ctrl___freq___width 3 64 #define reg_timer_rw_tmr0_ctrl_offset 8 65 66 /* Register rw_tmr1_div, scope timer, type rw */ 67 #define reg_timer_rw_tmr1_div_offset 16 68 69 /* Register r_tmr1_data, scope timer, type r */ 70 #define reg_timer_r_tmr1_data_offset 20 71 72 /* Register rw_tmr1_ctrl, scope timer, type rw */ 73 #define reg_timer_rw_tmr1_ctrl___op___lsb 0 74 #define reg_timer_rw_tmr1_ctrl___op___width 2 75 #define reg_timer_rw_tmr1_ctrl___freq___lsb 2 76 #define reg_timer_rw_tmr1_ctrl___freq___width 3 77 #define reg_timer_rw_tmr1_ctrl_offset 24 78 79 /* Register rs_cnt_data, scope timer, type rs */ 80 #define reg_timer_rs_cnt_data___tmr___lsb 0 81 #define reg_timer_rs_cnt_data___tmr___width 24 82 #define reg_timer_rs_cnt_data___cnt___lsb 24 83 #define reg_timer_rs_cnt_data___cnt___width 8 84 #define reg_timer_rs_cnt_data_offset 32 85 86 /* Register r_cnt_data, scope timer, type r */ 87 #define reg_timer_r_cnt_data___tmr___lsb 0 88 #define reg_timer_r_cnt_data___tmr___width 24 89 #define reg_timer_r_cnt_data___cnt___lsb 24 90 #define reg_timer_r_cnt_data___cnt___width 8 91 #define reg_timer_r_cnt_data_offset 36 92 93 /* Register rw_cnt_cfg, scope timer, type rw */ 94 #define reg_timer_rw_cnt_cfg___clk___lsb 0 95 #define reg_timer_rw_cnt_cfg___clk___width 2 96 #define reg_timer_rw_cnt_cfg_offset 40 97 98 /* Register rw_trig, scope timer, type rw */ 99 #define reg_timer_rw_trig_offset 48 100 101 /* Register rw_trig_cfg, scope timer, type rw */ 102 #define reg_timer_rw_trig_cfg___tmr___lsb 0 103 #define reg_timer_rw_trig_cfg___tmr___width 2 104 #define reg_timer_rw_trig_cfg_offset 52 105 106 /* Register r_time, scope timer, type r */ 107 #define reg_timer_r_time_offset 56 108 109 /* Register rw_out, scope timer, type rw */ 110 #define reg_timer_rw_out___tmr___lsb 0 111 #define reg_timer_rw_out___tmr___width 2 112 #define reg_timer_rw_out_offset 60 113 114 /* Register rw_wd_ctrl, scope timer, type rw */ 115 #define reg_timer_rw_wd_ctrl___cnt___lsb 0 116 #define reg_timer_rw_wd_ctrl___cnt___width 8 117 #define reg_timer_rw_wd_ctrl___cmd___lsb 8 118 #define reg_timer_rw_wd_ctrl___cmd___width 1 119 #define reg_timer_rw_wd_ctrl___cmd___bit 8 120 #define reg_timer_rw_wd_ctrl___key___lsb 9 121 #define reg_timer_rw_wd_ctrl___key___width 7 122 #define reg_timer_rw_wd_ctrl_offset 64 123 124 /* Register r_wd_stat, scope timer, type r */ 125 #define reg_timer_r_wd_stat___cnt___lsb 0 126 #define reg_timer_r_wd_stat___cnt___width 8 127 #define reg_timer_r_wd_stat___cmd___lsb 8 128 #define reg_timer_r_wd_stat___cmd___width 1 129 #define reg_timer_r_wd_stat___cmd___bit 8 130 #define reg_timer_r_wd_stat_offset 68 131 132 /* Register rw_intr_mask, scope timer, type rw */ 133 #define reg_timer_rw_intr_mask___tmr0___lsb 0 134 #define reg_timer_rw_intr_mask___tmr0___width 1 135 #define reg_timer_rw_intr_mask___tmr0___bit 0 136 #define reg_timer_rw_intr_mask___tmr1___lsb 1 137 #define reg_timer_rw_intr_mask___tmr1___width 1 138 #define reg_timer_rw_intr_mask___tmr1___bit 1 139 #define reg_timer_rw_intr_mask___cnt___lsb 2 140 #define reg_timer_rw_intr_mask___cnt___width 1 141 #define reg_timer_rw_intr_mask___cnt___bit 2 142 #define reg_timer_rw_intr_mask___trig___lsb 3 143 #define reg_timer_rw_intr_mask___trig___width 1 144 #define reg_timer_rw_intr_mask___trig___bit 3 145 #define reg_timer_rw_intr_mask_offset 72 146 147 /* Register rw_ack_intr, scope timer, type rw */ 148 #define reg_timer_rw_ack_intr___tmr0___lsb 0 149 #define reg_timer_rw_ack_intr___tmr0___width 1 150 #define reg_timer_rw_ack_intr___tmr0___bit 0 151 #define reg_timer_rw_ack_intr___tmr1___lsb 1 152 #define reg_timer_rw_ack_intr___tmr1___width 1 153 #define reg_timer_rw_ack_intr___tmr1___bit 1 154 #define reg_timer_rw_ack_intr___cnt___lsb 2 155 #define reg_timer_rw_ack_intr___cnt___width 1 156 #define reg_timer_rw_ack_intr___cnt___bit 2 157 #define reg_timer_rw_ack_intr___trig___lsb 3 158 #define reg_timer_rw_ack_intr___trig___width 1 159 #define reg_timer_rw_ack_intr___trig___bit 3 160 #define reg_timer_rw_ack_intr_offset 76 161 162 /* Register r_intr, scope timer, type r */ 163 #define reg_timer_r_intr___tmr0___lsb 0 164 #define reg_timer_r_intr___tmr0___width 1 165 #define reg_timer_r_intr___tmr0___bit 0 166 #define reg_timer_r_intr___tmr1___lsb 1 167 #define reg_timer_r_intr___tmr1___width 1 168 #define reg_timer_r_intr___tmr1___bit 1 169 #define reg_timer_r_intr___cnt___lsb 2 170 #define reg_timer_r_intr___cnt___width 1 171 #define reg_timer_r_intr___cnt___bit 2 172 #define reg_timer_r_intr___trig___lsb 3 173 #define reg_timer_r_intr___trig___width 1 174 #define reg_timer_r_intr___trig___bit 3 175 #define reg_timer_r_intr_offset 80 176 177 /* Register r_masked_intr, scope timer, type r */ 178 #define reg_timer_r_masked_intr___tmr0___lsb 0 179 #define reg_timer_r_masked_intr___tmr0___width 1 180 #define reg_timer_r_masked_intr___tmr0___bit 0 181 #define reg_timer_r_masked_intr___tmr1___lsb 1 182 #define reg_timer_r_masked_intr___tmr1___width 1 183 #define reg_timer_r_masked_intr___tmr1___bit 1 184 #define reg_timer_r_masked_intr___cnt___lsb 2 185 #define reg_timer_r_masked_intr___cnt___width 1 186 #define reg_timer_r_masked_intr___cnt___bit 2 187 #define reg_timer_r_masked_intr___trig___lsb 3 188 #define reg_timer_r_masked_intr___trig___width 1 189 #define reg_timer_r_masked_intr___trig___bit 3 190 #define reg_timer_r_masked_intr_offset 84 191 192 /* Register rw_test, scope timer, type rw */ 193 #define reg_timer_rw_test___dis___lsb 0 194 #define reg_timer_rw_test___dis___width 1 195 #define reg_timer_rw_test___dis___bit 0 196 #define reg_timer_rw_test___en___lsb 1 197 #define reg_timer_rw_test___en___width 1 198 #define reg_timer_rw_test___en___bit 1 199 #define reg_timer_rw_test_offset 88 200 201 202 /* Constants */ 203 #define regk_timer_ext 0x00000001 204 #define regk_timer_f100 0x00000007 205 #define regk_timer_f29_493 0x00000004 206 #define regk_timer_f32 0x00000005 207 #define regk_timer_f32_768 0x00000006 208 #define regk_timer_f90 0x00000003 209 #define regk_timer_hold 0x00000001 210 #define regk_timer_ld 0x00000000 211 #define regk_timer_no 0x00000000 212 #define regk_timer_off 0x00000000 213 #define regk_timer_run 0x00000002 214 #define regk_timer_rw_cnt_cfg_default 0x00000000 215 #define regk_timer_rw_intr_mask_default 0x00000000 216 #define regk_timer_rw_out_default 0x00000000 217 #define regk_timer_rw_test_default 0x00000000 218 #define regk_timer_rw_tmr0_ctrl_default 0x00000000 219 #define regk_timer_rw_tmr1_ctrl_default 0x00000000 220 #define regk_timer_rw_trig_cfg_default 0x00000000 221 #define regk_timer_start 0x00000001 222 #define regk_timer_stop 0x00000000 223 #define regk_timer_time 0x00000001 224 #define regk_timer_tmr0 0x00000002 225 #define regk_timer_tmr1 0x00000003 226 #define regk_timer_vclk 0x00000002 227 #define regk_timer_yes 0x00000001 228 #endif /* __timer_defs_asm_h */ 229