1 /*
2 * linux/arch/h8300/kernel/timer/tpu.c
3 *
4 * Yoshinori Sato <ysato@users.sourceforge.jp>
5 *
6 * TPU Timer Handler
7 *
8 */
9
10 #include <linux/config.h>
11 #include <linux/errno.h>
12 #include <linux/sched.h>
13 #include <linux/kernel.h>
14 #include <linux/param.h>
15 #include <linux/string.h>
16 #include <linux/mm.h>
17 #include <linux/interrupt.h>
18 #include <linux/init.h>
19 #include <linux/timex.h>
20
21 #include <asm/segment.h>
22 #include <asm/io.h>
23 #include <asm/irq.h>
24 #include <asm/regs267x.h>
25
26 /* TPU */
27 #if CONFIG_H8300_TPU_CH == 0
28 #define TPUBASE 0xffffd0
29 #define TPUIRQ 40
30 #elif CONFIG_H8300_TPU_CH == 1
31 #define TPUBASE 0xffffe0
32 #define TPUIRQ 48
33 #elif CONFIG_H8300_TPU_CH == 2
34 #define TPUBASE 0xfffff0
35 #define TPUIRQ 52
36 #elif CONFIG_H8300_TPU_CH == 3
37 #define TPUBASE 0xfffe80
38 #define TPUIRQ 56
39 #elif CONFIG_H8300_TPU_CH == 4
40 #define TPUBASE 0xfffe90
41 #define TPUIRQ 64
42 #else
43 #error Unknown timer channel.
44 #endif
45
46 #define _TCR 0
47 #define _TMDR 1
48 #define _TIOR 2
49 #define _TIER 4
50 #define _TSR 5
51 #define _TCNT 6
52 #define _GRA 8
53 #define _GRB 10
54
55 #define CCLR0 0x20
56
timer_interrupt(int irq,void * dev_id)57 static irqreturn_t timer_interrupt(int irq, void *dev_id)
58 {
59 h8300_timer_tick();
60 ctrl_bclr(0, TPUBASE + _TSR);
61 return IRQ_HANDLED;
62 }
63
64 static struct irqaction tpu_irq = {
65 .name = "tpu",
66 .handler = timer_interrupt,
67 .flags = IRQF_DISABLED | IRQF_TIMER,
68 .mask = CPU_MASK_NONE,
69 };
70
71 const static int __initdata divide_rate[] = {
72 #if CONFIG_H8300_TPU_CH == 0
73 1,4,16,64,0,0,0,0,
74 #elif (CONFIG_H8300_TPU_CH == 1) || (CONFIG_H8300_TPU_CH == 5)
75 1,4,16,64,0,0,256,0,
76 #elif (CONFIG_H8300_TPU_CH == 2) || (CONFIG_H8300_TPU_CH == 4)
77 1,4,16,64,0,0,0,1024,
78 #elif CONFIG_H8300_TPU_CH == 3
79 1,4,16,64,0,1024,256,4096,
80 #endif
81 };
82
h8300_timer_setup(void)83 void __init h8300_timer_setup(void)
84 {
85 unsigned int cnt;
86 unsigned int div;
87
88 calc_param(cnt, div, divide_rate, 0x10000);
89
90 setup_irq(TPUIRQ, &tpu_irq);
91
92 /* TPU module enabled */
93 ctrl_bclr(3, MSTPCRH);
94
95 ctrl_outb(0, TSTR);
96 ctrl_outb(CCLR0 | div, TPUBASE + _TCR);
97 ctrl_outb(0, TPUBASE + _TMDR);
98 ctrl_outw(0, TPUBASE + _TIOR);
99 ctrl_outb(0x01, TPUBASE + _TIER);
100 ctrl_outw(cnt, TPUBASE + _GRA);
101 ctrl_bset(CONFIG_H8300_TPU_CH, TSTR);
102 }
103