1 /*
2 * linux/arch/m32r/platforms/mappi/setup.c
3 *
4 * Setup routines for Renesas MAPPI Board
5 *
6 * Copyright (c) 2001-2005 Hiroyuki Kondo, Hirokazu Takata,
7 * Hitoshi Yamamoto
8 */
9
10 #include <linux/irq.h>
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/platform_device.h>
14
15 #include <asm/system.h>
16 #include <asm/m32r.h>
17 #include <asm/io.h>
18
19 #define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
20
21 icu_data_t icu_data[NR_IRQS];
22
disable_mappi_irq(unsigned int irq)23 static void disable_mappi_irq(unsigned int irq)
24 {
25 unsigned long port, data;
26
27 port = irq2port(irq);
28 data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
29 outl(data, port);
30 }
31
enable_mappi_irq(unsigned int irq)32 static void enable_mappi_irq(unsigned int irq)
33 {
34 unsigned long port, data;
35
36 port = irq2port(irq);
37 data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
38 outl(data, port);
39 }
40
mask_and_ack_mappi(unsigned int irq)41 static void mask_and_ack_mappi(unsigned int irq)
42 {
43 disable_mappi_irq(irq);
44 }
45
end_mappi_irq(unsigned int irq)46 static void end_mappi_irq(unsigned int irq)
47 {
48 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
49 enable_mappi_irq(irq);
50 }
51
startup_mappi_irq(unsigned int irq)52 static unsigned int startup_mappi_irq(unsigned int irq)
53 {
54 enable_mappi_irq(irq);
55 return (0);
56 }
57
shutdown_mappi_irq(unsigned int irq)58 static void shutdown_mappi_irq(unsigned int irq)
59 {
60 unsigned long port;
61
62 port = irq2port(irq);
63 outl(M32R_ICUCR_ILEVEL7, port);
64 }
65
66 static struct hw_interrupt_type mappi_irq_type =
67 {
68 .typename = "MAPPI-IRQ",
69 .startup = startup_mappi_irq,
70 .shutdown = shutdown_mappi_irq,
71 .enable = enable_mappi_irq,
72 .disable = disable_mappi_irq,
73 .ack = mask_and_ack_mappi,
74 .end = end_mappi_irq
75 };
76
init_IRQ(void)77 void __init init_IRQ(void)
78 {
79 static int once = 0;
80
81 if (once)
82 return;
83 else
84 once++;
85
86 #ifdef CONFIG_NE2000
87 /* INT0 : LAN controller (RTL8019AS) */
88 irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED;
89 irq_desc[M32R_IRQ_INT0].chip = &mappi_irq_type;
90 irq_desc[M32R_IRQ_INT0].action = NULL;
91 irq_desc[M32R_IRQ_INT0].depth = 1;
92 icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
93 disable_mappi_irq(M32R_IRQ_INT0);
94 #endif /* CONFIG_M32R_NE2000 */
95
96 /* MFT2 : system timer */
97 irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;
98 irq_desc[M32R_IRQ_MFT2].chip = &mappi_irq_type;
99 irq_desc[M32R_IRQ_MFT2].action = NULL;
100 irq_desc[M32R_IRQ_MFT2].depth = 1;
101 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
102 disable_mappi_irq(M32R_IRQ_MFT2);
103
104 #ifdef CONFIG_SERIAL_M32R_SIO
105 /* SIO0_R : uart receive data */
106 irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;
107 irq_desc[M32R_IRQ_SIO0_R].chip = &mappi_irq_type;
108 irq_desc[M32R_IRQ_SIO0_R].action = NULL;
109 irq_desc[M32R_IRQ_SIO0_R].depth = 1;
110 icu_data[M32R_IRQ_SIO0_R].icucr = 0;
111 disable_mappi_irq(M32R_IRQ_SIO0_R);
112
113 /* SIO0_S : uart send data */
114 irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;
115 irq_desc[M32R_IRQ_SIO0_S].chip = &mappi_irq_type;
116 irq_desc[M32R_IRQ_SIO0_S].action = NULL;
117 irq_desc[M32R_IRQ_SIO0_S].depth = 1;
118 icu_data[M32R_IRQ_SIO0_S].icucr = 0;
119 disable_mappi_irq(M32R_IRQ_SIO0_S);
120
121 /* SIO1_R : uart receive data */
122 irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED;
123 irq_desc[M32R_IRQ_SIO1_R].chip = &mappi_irq_type;
124 irq_desc[M32R_IRQ_SIO1_R].action = NULL;
125 irq_desc[M32R_IRQ_SIO1_R].depth = 1;
126 icu_data[M32R_IRQ_SIO1_R].icucr = 0;
127 disable_mappi_irq(M32R_IRQ_SIO1_R);
128
129 /* SIO1_S : uart send data */
130 irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED;
131 irq_desc[M32R_IRQ_SIO1_S].chip = &mappi_irq_type;
132 irq_desc[M32R_IRQ_SIO1_S].action = NULL;
133 irq_desc[M32R_IRQ_SIO1_S].depth = 1;
134 icu_data[M32R_IRQ_SIO1_S].icucr = 0;
135 disable_mappi_irq(M32R_IRQ_SIO1_S);
136 #endif /* CONFIG_SERIAL_M32R_SIO */
137
138 #if defined(CONFIG_M32R_PCC)
139 /* INT1 : pccard0 interrupt */
140 irq_desc[M32R_IRQ_INT1].status = IRQ_DISABLED;
141 irq_desc[M32R_IRQ_INT1].chip = &mappi_irq_type;
142 irq_desc[M32R_IRQ_INT1].action = NULL;
143 irq_desc[M32R_IRQ_INT1].depth = 1;
144 icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00;
145 disable_mappi_irq(M32R_IRQ_INT1);
146
147 /* INT2 : pccard1 interrupt */
148 irq_desc[M32R_IRQ_INT2].status = IRQ_DISABLED;
149 irq_desc[M32R_IRQ_INT2].chip = &mappi_irq_type;
150 irq_desc[M32R_IRQ_INT2].action = NULL;
151 irq_desc[M32R_IRQ_INT2].depth = 1;
152 icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00;
153 disable_mappi_irq(M32R_IRQ_INT2);
154 #endif /* CONFIG_M32RPCC */
155 }
156
157 #if defined(CONFIG_FB_S1D13XXX)
158
159 #include <video/s1d13xxxfb.h>
160 #include <asm/s1d13806.h>
161
162 static struct s1d13xxxfb_pdata s1d13xxxfb_data = {
163 .initregs = s1d13xxxfb_initregs,
164 .initregssize = ARRAY_SIZE(s1d13xxxfb_initregs),
165 .platform_init_video = NULL,
166 #ifdef CONFIG_PM
167 .platform_suspend_video = NULL,
168 .platform_resume_video = NULL,
169 #endif
170 };
171
172 static struct resource s1d13xxxfb_resources[] = {
173 [0] = {
174 .start = 0x10200000UL,
175 .end = 0x1033FFFFUL,
176 .flags = IORESOURCE_MEM,
177 },
178 [1] = {
179 .start = 0x10000000UL,
180 .end = 0x100001FFUL,
181 .flags = IORESOURCE_MEM,
182 }
183 };
184
185 static struct platform_device s1d13xxxfb_device = {
186 .name = S1D_DEVICENAME,
187 .id = 0,
188 .dev = {
189 .platform_data = &s1d13xxxfb_data,
190 },
191 .num_resources = ARRAY_SIZE(s1d13xxxfb_resources),
192 .resource = s1d13xxxfb_resources,
193 };
194
platform_init(void)195 static int __init platform_init(void)
196 {
197 platform_device_register(&s1d13xxxfb_device);
198 return 0;
199 }
200 arch_initcall(platform_init);
201 #endif
202