1/*****************************************************************************/ 2 3/* 4 * head.S -- common startup code for ColdFire CPUs. 5 * 6 * (C) Copyright 1999-2006, Greg Ungerer <gerg@snapgear.com>. 7 */ 8 9/*****************************************************************************/ 10 11#include <linux/sys.h> 12#include <linux/linkage.h> 13#include <linux/init.h> 14#include <asm/asm-offsets.h> 15#include <asm/coldfire.h> 16#include <asm/mcfcache.h> 17#include <asm/mcfsim.h> 18 19/*****************************************************************************/ 20 21/* 22 * If we don't have a fixed memory size, then lets build in code 23 * to auto detect the DRAM size. Obviously this is the prefered 24 * method, and should work for most boards. It won't work for those 25 * that do not have their RAM starting at address 0, and it only 26 * works on SDRAM (not boards fitted with SRAM). 27 */ 28#if CONFIG_RAMSIZE != 0 29.macro GET_MEM_SIZE 30 movel #CONFIG_RAMSIZE,%d0 /* hard coded memory size */ 31.endm 32 33#elif defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \ 34 defined(CONFIG_M5249) || defined(CONFIG_M527x) || \ 35 defined(CONFIG_M528x) || defined(CONFIG_M5307) || \ 36 defined(CONFIG_M5407) 37/* 38 * Not all these devices have exactly the same DRAM controller, 39 * but the DCMR register is virtually identical - give or take 40 * a couple of bits. The only exception is the 5272 devices, their 41 * DRAM controller is quite different. 42 */ 43.macro GET_MEM_SIZE 44 movel MCF_MBAR+MCFSIM_DMR0,%d0 /* get mask for 1st bank */ 45 btst #0,%d0 /* check if region enabled */ 46 beq 1f 47 andl #0xfffc0000,%d0 48 beq 1f 49 addl #0x00040000,%d0 /* convert mask to size */ 501: 51 movel MCF_MBAR+MCFSIM_DMR1,%d1 /* get mask for 2nd bank */ 52 btst #0,%d1 /* check if region enabled */ 53 beq 2f 54 andl #0xfffc0000, %d1 55 beq 2f 56 addl #0x00040000,%d1 57 addl %d1,%d0 /* total mem size in d0 */ 582: 59.endm 60 61#elif defined(CONFIG_M5272) 62.macro GET_MEM_SIZE 63 movel MCF_MBAR+MCFSIM_CSOR7,%d0 /* get SDRAM address mask */ 64 andil #0xfffff000,%d0 /* mask out chip select options */ 65 negl %d0 /* negate bits */ 66.endm 67 68#elif defined(CONFIG_M520x) 69.macro GET_MEM_SIZE 70 clrl %d0 71 movel MCF_MBAR+MCFSIM_SDCS0, %d2 /* Get SDRAM chip select 0 config */ 72 andl #0x1f, %d2 /* Get only the chip select size */ 73 beq 3f /* Check if it is enabled */ 74 addql #1, %d2 /* Form exponent */ 75 moveql #1, %d0 76 lsll %d2, %d0 /* 2 ^ exponent */ 773: 78 movel MCF_MBAR+MCFSIM_SDCS1, %d2 /* Get SDRAM chip select 1 config */ 79 andl #0x1f, %d2 /* Get only the chip select size */ 80 beq 4f /* Check if it is enabled */ 81 addql #1, %d2 /* Form exponent */ 82 moveql #1, %d1 83 lsll %d2, %d1 /* 2 ^ exponent */ 84 addl %d1, %d0 /* Total size of SDRAM in d0 */ 854: 86.endm 87 88#else 89#error "ERROR: I don't know how to probe your boards memory size?" 90#endif 91 92/*****************************************************************************/ 93 94/* 95 * Boards and platforms can do specific early hardware setup if 96 * they need to. Most don't need this, define away if not required. 97 */ 98#ifndef PLATFORM_SETUP 99#define PLATFORM_SETUP 100#endif 101 102/*****************************************************************************/ 103 104.global _start 105.global _rambase 106.global _ramvec 107.global _ramstart 108.global _ramend 109 110/*****************************************************************************/ 111 112.data 113 114/* 115 * During startup we store away the RAM setup. These are not in the 116 * bss, since their values are determined and written before the bss 117 * has been cleared. 118 */ 119_rambase: 120.long 0 121_ramvec: 122.long 0 123_ramstart: 124.long 0 125_ramend: 126.long 0 127 128/*****************************************************************************/ 129 130__HEAD 131 132/* 133 * This is the codes first entry point. This is where it all 134 * begins... 135 */ 136 137_start: 138 nop /* filler */ 139 movew #0x2700, %sr /* no interrupts */ 140 141 /* 142 * Do any platform or board specific setup now. Most boards 143 * don't need anything. Those exceptions are define this in 144 * their board specific includes. 145 */ 146 PLATFORM_SETUP 147 148 /* 149 * Create basic memory configuration. Set VBR accordingly, 150 * and size memory. 151 */ 152 movel #CONFIG_VECTORBASE,%a7 153 movec %a7,%VBR /* set vectors addr */ 154 movel %a7,_ramvec 155 156 movel #CONFIG_RAMBASE,%a7 /* mark the base of RAM */ 157 movel %a7,_rambase 158 159 GET_MEM_SIZE /* macro code determines size */ 160 addl %a7,%d0 161 movel %d0,_ramend /* set end ram addr */ 162 163 /* 164 * Now that we know what the memory is, lets enable cache 165 * and get things moving. This is Coldfire CPU specific. 166 */ 167 CACHE_ENABLE /* enable CPU cache */ 168 169 170#ifdef CONFIG_ROMFS_FS 171 /* 172 * Move ROM filesystem above bss :-) 173 */ 174 lea _sbss,%a0 /* get start of bss */ 175 lea _ebss,%a1 /* set up destination */ 176 movel %a0,%a2 /* copy of bss start */ 177 178 movel 8(%a0),%d0 /* get size of ROMFS */ 179 addql #8,%d0 /* allow for rounding */ 180 andl #0xfffffffc, %d0 /* whole words */ 181 182 addl %d0,%a0 /* copy from end */ 183 addl %d0,%a1 /* copy from end */ 184 movel %a1,_ramstart /* set start of ram */ 185 186_copy_romfs: 187 movel -(%a0),%d0 /* copy dword */ 188 movel %d0,-(%a1) 189 cmpl %a0,%a2 /* check if at end */ 190 bne _copy_romfs 191 192#else /* CONFIG_ROMFS_FS */ 193 lea _ebss,%a1 194 movel %a1,_ramstart 195#endif /* CONFIG_ROMFS_FS */ 196 197 198 /* 199 * Zero out the bss region. 200 */ 201 lea _sbss,%a0 /* get start of bss */ 202 lea _ebss,%a1 /* get end of bss */ 203 clrl %d0 /* set value */ 204_clear_bss: 205 movel %d0,(%a0)+ /* clear each word */ 206 cmpl %a0,%a1 /* check if at end */ 207 bne _clear_bss 208 209 /* 210 * Load the current task pointer and stack. 211 */ 212 lea init_thread_union,%a0 213 lea THREAD_SIZE(%a0),%sp 214 215 /* 216 * Assember start up done, start code proper. 217 */ 218 jsr start_kernel /* start Linux kernel */ 219 220_exit: 221 jmp _exit /* should never get here */ 222 223/*****************************************************************************/ 224