1 /***************************************************************************/
2
3 /*
4 * timers.c -- generic ColdFire hardware timer support.
5 *
6 * Copyright (C) 1999-2008, Greg Ungerer <gerg@snapgear.com>
7 */
8
9 /***************************************************************************/
10
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/sched.h>
14 #include <linux/interrupt.h>
15 #include <linux/irq.h>
16 #include <linux/profile.h>
17 #include <linux/clocksource.h>
18 #include <asm/io.h>
19 #include <asm/traps.h>
20 #include <asm/machdep.h>
21 #include <asm/coldfire.h>
22 #include <asm/mcftimer.h>
23 #include <asm/mcfsim.h>
24
25 /***************************************************************************/
26
27 /*
28 * By default use timer1 as the system clock timer.
29 */
30 #define FREQ (MCF_BUSCLK / 16)
31 #define TA(a) (MCF_MBAR + MCFTIMER_BASE1 + (a))
32
33 /*
34 * Default the timer and vector to use for ColdFire. Some ColdFire
35 * CPU's and some boards may want different. Their sub-architecture
36 * startup code (in config.c) can change these if they want.
37 */
38 unsigned int mcf_timervector = 29;
39 unsigned int mcf_profilevector = 31;
40 unsigned int mcf_timerlevel = 5;
41
42 /*
43 * These provide the underlying interrupt vector support.
44 * Unfortunately it is a little different on each ColdFire.
45 */
46 extern void mcf_settimericr(int timer, int level);
47 void coldfire_profile_init(void);
48
49 #if defined(CONFIG_M532x)
50 #define __raw_readtrr __raw_readl
51 #define __raw_writetrr __raw_writel
52 #else
53 #define __raw_readtrr __raw_readw
54 #define __raw_writetrr __raw_writew
55 #endif
56
57 static u32 mcftmr_cycles_per_jiffy;
58 static u32 mcftmr_cnt;
59
60 /***************************************************************************/
61
mcftmr_tick(int irq,void * dummy)62 static irqreturn_t mcftmr_tick(int irq, void *dummy)
63 {
64 /* Reset the ColdFire timer */
65 __raw_writeb(MCFTIMER_TER_CAP | MCFTIMER_TER_REF, TA(MCFTIMER_TER));
66
67 mcftmr_cnt += mcftmr_cycles_per_jiffy;
68 return arch_timer_interrupt(irq, dummy);
69 }
70
71 /***************************************************************************/
72
73 static struct irqaction mcftmr_timer_irq = {
74 .name = "timer",
75 .flags = IRQF_DISABLED | IRQF_TIMER,
76 .handler = mcftmr_tick,
77 };
78
79 /***************************************************************************/
80
mcftmr_read_clk(void)81 static cycle_t mcftmr_read_clk(void)
82 {
83 unsigned long flags;
84 u32 cycles;
85 u16 tcn;
86
87 local_irq_save(flags);
88 tcn = __raw_readw(TA(MCFTIMER_TCN));
89 cycles = mcftmr_cnt;
90 local_irq_restore(flags);
91
92 return cycles + tcn;
93 }
94
95 /***************************************************************************/
96
97 static struct clocksource mcftmr_clk = {
98 .name = "tmr",
99 .rating = 250,
100 .read = mcftmr_read_clk,
101 .shift = 20,
102 .mask = CLOCKSOURCE_MASK(32),
103 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
104 };
105
106 /***************************************************************************/
107
hw_timer_init(void)108 void hw_timer_init(void)
109 {
110 setup_irq(mcf_timervector, &mcftmr_timer_irq);
111
112 __raw_writew(MCFTIMER_TMR_DISABLE, TA(MCFTIMER_TMR));
113 mcftmr_cycles_per_jiffy = FREQ / HZ;
114 /*
115 * The coldfire timer runs from 0 to TRR included, then 0
116 * again and so on. It counts thus actually TRR + 1 steps
117 * for 1 tick, not TRR. So if you want n cycles,
118 * initialize TRR with n - 1.
119 */
120 __raw_writetrr(mcftmr_cycles_per_jiffy - 1, TA(MCFTIMER_TRR));
121 __raw_writew(MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 |
122 MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE, TA(MCFTIMER_TMR));
123
124 mcftmr_clk.mult = clocksource_hz2mult(FREQ, mcftmr_clk.shift);
125 clocksource_register(&mcftmr_clk);
126
127 mcf_settimericr(1, mcf_timerlevel);
128
129 #ifdef CONFIG_HIGHPROFILE
130 coldfire_profile_init();
131 #endif
132 }
133
134 /***************************************************************************/
135 #ifdef CONFIG_HIGHPROFILE
136 /***************************************************************************/
137
138 /*
139 * By default use timer2 as the profiler clock timer.
140 */
141 #define PA(a) (MCF_MBAR + MCFTIMER_BASE2 + (a))
142
143 /*
144 * Choose a reasonably fast profile timer. Make it an odd value to
145 * try and get good coverage of kernel operations.
146 */
147 #define PROFILEHZ 1013
148
149 /*
150 * Use the other timer to provide high accuracy profiling info.
151 */
coldfire_profile_tick(int irq,void * dummy)152 irqreturn_t coldfire_profile_tick(int irq, void *dummy)
153 {
154 /* Reset ColdFire timer2 */
155 __raw_writeb(MCFTIMER_TER_CAP | MCFTIMER_TER_REF, PA(MCFTIMER_TER));
156 if (current->pid)
157 profile_tick(CPU_PROFILING);
158 return IRQ_HANDLED;
159 }
160
161 /***************************************************************************/
162
163 static struct irqaction coldfire_profile_irq = {
164 .name = "profile timer",
165 .flags = IRQF_DISABLED | IRQF_TIMER,
166 .handler = coldfire_profile_tick,
167 };
168
coldfire_profile_init(void)169 void coldfire_profile_init(void)
170 {
171 printk(KERN_INFO "PROFILE: lodging TIMER2 @ %dHz as profile timer\n",
172 PROFILEHZ);
173
174 setup_irq(mcf_profilevector, &coldfire_profile_irq);
175
176 /* Set up TIMER 2 as high speed profile clock */
177 __raw_writew(MCFTIMER_TMR_DISABLE, PA(MCFTIMER_TMR));
178
179 __raw_writetrr(((MCF_BUSCLK / 16) / PROFILEHZ), PA(MCFTIMER_TRR));
180 __raw_writew(MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 |
181 MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE, PA(MCFTIMER_TMR));
182
183 mcf_settimericr(2, 7);
184 }
185
186 /***************************************************************************/
187 #endif /* CONFIG_HIGHPROFILE */
188 /***************************************************************************/
189