1 #ifndef EXCITE_FPGA_H_INCLUDED 2 #define EXCITE_FPGA_H_INCLUDED 3 4 5 /** 6 * Address alignment of the individual FPGA bytes. 7 * The address arrangement of the individual bytes of the FPGA is two 8 * byte aligned at the embedded MK2 platform. 9 */ 10 #ifdef EXCITE_CCI_FPGA_MK2 11 typedef unsigned char excite_cci_fpga_align_t __attribute__ ((aligned(2))); 12 #else 13 typedef unsigned char excite_cci_fpga_align_t; 14 #endif 15 16 17 /** 18 * Size of Dual Ported RAM. 19 */ 20 #define EXCITE_DPR_SIZE 263 21 22 23 /** 24 * Size of Reserved Status Fields in Dual Ported RAM. 25 */ 26 #define EXCITE_DPR_STATUS_SIZE 7 27 28 29 30 /** 31 * FPGA. 32 * Hardware register layout of the FPGA interface. The FPGA must accessed 33 * byte wise solely. 34 * @see EXCITE_CCI_DPR_MK2 35 */ 36 typedef struct excite_fpga { 37 38 /** 39 * Dual Ported RAM. 40 */ 41 excite_cci_fpga_align_t dpr[EXCITE_DPR_SIZE]; 42 43 /** 44 * Status. 45 */ 46 excite_cci_fpga_align_t status[EXCITE_DPR_STATUS_SIZE]; 47 48 #ifdef EXCITE_CCI_FPGA_MK2 49 /** 50 * RM9000 Interrupt. 51 * Write access initiates interrupt at the RM9000 (MIPS) processor of the eXcite. 52 */ 53 excite_cci_fpga_align_t rm9k_int; 54 #else 55 /** 56 * MK2 Interrupt. 57 * Write access initiates interrupt at the ARM processor of the MK2. 58 */ 59 excite_cci_fpga_align_t mk2_int; 60 61 excite_cci_fpga_align_t gap[0x1000-0x10f]; 62 63 /** 64 * IRQ Source/Acknowledge. 65 */ 66 excite_cci_fpga_align_t rm9k_irq_src; 67 68 /** 69 * IRQ Mask. 70 * Set bits enable the related interrupt. 71 */ 72 excite_cci_fpga_align_t rm9k_irq_mask; 73 #endif 74 75 76 } excite_fpga; 77 78 79 80 #endif /* ndef EXCITE_FPGA_H_INCLUDED */ 81