1 /*
2 * Copyright 2001 MontaVista Software Inc.
3 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
4 *
5 * Copyright (C) 2001 Ralf Baechle
6 * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved.
7 * Author: Maciej W. Rozycki <macro@mips.com>
8 *
9 * This file define the irq handler for MIPS CPU interrupts.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 */
16
17 /*
18 * Almost all MIPS CPUs define 8 interrupt sources. They are typically
19 * level triggered (i.e., cannot be cleared from CPU; must be cleared from
20 * device). The first two are software interrupts which we don't really
21 * use or support. The last one is usually the CPU timer interrupt if
22 * counter register is present or, for CPUs with an external FPU, by
23 * convention it's the FPU exception interrupt.
24 *
25 * Don't even think about using this on SMP. You have been warned.
26 *
27 * This file exports one global function:
28 * void mips_cpu_irq_init(void);
29 */
30 #include <linux/init.h>
31 #include <linux/interrupt.h>
32 #include <linux/kernel.h>
33
34 #include <asm/irq_cpu.h>
35 #include <asm/mipsregs.h>
36 #include <asm/mipsmtregs.h>
37 #include <asm/system.h>
38
unmask_mips_irq(unsigned int irq)39 static inline void unmask_mips_irq(unsigned int irq)
40 {
41 set_c0_status(0x100 << (irq - MIPS_CPU_IRQ_BASE));
42 irq_enable_hazard();
43 }
44
mask_mips_irq(unsigned int irq)45 static inline void mask_mips_irq(unsigned int irq)
46 {
47 clear_c0_status(0x100 << (irq - MIPS_CPU_IRQ_BASE));
48 irq_disable_hazard();
49 }
50
51 static struct irq_chip mips_cpu_irq_controller = {
52 .name = "MIPS",
53 .ack = mask_mips_irq,
54 .mask = mask_mips_irq,
55 .mask_ack = mask_mips_irq,
56 .unmask = unmask_mips_irq,
57 .eoi = unmask_mips_irq,
58 };
59
60 /*
61 * Basically the same as above but taking care of all the MT stuff
62 */
63
64 #define unmask_mips_mt_irq unmask_mips_irq
65 #define mask_mips_mt_irq mask_mips_irq
66
mips_mt_cpu_irq_startup(unsigned int irq)67 static unsigned int mips_mt_cpu_irq_startup(unsigned int irq)
68 {
69 unsigned int vpflags = dvpe();
70
71 clear_c0_cause(0x100 << (irq - MIPS_CPU_IRQ_BASE));
72 evpe(vpflags);
73 unmask_mips_mt_irq(irq);
74
75 return 0;
76 }
77
78 /*
79 * While we ack the interrupt interrupts are disabled and thus we don't need
80 * to deal with concurrency issues. Same for mips_cpu_irq_end.
81 */
mips_mt_cpu_irq_ack(unsigned int irq)82 static void mips_mt_cpu_irq_ack(unsigned int irq)
83 {
84 unsigned int vpflags = dvpe();
85 clear_c0_cause(0x100 << (irq - MIPS_CPU_IRQ_BASE));
86 evpe(vpflags);
87 mask_mips_mt_irq(irq);
88 }
89
90 static struct irq_chip mips_mt_cpu_irq_controller = {
91 .name = "MIPS",
92 .startup = mips_mt_cpu_irq_startup,
93 .ack = mips_mt_cpu_irq_ack,
94 .mask = mask_mips_mt_irq,
95 .mask_ack = mips_mt_cpu_irq_ack,
96 .unmask = unmask_mips_mt_irq,
97 .eoi = unmask_mips_mt_irq,
98 };
99
mips_cpu_irq_init(void)100 void __init mips_cpu_irq_init(void)
101 {
102 int irq_base = MIPS_CPU_IRQ_BASE;
103 int i;
104
105 /* Mask interrupts. */
106 clear_c0_status(ST0_IM);
107 clear_c0_cause(CAUSEF_IP);
108
109 /*
110 * Only MT is using the software interrupts currently, so we just
111 * leave them uninitialized for other processors.
112 */
113 if (cpu_has_mipsmt)
114 for (i = irq_base; i < irq_base + 2; i++)
115 set_irq_chip(i, &mips_mt_cpu_irq_controller);
116
117 for (i = irq_base + 2; i < irq_base + 8; i++)
118 set_irq_chip_and_handler(i, &mips_cpu_irq_controller,
119 handle_percpu_irq);
120 }
121