• Home
  • Line#
  • Scopes#
  • Navigate#
  • Raw
  • Download
1 /*
2  * This program is free software; you can redistribute it and/or
3  * modify it under the terms of the GNU General Public License
4  * as published by the Free Software Foundation; either version 2
5  * of the License, or (at your option) any later version.
6  *
7  * This program is distributed in the hope that it will be useful,
8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
10  * GNU General Public License for more details.
11  *
12  * You should have received a copy of the GNU General Public License
13  * along with this program; if not, write to the Free Software
14  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
15  *
16  * Copyright (C) 2004 Mips Technologies, Inc
17  * Copyright (C) 2008 Kevin D. Kissell
18  */
19 
20 #include <linux/clockchips.h>
21 #include <linux/kernel.h>
22 #include <linux/sched.h>
23 #include <linux/cpumask.h>
24 #include <linux/interrupt.h>
25 #include <linux/kernel_stat.h>
26 #include <linux/module.h>
27 
28 #include <asm/cpu.h>
29 #include <asm/processor.h>
30 #include <asm/atomic.h>
31 #include <asm/system.h>
32 #include <asm/hardirq.h>
33 #include <asm/hazards.h>
34 #include <asm/irq.h>
35 #include <asm/mmu_context.h>
36 #include <asm/mipsregs.h>
37 #include <asm/cacheflush.h>
38 #include <asm/time.h>
39 #include <asm/addrspace.h>
40 #include <asm/smtc.h>
41 #include <asm/smtc_proc.h>
42 
43 /*
44  * SMTC Kernel needs to manipulate low-level CPU interrupt mask
45  * in do_IRQ. These are passed in setup_irq_smtc() and stored
46  * in this table.
47  */
48 unsigned long irq_hwmask[NR_IRQS];
49 
50 #define LOCK_MT_PRA() \
51 	local_irq_save(flags); \
52 	mtflags = dmt()
53 
54 #define UNLOCK_MT_PRA() \
55 	emt(mtflags); \
56 	local_irq_restore(flags)
57 
58 #define LOCK_CORE_PRA() \
59 	local_irq_save(flags); \
60 	mtflags = dvpe()
61 
62 #define UNLOCK_CORE_PRA() \
63 	evpe(mtflags); \
64 	local_irq_restore(flags)
65 
66 /*
67  * Data structures purely associated with SMTC parallelism
68  */
69 
70 
71 /*
72  * Table for tracking ASIDs whose lifetime is prolonged.
73  */
74 
75 asiduse smtc_live_asid[MAX_SMTC_TLBS][MAX_SMTC_ASIDS];
76 
77 
78 /*
79  * Number of InterProcessor Interrupt (IPI) message buffers to allocate
80  */
81 
82 #define IPIBUF_PER_CPU 4
83 
84 struct smtc_ipi_q IPIQ[NR_CPUS];
85 static struct smtc_ipi_q freeIPIq;
86 
87 
88 /* Forward declarations */
89 
90 void ipi_decode(struct smtc_ipi *);
91 static void post_direct_ipi(int cpu, struct smtc_ipi *pipi);
92 static void setup_cross_vpe_interrupts(unsigned int nvpe);
93 void init_smtc_stats(void);
94 
95 /* Global SMTC Status */
96 
97 unsigned int smtc_status = 0;
98 
99 /* Boot command line configuration overrides */
100 
101 static int vpe0limit;
102 static int ipibuffers = 0;
103 static int nostlb = 0;
104 static int asidmask = 0;
105 unsigned long smtc_asid_mask = 0xff;
106 
vpe0tcs(char * str)107 static int __init vpe0tcs(char *str)
108 {
109 	get_option(&str, &vpe0limit);
110 
111 	return 1;
112 }
113 
ipibufs(char * str)114 static int __init ipibufs(char *str)
115 {
116 	get_option(&str, &ipibuffers);
117 	return 1;
118 }
119 
stlb_disable(char * s)120 static int __init stlb_disable(char *s)
121 {
122 	nostlb = 1;
123 	return 1;
124 }
125 
asidmask_set(char * str)126 static int __init asidmask_set(char *str)
127 {
128 	get_option(&str, &asidmask);
129 	switch (asidmask) {
130 	case 0x1:
131 	case 0x3:
132 	case 0x7:
133 	case 0xf:
134 	case 0x1f:
135 	case 0x3f:
136 	case 0x7f:
137 	case 0xff:
138 		smtc_asid_mask = (unsigned long)asidmask;
139 		break;
140 	default:
141 		printk("ILLEGAL ASID mask 0x%x from command line\n", asidmask);
142 	}
143 	return 1;
144 }
145 
146 __setup("vpe0tcs=", vpe0tcs);
147 __setup("ipibufs=", ipibufs);
148 __setup("nostlb", stlb_disable);
149 __setup("asidmask=", asidmask_set);
150 
151 #ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG
152 
153 static int hang_trig = 0;
154 
hangtrig_enable(char * s)155 static int __init hangtrig_enable(char *s)
156 {
157 	hang_trig = 1;
158 	return 1;
159 }
160 
161 
162 __setup("hangtrig", hangtrig_enable);
163 
164 #define DEFAULT_BLOCKED_IPI_LIMIT 32
165 
166 static int timerq_limit = DEFAULT_BLOCKED_IPI_LIMIT;
167 
tintq(char * str)168 static int __init tintq(char *str)
169 {
170 	get_option(&str, &timerq_limit);
171 	return 1;
172 }
173 
174 __setup("tintq=", tintq);
175 
176 static int imstuckcount[2][8];
177 /* vpemask represents IM/IE bits of per-VPE Status registers, low-to-high */
178 static int vpemask[2][8] = {
179 	{0, 0, 1, 0, 0, 0, 0, 1},
180 	{0, 0, 0, 0, 0, 0, 0, 1}
181 };
182 int tcnoprog[NR_CPUS];
183 static atomic_t idle_hook_initialized = {0};
184 static int clock_hang_reported[NR_CPUS];
185 
186 #endif /* CONFIG_SMTC_IDLE_HOOK_DEBUG */
187 
188 /*
189  * Configure shared TLB - VPC configuration bit must be set by caller
190  */
191 
smtc_configure_tlb(void)192 static void smtc_configure_tlb(void)
193 {
194 	int i, tlbsiz, vpes;
195 	unsigned long mvpconf0;
196 	unsigned long config1val;
197 
198 	/* Set up ASID preservation table */
199 	for (vpes=0; vpes<MAX_SMTC_TLBS; vpes++) {
200 	    for(i = 0; i < MAX_SMTC_ASIDS; i++) {
201 		smtc_live_asid[vpes][i] = 0;
202 	    }
203 	}
204 	mvpconf0 = read_c0_mvpconf0();
205 
206 	if ((vpes = ((mvpconf0 & MVPCONF0_PVPE)
207 			>> MVPCONF0_PVPE_SHIFT) + 1) > 1) {
208 	    /* If we have multiple VPEs, try to share the TLB */
209 	    if ((mvpconf0 & MVPCONF0_TLBS) && !nostlb) {
210 		/*
211 		 * If TLB sizing is programmable, shared TLB
212 		 * size is the total available complement.
213 		 * Otherwise, we have to take the sum of all
214 		 * static VPE TLB entries.
215 		 */
216 		if ((tlbsiz = ((mvpconf0 & MVPCONF0_PTLBE)
217 				>> MVPCONF0_PTLBE_SHIFT)) == 0) {
218 		    /*
219 		     * If there's more than one VPE, there had better
220 		     * be more than one TC, because we need one to bind
221 		     * to each VPE in turn to be able to read
222 		     * its configuration state!
223 		     */
224 		    settc(1);
225 		    /* Stop the TC from doing anything foolish */
226 		    write_tc_c0_tchalt(TCHALT_H);
227 		    mips_ihb();
228 		    /* No need to un-Halt - that happens later anyway */
229 		    for (i=0; i < vpes; i++) {
230 		    	write_tc_c0_tcbind(i);
231 			/*
232 			 * To be 100% sure we're really getting the right
233 			 * information, we exit the configuration state
234 			 * and do an IHB after each rebinding.
235 			 */
236 			write_c0_mvpcontrol(
237 				read_c0_mvpcontrol() & ~ MVPCONTROL_VPC );
238 			mips_ihb();
239 			/*
240 			 * Only count if the MMU Type indicated is TLB
241 			 */
242 			if (((read_vpe_c0_config() & MIPS_CONF_MT) >> 7) == 1) {
243 				config1val = read_vpe_c0_config1();
244 				tlbsiz += ((config1val >> 25) & 0x3f) + 1;
245 			}
246 
247 			/* Put core back in configuration state */
248 			write_c0_mvpcontrol(
249 				read_c0_mvpcontrol() | MVPCONTROL_VPC );
250 			mips_ihb();
251 		    }
252 		}
253 		write_c0_mvpcontrol(read_c0_mvpcontrol() | MVPCONTROL_STLB);
254 		ehb();
255 
256 		/*
257 		 * Setup kernel data structures to use software total,
258 		 * rather than read the per-VPE Config1 value. The values
259 		 * for "CPU 0" gets copied to all the other CPUs as part
260 		 * of their initialization in smtc_cpu_setup().
261 		 */
262 
263 		/* MIPS32 limits TLB indices to 64 */
264 		if (tlbsiz > 64)
265 			tlbsiz = 64;
266 		cpu_data[0].tlbsize = current_cpu_data.tlbsize = tlbsiz;
267 		smtc_status |= SMTC_TLB_SHARED;
268 		local_flush_tlb_all();
269 
270 		printk("TLB of %d entry pairs shared by %d VPEs\n",
271 			tlbsiz, vpes);
272 	    } else {
273 		printk("WARNING: TLB Not Sharable on SMTC Boot!\n");
274 	    }
275 	}
276 }
277 
278 
279 /*
280  * Incrementally build the CPU map out of constituent MIPS MT cores,
281  * using the specified available VPEs and TCs.  Plaform code needs
282  * to ensure that each MIPS MT core invokes this routine on reset,
283  * one at a time(!).
284  *
285  * This version of the build_cpu_map and prepare_cpus routines assumes
286  * that *all* TCs of a MIPS MT core will be used for Linux, and that
287  * they will be spread across *all* available VPEs (to minimise the
288  * loss of efficiency due to exception service serialization).
289  * An improved version would pick up configuration information and
290  * possibly leave some TCs/VPEs as "slave" processors.
291  *
292  * Use c0_MVPConf0 to find out how many TCs are available, setting up
293  * cpu_possible_map and the logical/physical mappings.
294  */
295 
smtc_build_cpu_map(int start_cpu_slot)296 int __init smtc_build_cpu_map(int start_cpu_slot)
297 {
298 	int i, ntcs;
299 
300 	/*
301 	 * The CPU map isn't actually used for anything at this point,
302 	 * so it's not clear what else we should do apart from set
303 	 * everything up so that "logical" = "physical".
304 	 */
305 	ntcs = ((read_c0_mvpconf0() & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1;
306 	for (i=start_cpu_slot; i<NR_CPUS && i<ntcs; i++) {
307 		cpu_set(i, cpu_possible_map);
308 		__cpu_number_map[i] = i;
309 		__cpu_logical_map[i] = i;
310 	}
311 #ifdef CONFIG_MIPS_MT_FPAFF
312 	/* Initialize map of CPUs with FPUs */
313 	cpus_clear(mt_fpu_cpumask);
314 #endif
315 
316 	/* One of those TC's is the one booting, and not a secondary... */
317 	printk("%i available secondary CPU TC(s)\n", i - 1);
318 
319 	return i;
320 }
321 
322 /*
323  * Common setup before any secondaries are started
324  * Make sure all CPU's are in a sensible state before we boot any of the
325  * secondaries.
326  *
327  * For MIPS MT "SMTC" operation, we set up all TCs, spread as evenly
328  * as possible across the available VPEs.
329  */
330 
smtc_tc_setup(int vpe,int tc,int cpu)331 static void smtc_tc_setup(int vpe, int tc, int cpu)
332 {
333 	settc(tc);
334 	write_tc_c0_tchalt(TCHALT_H);
335 	mips_ihb();
336 	write_tc_c0_tcstatus((read_tc_c0_tcstatus()
337 			& ~(TCSTATUS_TKSU | TCSTATUS_DA | TCSTATUS_IXMT))
338 			| TCSTATUS_A);
339 	/*
340 	 * TCContext gets an offset from the base of the IPIQ array
341 	 * to be used in low-level code to detect the presence of
342 	 * an active IPI queue
343 	 */
344 	write_tc_c0_tccontext((sizeof(struct smtc_ipi_q) * cpu) << 16);
345 	/* Bind tc to vpe */
346 	write_tc_c0_tcbind(vpe);
347 	/* In general, all TCs should have the same cpu_data indications */
348 	memcpy(&cpu_data[cpu], &cpu_data[0], sizeof(struct cpuinfo_mips));
349 	/* For 34Kf, start with TC/CPU 0 as sole owner of single FPU context */
350 	if (cpu_data[0].cputype == CPU_34K ||
351 	    cpu_data[0].cputype == CPU_1004K)
352 		cpu_data[cpu].options &= ~MIPS_CPU_FPU;
353 	cpu_data[cpu].vpe_id = vpe;
354 	cpu_data[cpu].tc_id = tc;
355 	/* Multi-core SMTC hasn't been tested, but be prepared */
356 	cpu_data[cpu].core = (read_vpe_c0_ebase() >> 1) & 0xff;
357 }
358 
359 /*
360  * Tweak to get Count registes in as close a sync as possible.
361  * Value seems good for 34K-class cores.
362  */
363 
364 #define CP0_SKEW 8
365 
smtc_prepare_cpus(int cpus)366 void smtc_prepare_cpus(int cpus)
367 {
368 	int i, vpe, tc, ntc, nvpe, tcpervpe[NR_CPUS], slop, cpu;
369 	unsigned long flags;
370 	unsigned long val;
371 	int nipi;
372 	struct smtc_ipi *pipi;
373 
374 	/* disable interrupts so we can disable MT */
375 	local_irq_save(flags);
376 	/* disable MT so we can configure */
377 	dvpe();
378 	dmt();
379 
380 	spin_lock_init(&freeIPIq.lock);
381 
382 	/*
383 	 * We probably don't have as many VPEs as we do SMP "CPUs",
384 	 * but it's possible - and in any case we'll never use more!
385 	 */
386 	for (i=0; i<NR_CPUS; i++) {
387 		IPIQ[i].head = IPIQ[i].tail = NULL;
388 		spin_lock_init(&IPIQ[i].lock);
389 		IPIQ[i].depth = 0;
390 	}
391 
392 	/* cpu_data index starts at zero */
393 	cpu = 0;
394 	cpu_data[cpu].vpe_id = 0;
395 	cpu_data[cpu].tc_id = 0;
396 	cpu_data[cpu].core = (read_c0_ebase() >> 1) & 0xff;
397 	cpu++;
398 
399 	/* Report on boot-time options */
400 	mips_mt_set_cpuoptions();
401 	if (vpelimit > 0)
402 		printk("Limit of %d VPEs set\n", vpelimit);
403 	if (tclimit > 0)
404 		printk("Limit of %d TCs set\n", tclimit);
405 	if (nostlb) {
406 		printk("Shared TLB Use Inhibited - UNSAFE for Multi-VPE Operation\n");
407 	}
408 	if (asidmask)
409 		printk("ASID mask value override to 0x%x\n", asidmask);
410 
411 	/* Temporary */
412 #ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG
413 	if (hang_trig)
414 		printk("Logic Analyser Trigger on suspected TC hang\n");
415 #endif /* CONFIG_SMTC_IDLE_HOOK_DEBUG */
416 
417 	/* Put MVPE's into 'configuration state' */
418 	write_c0_mvpcontrol( read_c0_mvpcontrol() | MVPCONTROL_VPC );
419 
420 	val = read_c0_mvpconf0();
421 	nvpe = ((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
422 	if (vpelimit > 0 && nvpe > vpelimit)
423 		nvpe = vpelimit;
424 	ntc = ((val & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1;
425 	if (ntc > NR_CPUS)
426 		ntc = NR_CPUS;
427 	if (tclimit > 0 && ntc > tclimit)
428 		ntc = tclimit;
429 	slop = ntc % nvpe;
430 	for (i = 0; i < nvpe; i++) {
431 		tcpervpe[i] = ntc / nvpe;
432 		if (slop) {
433 			if((slop - i) > 0) tcpervpe[i]++;
434 		}
435 	}
436 	/* Handle command line override for VPE0 */
437 	if (vpe0limit > ntc) vpe0limit = ntc;
438 	if (vpe0limit > 0) {
439 		int slopslop;
440 		if (vpe0limit < tcpervpe[0]) {
441 		    /* Reducing TC count - distribute to others */
442 		    slop = tcpervpe[0] - vpe0limit;
443 		    slopslop = slop % (nvpe - 1);
444 		    tcpervpe[0] = vpe0limit;
445 		    for (i = 1; i < nvpe; i++) {
446 			tcpervpe[i] += slop / (nvpe - 1);
447 			if(slopslop && ((slopslop - (i - 1) > 0)))
448 				tcpervpe[i]++;
449 		    }
450 		} else if (vpe0limit > tcpervpe[0]) {
451 		    /* Increasing TC count - steal from others */
452 		    slop = vpe0limit - tcpervpe[0];
453 		    slopslop = slop % (nvpe - 1);
454 		    tcpervpe[0] = vpe0limit;
455 		    for (i = 1; i < nvpe; i++) {
456 			tcpervpe[i] -= slop / (nvpe - 1);
457 			if(slopslop && ((slopslop - (i - 1) > 0)))
458 				tcpervpe[i]--;
459 		    }
460 		}
461 	}
462 
463 	/* Set up shared TLB */
464 	smtc_configure_tlb();
465 
466 	for (tc = 0, vpe = 0 ; (vpe < nvpe) && (tc < ntc) ; vpe++) {
467 		/*
468 		 * Set the MVP bits.
469 		 */
470 		settc(tc);
471 		write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_MVP);
472 		if (vpe != 0)
473 			printk(", ");
474 		printk("VPE %d: TC", vpe);
475 		for (i = 0; i < tcpervpe[vpe]; i++) {
476 			/*
477 			 * TC 0 is bound to VPE 0 at reset,
478 			 * and is presumably executing this
479 			 * code.  Leave it alone!
480 			 */
481 			if (tc != 0) {
482 				smtc_tc_setup(vpe, tc, cpu);
483 				cpu++;
484 			}
485 			printk(" %d", tc);
486 			tc++;
487 		}
488 		if (vpe != 0) {
489 			/*
490 			 * Clear any stale software interrupts from VPE's Cause
491 			 */
492 			write_vpe_c0_cause(0);
493 
494 			/*
495 			 * Clear ERL/EXL of VPEs other than 0
496 			 * and set restricted interrupt enable/mask.
497 			 */
498 			write_vpe_c0_status((read_vpe_c0_status()
499 				& ~(ST0_BEV | ST0_ERL | ST0_EXL | ST0_IM))
500 				| (STATUSF_IP0 | STATUSF_IP1 | STATUSF_IP7
501 				| ST0_IE));
502 			/*
503 			 * set config to be the same as vpe0,
504 			 *  particularly kseg0 coherency alg
505 			 */
506 			write_vpe_c0_config(read_c0_config());
507 			/* Clear any pending timer interrupt */
508 			write_vpe_c0_compare(0);
509 			/* Propagate Config7 */
510 			write_vpe_c0_config7(read_c0_config7());
511 			write_vpe_c0_count(read_c0_count() + CP0_SKEW);
512 			ehb();
513 		}
514 		/* enable multi-threading within VPE */
515 		write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() | VPECONTROL_TE);
516 		/* enable the VPE */
517 		write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_VPA);
518 	}
519 
520 	/*
521 	 * Pull any physically present but unused TCs out of circulation.
522 	 */
523 	while (tc < (((val & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1)) {
524 		cpu_clear(tc, cpu_possible_map);
525 		cpu_clear(tc, cpu_present_map);
526 		tc++;
527 	}
528 
529 	/* release config state */
530 	write_c0_mvpcontrol( read_c0_mvpcontrol() & ~ MVPCONTROL_VPC );
531 
532 	printk("\n");
533 
534 	/* Set up coprocessor affinity CPU mask(s) */
535 
536 #ifdef CONFIG_MIPS_MT_FPAFF
537 	for (tc = 0; tc < ntc; tc++) {
538 		if (cpu_data[tc].options & MIPS_CPU_FPU)
539 			cpu_set(tc, mt_fpu_cpumask);
540 	}
541 #endif
542 
543 	/* set up ipi interrupts... */
544 
545 	/* If we have multiple VPEs running, set up the cross-VPE interrupt */
546 
547 	setup_cross_vpe_interrupts(nvpe);
548 
549 	/* Set up queue of free IPI "messages". */
550 	nipi = NR_CPUS * IPIBUF_PER_CPU;
551 	if (ipibuffers > 0)
552 		nipi = ipibuffers;
553 
554 	pipi = kmalloc(nipi *sizeof(struct smtc_ipi), GFP_KERNEL);
555 	if (pipi == NULL)
556 		panic("kmalloc of IPI message buffers failed\n");
557 	else
558 		printk("IPI buffer pool of %d buffers\n", nipi);
559 	for (i = 0; i < nipi; i++) {
560 		smtc_ipi_nq(&freeIPIq, pipi);
561 		pipi++;
562 	}
563 
564 	/* Arm multithreading and enable other VPEs - but all TCs are Halted */
565 	emt(EMT_ENABLE);
566 	evpe(EVPE_ENABLE);
567 	local_irq_restore(flags);
568 	/* Initialize SMTC /proc statistics/diagnostics */
569 	init_smtc_stats();
570 }
571 
572 
573 /*
574  * Setup the PC, SP, and GP of a secondary processor and start it
575  * running!
576  * smp_bootstrap is the place to resume from
577  * __KSTK_TOS(idle) is apparently the stack pointer
578  * (unsigned long)idle->thread_info the gp
579  *
580  */
smtc_boot_secondary(int cpu,struct task_struct * idle)581 void __cpuinit smtc_boot_secondary(int cpu, struct task_struct *idle)
582 {
583 	extern u32 kernelsp[NR_CPUS];
584 	unsigned long flags;
585 	int mtflags;
586 
587 	LOCK_MT_PRA();
588 	if (cpu_data[cpu].vpe_id != cpu_data[smp_processor_id()].vpe_id) {
589 		dvpe();
590 	}
591 	settc(cpu_data[cpu].tc_id);
592 
593 	/* pc */
594 	write_tc_c0_tcrestart((unsigned long)&smp_bootstrap);
595 
596 	/* stack pointer */
597 	kernelsp[cpu] = __KSTK_TOS(idle);
598 	write_tc_gpr_sp(__KSTK_TOS(idle));
599 
600 	/* global pointer */
601 	write_tc_gpr_gp((unsigned long)task_thread_info(idle));
602 
603 	smtc_status |= SMTC_MTC_ACTIVE;
604 	write_tc_c0_tchalt(0);
605 	if (cpu_data[cpu].vpe_id != cpu_data[smp_processor_id()].vpe_id) {
606 		evpe(EVPE_ENABLE);
607 	}
608 	UNLOCK_MT_PRA();
609 }
610 
smtc_init_secondary(void)611 void smtc_init_secondary(void)
612 {
613 	local_irq_enable();
614 }
615 
smtc_smp_finish(void)616 void smtc_smp_finish(void)
617 {
618 	int cpu = smp_processor_id();
619 
620 	/*
621 	 * Lowest-numbered CPU per VPE starts a clock tick.
622 	 * Like per_cpu_trap_init() hack, this assumes that
623 	 * SMTC init code assigns TCs consdecutively and
624 	 * in ascending order across available VPEs.
625 	 */
626 	if (cpu > 0 && (cpu_data[cpu].vpe_id != cpu_data[cpu - 1].vpe_id))
627 		write_c0_compare(read_c0_count() + mips_hpt_frequency/HZ);
628 
629 	printk("TC %d going on-line as CPU %d\n",
630 		cpu_data[smp_processor_id()].tc_id, smp_processor_id());
631 }
632 
smtc_cpus_done(void)633 void smtc_cpus_done(void)
634 {
635 }
636 
637 /*
638  * Support for SMTC-optimized driver IRQ registration
639  */
640 
641 /*
642  * SMTC Kernel needs to manipulate low-level CPU interrupt mask
643  * in do_IRQ. These are passed in setup_irq_smtc() and stored
644  * in this table.
645  */
646 
setup_irq_smtc(unsigned int irq,struct irqaction * new,unsigned long hwmask)647 int setup_irq_smtc(unsigned int irq, struct irqaction * new,
648 			unsigned long hwmask)
649 {
650 #ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG
651 	unsigned int vpe = current_cpu_data.vpe_id;
652 
653 	vpemask[vpe][irq - MIPS_CPU_IRQ_BASE] = 1;
654 #endif
655 	irq_hwmask[irq] = hwmask;
656 
657 	return setup_irq(irq, new);
658 }
659 
660 #ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
661 /*
662  * Support for IRQ affinity to TCs
663  */
664 
smtc_set_irq_affinity(unsigned int irq,cpumask_t affinity)665 void smtc_set_irq_affinity(unsigned int irq, cpumask_t affinity)
666 {
667 	/*
668 	 * If a "fast path" cache of quickly decodable affinity state
669 	 * is maintained, this is where it gets done, on a call up
670 	 * from the platform affinity code.
671 	 */
672 }
673 
smtc_forward_irq(unsigned int irq)674 void smtc_forward_irq(unsigned int irq)
675 {
676 	int target;
677 
678 	/*
679 	 * OK wise guy, now figure out how to get the IRQ
680 	 * to be serviced on an authorized "CPU".
681 	 *
682 	 * Ideally, to handle the situation where an IRQ has multiple
683 	 * eligible CPUS, we would maintain state per IRQ that would
684 	 * allow a fair distribution of service requests.  Since the
685 	 * expected use model is any-or-only-one, for simplicity
686 	 * and efficiency, we just pick the easiest one to find.
687 	 */
688 
689 	target = first_cpu(irq_desc[irq].affinity);
690 
691 	/*
692 	 * We depend on the platform code to have correctly processed
693 	 * IRQ affinity change requests to ensure that the IRQ affinity
694 	 * mask has been purged of bits corresponding to nonexistent and
695 	 * offline "CPUs", and to TCs bound to VPEs other than the VPE
696 	 * connected to the physical interrupt input for the interrupt
697 	 * in question.  Otherwise we have a nasty problem with interrupt
698 	 * mask management.  This is best handled in non-performance-critical
699 	 * platform IRQ affinity setting code,  to minimize interrupt-time
700 	 * checks.
701 	 */
702 
703 	/* If no one is eligible, service locally */
704 	if (target >= NR_CPUS) {
705 		do_IRQ_no_affinity(irq);
706 		return;
707 	}
708 
709 	smtc_send_ipi(target, IRQ_AFFINITY_IPI, irq);
710 }
711 
712 #endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
713 
714 /*
715  * IPI model for SMTC is tricky, because interrupts aren't TC-specific.
716  * Within a VPE one TC can interrupt another by different approaches.
717  * The easiest to get right would probably be to make all TCs except
718  * the target IXMT and set a software interrupt, but an IXMT-based
719  * scheme requires that a handler must run before a new IPI could
720  * be sent, which would break the "broadcast" loops in MIPS MT.
721  * A more gonzo approach within a VPE is to halt the TC, extract
722  * its Restart, Status, and a couple of GPRs, and program the Restart
723  * address to emulate an interrupt.
724  *
725  * Within a VPE, one can be confident that the target TC isn't in
726  * a critical EXL state when halted, since the write to the Halt
727  * register could not have issued on the writing thread if the
728  * halting thread had EXL set. So k0 and k1 of the target TC
729  * can be used by the injection code.  Across VPEs, one can't
730  * be certain that the target TC isn't in a critical exception
731  * state. So we try a two-step process of sending a software
732  * interrupt to the target VPE, which either handles the event
733  * itself (if it was the target) or injects the event within
734  * the VPE.
735  */
736 
smtc_ipi_qdump(void)737 static void smtc_ipi_qdump(void)
738 {
739 	int i;
740 
741 	for (i = 0; i < NR_CPUS ;i++) {
742 		printk("IPIQ[%d]: head = 0x%x, tail = 0x%x, depth = %d\n",
743 			i, (unsigned)IPIQ[i].head, (unsigned)IPIQ[i].tail,
744 			IPIQ[i].depth);
745 	}
746 }
747 
748 /*
749  * The standard atomic.h primitives don't quite do what we want
750  * here: We need an atomic add-and-return-previous-value (which
751  * could be done with atomic_add_return and a decrement) and an
752  * atomic set/zero-and-return-previous-value (which can't really
753  * be done with the atomic.h primitives). And since this is
754  * MIPS MT, we can assume that we have LL/SC.
755  */
atomic_postincrement(atomic_t * v)756 static inline int atomic_postincrement(atomic_t *v)
757 {
758 	unsigned long result;
759 
760 	unsigned long temp;
761 
762 	__asm__ __volatile__(
763 	"1:	ll	%0, %2					\n"
764 	"	addu	%1, %0, 1				\n"
765 	"	sc	%1, %2					\n"
766 	"	beqz	%1, 1b					\n"
767 	__WEAK_LLSC_MB
768 	: "=&r" (result), "=&r" (temp), "=m" (v->counter)
769 	: "m" (v->counter)
770 	: "memory");
771 
772 	return result;
773 }
774 
smtc_send_ipi(int cpu,int type,unsigned int action)775 void smtc_send_ipi(int cpu, int type, unsigned int action)
776 {
777 	int tcstatus;
778 	struct smtc_ipi *pipi;
779 	unsigned long flags;
780 	int mtflags;
781 	unsigned long tcrestart;
782 	extern void r4k_wait_irqoff(void), __pastwait(void);
783 
784 	if (cpu == smp_processor_id()) {
785 		printk("Cannot Send IPI to self!\n");
786 		return;
787 	}
788 	/* Set up a descriptor, to be delivered either promptly or queued */
789 	pipi = smtc_ipi_dq(&freeIPIq);
790 	if (pipi == NULL) {
791 		bust_spinlocks(1);
792 		mips_mt_regdump(dvpe());
793 		panic("IPI Msg. Buffers Depleted\n");
794 	}
795 	pipi->type = type;
796 	pipi->arg = (void *)action;
797 	pipi->dest = cpu;
798 	if (cpu_data[cpu].vpe_id != cpu_data[smp_processor_id()].vpe_id) {
799 		/* If not on same VPE, enqueue and send cross-VPE interrupt */
800 		smtc_ipi_nq(&IPIQ[cpu], pipi);
801 		LOCK_CORE_PRA();
802 		settc(cpu_data[cpu].tc_id);
803 		write_vpe_c0_cause(read_vpe_c0_cause() | C_SW1);
804 		UNLOCK_CORE_PRA();
805 	} else {
806 		/*
807 		 * Not sufficient to do a LOCK_MT_PRA (dmt) here,
808 		 * since ASID shootdown on the other VPE may
809 		 * collide with this operation.
810 		 */
811 		LOCK_CORE_PRA();
812 		settc(cpu_data[cpu].tc_id);
813 		/* Halt the targeted TC */
814 		write_tc_c0_tchalt(TCHALT_H);
815 		mips_ihb();
816 
817 		/*
818 	 	 * Inspect TCStatus - if IXMT is set, we have to queue
819 		 * a message. Otherwise, we set up the "interrupt"
820 		 * of the other TC
821 	 	 */
822 		tcstatus = read_tc_c0_tcstatus();
823 
824 		if ((tcstatus & TCSTATUS_IXMT) != 0) {
825 			/*
826 			 * If we're in the the irq-off version of the wait
827 			 * loop, we need to force exit from the wait and
828 			 * do a direct post of the IPI.
829 			 */
830 			if (cpu_wait == r4k_wait_irqoff) {
831 				tcrestart = read_tc_c0_tcrestart();
832 				if (tcrestart >= (unsigned long)r4k_wait_irqoff
833 				    && tcrestart < (unsigned long)__pastwait) {
834 					write_tc_c0_tcrestart(__pastwait);
835 					tcstatus &= ~TCSTATUS_IXMT;
836 					write_tc_c0_tcstatus(tcstatus);
837 					goto postdirect;
838 				}
839 			}
840 			/*
841 			 * Otherwise we queue the message for the target TC
842 			 * to pick up when he does a local_irq_restore()
843 			 */
844 			write_tc_c0_tchalt(0);
845 			UNLOCK_CORE_PRA();
846 			smtc_ipi_nq(&IPIQ[cpu], pipi);
847 		} else {
848 postdirect:
849 			post_direct_ipi(cpu, pipi);
850 			write_tc_c0_tchalt(0);
851 			UNLOCK_CORE_PRA();
852 		}
853 	}
854 }
855 
856 /*
857  * Send IPI message to Halted TC, TargTC/TargVPE already having been set
858  */
post_direct_ipi(int cpu,struct smtc_ipi * pipi)859 static void post_direct_ipi(int cpu, struct smtc_ipi *pipi)
860 {
861 	struct pt_regs *kstack;
862 	unsigned long tcstatus;
863 	unsigned long tcrestart;
864 	extern u32 kernelsp[NR_CPUS];
865 	extern void __smtc_ipi_vector(void);
866 //printk("%s: on %d for %d\n", __func__, smp_processor_id(), cpu);
867 
868 	/* Extract Status, EPC from halted TC */
869 	tcstatus = read_tc_c0_tcstatus();
870 	tcrestart = read_tc_c0_tcrestart();
871 	/* If TCRestart indicates a WAIT instruction, advance the PC */
872 	if ((tcrestart & 0x80000000)
873 	    && ((*(unsigned int *)tcrestart & 0xfe00003f) == 0x42000020)) {
874 		tcrestart += 4;
875 	}
876 	/*
877 	 * Save on TC's future kernel stack
878 	 *
879 	 * CU bit of Status is indicator that TC was
880 	 * already running on a kernel stack...
881 	 */
882 	if (tcstatus & ST0_CU0)  {
883 		/* Note that this "- 1" is pointer arithmetic */
884 		kstack = ((struct pt_regs *)read_tc_gpr_sp()) - 1;
885 	} else {
886 		kstack = ((struct pt_regs *)kernelsp[cpu]) - 1;
887 	}
888 
889 	kstack->cp0_epc = (long)tcrestart;
890 	/* Save TCStatus */
891 	kstack->cp0_tcstatus = tcstatus;
892 	/* Pass token of operation to be performed kernel stack pad area */
893 	kstack->pad0[4] = (unsigned long)pipi;
894 	/* Pass address of function to be called likewise */
895 	kstack->pad0[5] = (unsigned long)&ipi_decode;
896 	/* Set interrupt exempt and kernel mode */
897 	tcstatus |= TCSTATUS_IXMT;
898 	tcstatus &= ~TCSTATUS_TKSU;
899 	write_tc_c0_tcstatus(tcstatus);
900 	ehb();
901 	/* Set TC Restart address to be SMTC IPI vector */
902 	write_tc_c0_tcrestart(__smtc_ipi_vector);
903 }
904 
ipi_resched_interrupt(void)905 static void ipi_resched_interrupt(void)
906 {
907 	/* Return from interrupt should be enough to cause scheduler check */
908 }
909 
ipi_call_interrupt(void)910 static void ipi_call_interrupt(void)
911 {
912 	/* Invoke generic function invocation code in smp.c */
913 	smp_call_function_interrupt();
914 }
915 
916 DECLARE_PER_CPU(struct clock_event_device, mips_clockevent_device);
917 
ipi_decode(struct smtc_ipi * pipi)918 void ipi_decode(struct smtc_ipi *pipi)
919 {
920 	unsigned int cpu = smp_processor_id();
921 	struct clock_event_device *cd;
922 	void *arg_copy = pipi->arg;
923 	int type_copy = pipi->type;
924 	smtc_ipi_nq(&freeIPIq, pipi);
925 	switch (type_copy) {
926 	case SMTC_CLOCK_TICK:
927 		irq_enter();
928 		kstat_this_cpu.irqs[MIPS_CPU_IRQ_BASE + 1]++;
929 		cd = &per_cpu(mips_clockevent_device, cpu);
930 		cd->event_handler(cd);
931 		irq_exit();
932 		break;
933 
934 	case LINUX_SMP_IPI:
935 		switch ((int)arg_copy) {
936 		case SMP_RESCHEDULE_YOURSELF:
937 			ipi_resched_interrupt();
938 			break;
939 		case SMP_CALL_FUNCTION:
940 			ipi_call_interrupt();
941 			break;
942 		default:
943 			printk("Impossible SMTC IPI Argument 0x%x\n",
944 				(int)arg_copy);
945 			break;
946 		}
947 		break;
948 #ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
949 	case IRQ_AFFINITY_IPI:
950 		/*
951 		 * Accept a "forwarded" interrupt that was initially
952 		 * taken by a TC who doesn't have affinity for the IRQ.
953 		 */
954 		do_IRQ_no_affinity((int)arg_copy);
955 		break;
956 #endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
957 	default:
958 		printk("Impossible SMTC IPI Type 0x%x\n", type_copy);
959 		break;
960 	}
961 }
962 
963 /*
964  * Similar to smtc_ipi_replay(), but invoked from context restore,
965  * so it reuses the current exception frame rather than set up a
966  * new one with self_ipi.
967  */
968 
deferred_smtc_ipi(void)969 void deferred_smtc_ipi(void)
970 {
971 	int cpu = smp_processor_id();
972 
973 	/*
974 	 * Test is not atomic, but much faster than a dequeue,
975 	 * and the vast majority of invocations will have a null queue.
976 	 * If irq_disabled when this was called, then any IPIs queued
977 	 * after we test last will be taken on the next irq_enable/restore.
978 	 * If interrupts were enabled, then any IPIs added after the
979 	 * last test will be taken directly.
980 	 */
981 
982 	while (IPIQ[cpu].head != NULL) {
983 		struct smtc_ipi_q *q = &IPIQ[cpu];
984 		struct smtc_ipi *pipi;
985 		unsigned long flags;
986 
987 		/*
988 		 * It may be possible we'll come in with interrupts
989 		 * already enabled.
990 		 */
991 		local_irq_save(flags);
992 
993 		spin_lock(&q->lock);
994 		pipi = __smtc_ipi_dq(q);
995 		spin_unlock(&q->lock);
996 		if (pipi != NULL)
997 			ipi_decode(pipi);
998 		/*
999 		 * The use of the __raw_local restore isn't
1000 		 * as obviously necessary here as in smtc_ipi_replay(),
1001 		 * but it's more efficient, given that we're already
1002 		 * running down the IPI queue.
1003 		 */
1004 		__raw_local_irq_restore(flags);
1005 	}
1006 }
1007 
1008 /*
1009  * Cross-VPE interrupts in the SMTC prototype use "software interrupts"
1010  * set via cross-VPE MTTR manipulation of the Cause register. It would be
1011  * in some regards preferable to have external logic for "doorbell" hardware
1012  * interrupts.
1013  */
1014 
1015 static int cpu_ipi_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_IRQ;
1016 
ipi_interrupt(int irq,void * dev_idm)1017 static irqreturn_t ipi_interrupt(int irq, void *dev_idm)
1018 {
1019 	int my_vpe = cpu_data[smp_processor_id()].vpe_id;
1020 	int my_tc = cpu_data[smp_processor_id()].tc_id;
1021 	int cpu;
1022 	struct smtc_ipi *pipi;
1023 	unsigned long tcstatus;
1024 	int sent;
1025 	unsigned long flags;
1026 	unsigned int mtflags;
1027 	unsigned int vpflags;
1028 
1029 	/*
1030 	 * So long as cross-VPE interrupts are done via
1031 	 * MFTR/MTTR read-modify-writes of Cause, we need
1032 	 * to stop other VPEs whenever the local VPE does
1033 	 * anything similar.
1034 	 */
1035 	local_irq_save(flags);
1036 	vpflags = dvpe();
1037 	clear_c0_cause(0x100 << MIPS_CPU_IPI_IRQ);
1038 	set_c0_status(0x100 << MIPS_CPU_IPI_IRQ);
1039 	irq_enable_hazard();
1040 	evpe(vpflags);
1041 	local_irq_restore(flags);
1042 
1043 	/*
1044 	 * Cross-VPE Interrupt handler: Try to directly deliver IPIs
1045 	 * queued for TCs on this VPE other than the current one.
1046 	 * Return-from-interrupt should cause us to drain the queue
1047 	 * for the current TC, so we ought not to have to do it explicitly here.
1048 	 */
1049 
1050 	for_each_online_cpu(cpu) {
1051 		if (cpu_data[cpu].vpe_id != my_vpe)
1052 			continue;
1053 
1054 		pipi = smtc_ipi_dq(&IPIQ[cpu]);
1055 		if (pipi != NULL) {
1056 			if (cpu_data[cpu].tc_id != my_tc) {
1057 				sent = 0;
1058 				LOCK_MT_PRA();
1059 				settc(cpu_data[cpu].tc_id);
1060 				write_tc_c0_tchalt(TCHALT_H);
1061 				mips_ihb();
1062 				tcstatus = read_tc_c0_tcstatus();
1063 				if ((tcstatus & TCSTATUS_IXMT) == 0) {
1064 					post_direct_ipi(cpu, pipi);
1065 					sent = 1;
1066 				}
1067 				write_tc_c0_tchalt(0);
1068 				UNLOCK_MT_PRA();
1069 				if (!sent) {
1070 					smtc_ipi_req(&IPIQ[cpu], pipi);
1071 				}
1072 			} else {
1073 				/*
1074 				 * ipi_decode() should be called
1075 				 * with interrupts off
1076 				 */
1077 				local_irq_save(flags);
1078 				ipi_decode(pipi);
1079 				local_irq_restore(flags);
1080 			}
1081 		}
1082 	}
1083 
1084 	return IRQ_HANDLED;
1085 }
1086 
ipi_irq_dispatch(void)1087 static void ipi_irq_dispatch(void)
1088 {
1089 	do_IRQ(cpu_ipi_irq);
1090 }
1091 
1092 static struct irqaction irq_ipi = {
1093 	.handler	= ipi_interrupt,
1094 	.flags		= IRQF_DISABLED,
1095 	.name		= "SMTC_IPI",
1096 	.flags		= IRQF_PERCPU
1097 };
1098 
setup_cross_vpe_interrupts(unsigned int nvpe)1099 static void setup_cross_vpe_interrupts(unsigned int nvpe)
1100 {
1101 	if (nvpe < 1)
1102 		return;
1103 
1104 	if (!cpu_has_vint)
1105 		panic("SMTC Kernel requires Vectored Interrupt support");
1106 
1107 	set_vi_handler(MIPS_CPU_IPI_IRQ, ipi_irq_dispatch);
1108 
1109 	setup_irq_smtc(cpu_ipi_irq, &irq_ipi, (0x100 << MIPS_CPU_IPI_IRQ));
1110 
1111 	set_irq_handler(cpu_ipi_irq, handle_percpu_irq);
1112 }
1113 
1114 /*
1115  * SMTC-specific hacks invoked from elsewhere in the kernel.
1116  */
1117 
1118  /*
1119   * smtc_ipi_replay is called from raw_local_irq_restore
1120   */
1121 
smtc_ipi_replay(void)1122 void smtc_ipi_replay(void)
1123 {
1124 	unsigned int cpu = smp_processor_id();
1125 
1126 	/*
1127 	 * To the extent that we've ever turned interrupts off,
1128 	 * we may have accumulated deferred IPIs.  This is subtle.
1129 	 * we should be OK:  If we pick up something and dispatch
1130 	 * it here, that's great. If we see nothing, but concurrent
1131 	 * with this operation, another TC sends us an IPI, IXMT
1132 	 * is clear, and we'll handle it as a real pseudo-interrupt
1133 	 * and not a pseudo-pseudo interrupt.  The important thing
1134 	 * is to do the last check for queued message *after* the
1135 	 * re-enabling of interrupts.
1136 	 */
1137 	while (IPIQ[cpu].head != NULL) {
1138 		struct smtc_ipi_q *q = &IPIQ[cpu];
1139 		struct smtc_ipi *pipi;
1140 		unsigned long flags;
1141 
1142 		/*
1143 		 * It's just possible we'll come in with interrupts
1144 		 * already enabled.
1145 		 */
1146 		local_irq_save(flags);
1147 
1148 		spin_lock(&q->lock);
1149 		pipi = __smtc_ipi_dq(q);
1150 		spin_unlock(&q->lock);
1151 		/*
1152 		 ** But use a raw restore here to avoid recursion.
1153 		 */
1154 		__raw_local_irq_restore(flags);
1155 
1156 		if (pipi) {
1157 			self_ipi(pipi);
1158 			smtc_cpu_stats[cpu].selfipis++;
1159 		}
1160 	}
1161 }
1162 
1163 EXPORT_SYMBOL(smtc_ipi_replay);
1164 
smtc_idle_loop_hook(void)1165 void smtc_idle_loop_hook(void)
1166 {
1167 #ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG
1168 	int im;
1169 	int flags;
1170 	int mtflags;
1171 	int bit;
1172 	int vpe;
1173 	int tc;
1174 	int hook_ntcs;
1175 	/*
1176 	 * printk within DMT-protected regions can deadlock,
1177 	 * so buffer diagnostic messages for later output.
1178 	 */
1179 	char *pdb_msg;
1180 	char id_ho_db_msg[768]; /* worst-case use should be less than 700 */
1181 
1182 	if (atomic_read(&idle_hook_initialized) == 0) { /* fast test */
1183 		if (atomic_add_return(1, &idle_hook_initialized) == 1) {
1184 			int mvpconf0;
1185 			/* Tedious stuff to just do once */
1186 			mvpconf0 = read_c0_mvpconf0();
1187 			hook_ntcs = ((mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1;
1188 			if (hook_ntcs > NR_CPUS)
1189 				hook_ntcs = NR_CPUS;
1190 			for (tc = 0; tc < hook_ntcs; tc++) {
1191 				tcnoprog[tc] = 0;
1192 				clock_hang_reported[tc] = 0;
1193 	    		}
1194 			for (vpe = 0; vpe < 2; vpe++)
1195 				for (im = 0; im < 8; im++)
1196 					imstuckcount[vpe][im] = 0;
1197 			printk("Idle loop test hook initialized for %d TCs\n", hook_ntcs);
1198 			atomic_set(&idle_hook_initialized, 1000);
1199 		} else {
1200 			/* Someone else is initializing in parallel - let 'em finish */
1201 			while (atomic_read(&idle_hook_initialized) < 1000)
1202 				;
1203 		}
1204 	}
1205 
1206 	/* Have we stupidly left IXMT set somewhere? */
1207 	if (read_c0_tcstatus() & 0x400) {
1208 		write_c0_tcstatus(read_c0_tcstatus() & ~0x400);
1209 		ehb();
1210 		printk("Dangling IXMT in cpu_idle()\n");
1211 	}
1212 
1213 	/* Have we stupidly left an IM bit turned off? */
1214 #define IM_LIMIT 2000
1215 	local_irq_save(flags);
1216 	mtflags = dmt();
1217 	pdb_msg = &id_ho_db_msg[0];
1218 	im = read_c0_status();
1219 	vpe = current_cpu_data.vpe_id;
1220 	for (bit = 0; bit < 8; bit++) {
1221 		/*
1222 		 * In current prototype, I/O interrupts
1223 		 * are masked for VPE > 0
1224 		 */
1225 		if (vpemask[vpe][bit]) {
1226 			if (!(im & (0x100 << bit)))
1227 				imstuckcount[vpe][bit]++;
1228 			else
1229 				imstuckcount[vpe][bit] = 0;
1230 			if (imstuckcount[vpe][bit] > IM_LIMIT) {
1231 				set_c0_status(0x100 << bit);
1232 				ehb();
1233 				imstuckcount[vpe][bit] = 0;
1234 				pdb_msg += sprintf(pdb_msg,
1235 					"Dangling IM %d fixed for VPE %d\n", bit,
1236 					vpe);
1237 			}
1238 		}
1239 	}
1240 
1241 	emt(mtflags);
1242 	local_irq_restore(flags);
1243 	if (pdb_msg != &id_ho_db_msg[0])
1244 		printk("CPU%d: %s", smp_processor_id(), id_ho_db_msg);
1245 #endif /* CONFIG_SMTC_IDLE_HOOK_DEBUG */
1246 
1247 	smtc_ipi_replay();
1248 }
1249 
smtc_soft_dump(void)1250 void smtc_soft_dump(void)
1251 {
1252 	int i;
1253 
1254 	printk("Counter Interrupts taken per CPU (TC)\n");
1255 	for (i=0; i < NR_CPUS; i++) {
1256 		printk("%d: %ld\n", i, smtc_cpu_stats[i].timerints);
1257 	}
1258 	printk("Self-IPI invocations:\n");
1259 	for (i=0; i < NR_CPUS; i++) {
1260 		printk("%d: %ld\n", i, smtc_cpu_stats[i].selfipis);
1261 	}
1262 	smtc_ipi_qdump();
1263 	printk("%d Recoveries of \"stolen\" FPU\n",
1264 	       atomic_read(&smtc_fpu_recoveries));
1265 }
1266 
1267 
1268 /*
1269  * TLB management routines special to SMTC
1270  */
1271 
smtc_get_new_mmu_context(struct mm_struct * mm,unsigned long cpu)1272 void smtc_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
1273 {
1274 	unsigned long flags, mtflags, tcstat, prevhalt, asid;
1275 	int tlb, i;
1276 
1277 	/*
1278 	 * It would be nice to be able to use a spinlock here,
1279 	 * but this is invoked from within TLB flush routines
1280 	 * that protect themselves with DVPE, so if a lock is
1281 	 * held by another TC, it'll never be freed.
1282 	 *
1283 	 * DVPE/DMT must not be done with interrupts enabled,
1284 	 * so even so most callers will already have disabled
1285 	 * them, let's be really careful...
1286 	 */
1287 
1288 	local_irq_save(flags);
1289 	if (smtc_status & SMTC_TLB_SHARED) {
1290 		mtflags = dvpe();
1291 		tlb = 0;
1292 	} else {
1293 		mtflags = dmt();
1294 		tlb = cpu_data[cpu].vpe_id;
1295 	}
1296 	asid = asid_cache(cpu);
1297 
1298 	do {
1299 		if (!((asid += ASID_INC) & ASID_MASK) ) {
1300 			if (cpu_has_vtag_icache)
1301 				flush_icache_all();
1302 			/* Traverse all online CPUs (hack requires contigous range) */
1303 			for_each_online_cpu(i) {
1304 				/*
1305 				 * We don't need to worry about our own CPU, nor those of
1306 				 * CPUs who don't share our TLB.
1307 				 */
1308 				if ((i != smp_processor_id()) &&
1309 				    ((smtc_status & SMTC_TLB_SHARED) ||
1310 				     (cpu_data[i].vpe_id == cpu_data[cpu].vpe_id))) {
1311 					settc(cpu_data[i].tc_id);
1312 					prevhalt = read_tc_c0_tchalt() & TCHALT_H;
1313 					if (!prevhalt) {
1314 						write_tc_c0_tchalt(TCHALT_H);
1315 						mips_ihb();
1316 					}
1317 					tcstat = read_tc_c0_tcstatus();
1318 					smtc_live_asid[tlb][(tcstat & ASID_MASK)] |= (asiduse)(0x1 << i);
1319 					if (!prevhalt)
1320 						write_tc_c0_tchalt(0);
1321 				}
1322 			}
1323 			if (!asid)		/* fix version if needed */
1324 				asid = ASID_FIRST_VERSION;
1325 			local_flush_tlb_all();	/* start new asid cycle */
1326 		}
1327 	} while (smtc_live_asid[tlb][(asid & ASID_MASK)]);
1328 
1329 	/*
1330 	 * SMTC shares the TLB within VPEs and possibly across all VPEs.
1331 	 */
1332 	for_each_online_cpu(i) {
1333 		if ((smtc_status & SMTC_TLB_SHARED) ||
1334 		    (cpu_data[i].vpe_id == cpu_data[cpu].vpe_id))
1335 			cpu_context(i, mm) = asid_cache(i) = asid;
1336 	}
1337 
1338 	if (smtc_status & SMTC_TLB_SHARED)
1339 		evpe(mtflags);
1340 	else
1341 		emt(mtflags);
1342 	local_irq_restore(flags);
1343 }
1344 
1345 /*
1346  * Invoked from macros defined in mmu_context.h
1347  * which must already have disabled interrupts
1348  * and done a DVPE or DMT as appropriate.
1349  */
1350 
smtc_flush_tlb_asid(unsigned long asid)1351 void smtc_flush_tlb_asid(unsigned long asid)
1352 {
1353 	int entry;
1354 	unsigned long ehi;
1355 
1356 	entry = read_c0_wired();
1357 
1358 	/* Traverse all non-wired entries */
1359 	while (entry < current_cpu_data.tlbsize) {
1360 		write_c0_index(entry);
1361 		ehb();
1362 		tlb_read();
1363 		ehb();
1364 		ehi = read_c0_entryhi();
1365 		if ((ehi & ASID_MASK) == asid) {
1366 		    /*
1367 		     * Invalidate only entries with specified ASID,
1368 		     * makiing sure all entries differ.
1369 		     */
1370 		    write_c0_entryhi(CKSEG0 + (entry << (PAGE_SHIFT + 1)));
1371 		    write_c0_entrylo0(0);
1372 		    write_c0_entrylo1(0);
1373 		    mtc0_tlbw_hazard();
1374 		    tlb_write_indexed();
1375 		}
1376 		entry++;
1377 	}
1378 	write_c0_index(PARKED_INDEX);
1379 	tlbw_use_hazard();
1380 }
1381 
1382 /*
1383  * Support for single-threading cache flush operations.
1384  */
1385 
1386 static int halt_state_save[NR_CPUS];
1387 
1388 /*
1389  * To really, really be sure that nothing is being done
1390  * by other TCs, halt them all.  This code assumes that
1391  * a DVPE has already been done, so while their Halted
1392  * state is theoretically architecturally unstable, in
1393  * practice, it's not going to change while we're looking
1394  * at it.
1395  */
1396 
smtc_cflush_lockdown(void)1397 void smtc_cflush_lockdown(void)
1398 {
1399 	int cpu;
1400 
1401 	for_each_online_cpu(cpu) {
1402 		if (cpu != smp_processor_id()) {
1403 			settc(cpu_data[cpu].tc_id);
1404 			halt_state_save[cpu] = read_tc_c0_tchalt();
1405 			write_tc_c0_tchalt(TCHALT_H);
1406 		}
1407 	}
1408 	mips_ihb();
1409 }
1410 
1411 /* It would be cheating to change the cpu_online states during a flush! */
1412 
smtc_cflush_release(void)1413 void smtc_cflush_release(void)
1414 {
1415 	int cpu;
1416 
1417 	/*
1418 	 * Start with a hazard barrier to ensure
1419 	 * that all CACHE ops have played through.
1420 	 */
1421 	mips_ihb();
1422 
1423 	for_each_online_cpu(cpu) {
1424 		if (cpu != smp_processor_id()) {
1425 			settc(cpu_data[cpu].tc_id);
1426 			write_tc_c0_tchalt(halt_state_save[cpu]);
1427 		}
1428 	}
1429 	mips_ihb();
1430 }
1431