1 /*
2 * fixup-lm2e.c
3 *
4 * Copyright (C) 2004 ICT CAS
5 * Author: Li xiaoyu, ICT CAS
6 * lixy@ict.ac.cn
7 *
8 * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology
9 * Author: Fuxin Zhang, zhangfx@lemote.com
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
19 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
22 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
23 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 *
27 * You should have received a copy of the GNU General Public License along
28 * with this program; if not, write to the Free Software Foundation, Inc.,
29 * 675 Mass Ave, Cambridge, MA 02139, USA.
30 *
31 */
32 #include <linux/init.h>
33 #include <linux/pci.h>
34 #include <asm/mips-boards/bonito64.h>
35
36 /* South bridge slot number is set by the pci probe process */
37 static u8 sb_slot = 5;
38
pcibios_map_irq(const struct pci_dev * dev,u8 slot,u8 pin)39 int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
40 {
41 int irq = 0;
42
43 if (slot == sb_slot) {
44 switch (PCI_FUNC(dev->devfn)) {
45 case 2:
46 irq = 10;
47 break;
48 case 3:
49 irq = 11;
50 break;
51 case 5:
52 irq = 9;
53 break;
54 }
55 } else {
56 irq = BONITO_IRQ_BASE + 25 + pin;
57 }
58 return irq;
59
60 }
61
62 /* Do platform specific device initialization at pci_enable_device() time */
pcibios_plat_dev_init(struct pci_dev * dev)63 int pcibios_plat_dev_init(struct pci_dev *dev)
64 {
65 return 0;
66 }
67
loongson2e_nec_fixup(struct pci_dev * pdev)68 static void __init loongson2e_nec_fixup(struct pci_dev *pdev)
69 {
70 unsigned int val;
71
72 /* Configues port 1, 2, 3, 4 to be validate*/
73 pci_read_config_dword(pdev, 0xe0, &val);
74 pci_write_config_dword(pdev, 0xe0, (val & ~7) | 0x4);
75
76 /* System clock is 48-MHz Oscillator. */
77 pci_write_config_dword(pdev, 0xe4, 1 << 5);
78 }
79
loongson2e_686b_func0_fixup(struct pci_dev * pdev)80 static void __init loongson2e_686b_func0_fixup(struct pci_dev *pdev)
81 {
82 unsigned char c;
83
84 sb_slot = PCI_SLOT(pdev->devfn);
85
86 printk(KERN_INFO "via686b fix: ISA bridge\n");
87
88 /* Enable I/O Recovery time */
89 pci_write_config_byte(pdev, 0x40, 0x08);
90
91 /* Enable ISA refresh */
92 pci_write_config_byte(pdev, 0x41, 0x01);
93
94 /* disable ISA line buffer */
95 pci_write_config_byte(pdev, 0x45, 0x00);
96
97 /* Gate INTR, and flush line buffer */
98 pci_write_config_byte(pdev, 0x46, 0xe0);
99
100 /* Disable PCI Delay Transaction, Enable EISA ports 4D0/4D1. */
101 /* pci_write_config_byte(pdev, 0x47, 0x20); */
102
103 /*
104 * enable PCI Delay Transaction, Enable EISA ports 4D0/4D1.
105 * enable time-out timer
106 */
107 pci_write_config_byte(pdev, 0x47, 0xe6);
108
109 /*
110 * enable level trigger on pci irqs: 9,10,11,13
111 * important! without this PCI interrupts won't work
112 */
113 outb(0x2e, 0x4d1);
114
115 /* 512 K PCI Decode */
116 pci_write_config_byte(pdev, 0x48, 0x01);
117
118 /* Wait for PGNT before grant to ISA Master/DMA */
119 pci_write_config_byte(pdev, 0x4a, 0x84);
120
121 /*
122 * Plug'n'Play
123 *
124 * Parallel DRQ 3, Floppy DRQ 2 (default)
125 */
126 pci_write_config_byte(pdev, 0x50, 0x0e);
127
128 /*
129 * IRQ Routing for Floppy and Parallel port
130 *
131 * IRQ 6 for floppy, IRQ 7 for parallel port
132 */
133 pci_write_config_byte(pdev, 0x51, 0x76);
134
135 /* IRQ Routing for serial ports (take IRQ 3 and 4) */
136 pci_write_config_byte(pdev, 0x52, 0x34);
137
138 /* All IRQ's level triggered. */
139 pci_write_config_byte(pdev, 0x54, 0x00);
140
141 /* route PIRQA-D irq */
142 pci_write_config_byte(pdev, 0x55, 0x90); /* bit 7-4, PIRQA */
143 pci_write_config_byte(pdev, 0x56, 0xba); /* bit 7-4, PIRQC; */
144 /* 3-0, PIRQB */
145 pci_write_config_byte(pdev, 0x57, 0xd0); /* bit 7-4, PIRQD */
146
147 /* enable function 5/6, audio/modem */
148 pci_read_config_byte(pdev, 0x85, &c);
149 c &= ~(0x3 << 2);
150 pci_write_config_byte(pdev, 0x85, c);
151
152 printk(KERN_INFO"via686b fix: ISA bridge done\n");
153 }
154
loongson2e_686b_func1_fixup(struct pci_dev * pdev)155 static void __init loongson2e_686b_func1_fixup(struct pci_dev *pdev)
156 {
157 printk(KERN_INFO"via686b fix: IDE\n");
158
159 /* Modify IDE controller setup */
160 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 48);
161 pci_write_config_byte(pdev, PCI_COMMAND,
162 PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
163 PCI_COMMAND_MASTER);
164 pci_write_config_byte(pdev, 0x40, 0x0b);
165 /* legacy mode */
166 pci_write_config_byte(pdev, 0x42, 0x09);
167
168 #if 1/* play safe, otherwise we may see notebook's usb keyboard lockup */
169 /* disable read prefetch/write post buffers */
170 pci_write_config_byte(pdev, 0x41, 0x02);
171
172 /* use 3/4 as fifo thresh hold */
173 pci_write_config_byte(pdev, 0x43, 0x0a);
174 pci_write_config_byte(pdev, 0x44, 0x00);
175
176 pci_write_config_byte(pdev, 0x45, 0x00);
177 #else
178 pci_write_config_byte(pdev, 0x41, 0xc2);
179 pci_write_config_byte(pdev, 0x43, 0x35);
180 pci_write_config_byte(pdev, 0x44, 0x1c);
181
182 pci_write_config_byte(pdev, 0x45, 0x10);
183 #endif
184
185 printk(KERN_INFO"via686b fix: IDE done\n");
186 }
187
loongson2e_686b_func2_fixup(struct pci_dev * pdev)188 static void __init loongson2e_686b_func2_fixup(struct pci_dev *pdev)
189 {
190 /* irq routing */
191 pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, 10);
192 }
193
loongson2e_686b_func3_fixup(struct pci_dev * pdev)194 static void __init loongson2e_686b_func3_fixup(struct pci_dev *pdev)
195 {
196 /* irq routing */
197 pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, 11);
198 }
199
loongson2e_686b_func5_fixup(struct pci_dev * pdev)200 static void __init loongson2e_686b_func5_fixup(struct pci_dev *pdev)
201 {
202 unsigned int val;
203 unsigned char c;
204
205 /* enable IO */
206 pci_write_config_byte(pdev, PCI_COMMAND,
207 PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
208 PCI_COMMAND_MASTER);
209 pci_read_config_dword(pdev, 0x4, &val);
210 pci_write_config_dword(pdev, 0x4, val | 1);
211
212 /* route ac97 IRQ */
213 pci_write_config_byte(pdev, 0x3c, 9);
214
215 pci_read_config_byte(pdev, 0x8, &c);
216
217 /* link control: enable link & SGD PCM output */
218 pci_write_config_byte(pdev, 0x41, 0xcc);
219
220 /* disable game port, FM, midi, sb, enable write to reg2c-2f */
221 pci_write_config_byte(pdev, 0x42, 0x20);
222
223 /* we are using Avance logic codec */
224 pci_write_config_word(pdev, 0x2c, 0x1005);
225 pci_write_config_word(pdev, 0x2e, 0x4710);
226 pci_read_config_dword(pdev, 0x2c, &val);
227
228 pci_write_config_byte(pdev, 0x42, 0x0);
229 }
230
231 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686,
232 loongson2e_686b_func0_fixup);
233 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1,
234 loongson2e_686b_func1_fixup);
235 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2,
236 loongson2e_686b_func2_fixup);
237 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3,
238 loongson2e_686b_func3_fixup);
239 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_5,
240 loongson2e_686b_func5_fixup);
241 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_USB,
242 loongson2e_nec_fixup);
243