1 /*
2 * Setting up the clock on MSP SOCs. No RTC typically.
3 *
4 * Carsten Langgaard, carstenl@mips.com
5 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
6 *
7 * ########################################################################
8 *
9 * This program is free software; you can distribute it and/or modify it
10 * under the terms of the GNU General Public License (Version 2) as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
21 *
22 * ########################################################################
23 */
24
25 #include <linux/init.h>
26 #include <linux/kernel_stat.h>
27 #include <linux/sched.h>
28 #include <linux/spinlock.h>
29 #include <linux/module.h>
30 #include <linux/ptrace.h>
31
32 #include <asm/mipsregs.h>
33 #include <asm/time.h>
34
35 #include <msp_prom.h>
36 #include <msp_int.h>
37 #include <msp_regs.h>
38
plat_time_init(void)39 void __init plat_time_init(void)
40 {
41 char *endp, *s;
42 unsigned long cpu_rate = 0;
43
44 if (cpu_rate == 0) {
45 s = prom_getenv("clkfreqhz");
46 cpu_rate = simple_strtoul(s, &endp, 10);
47 if (endp != NULL && *endp != 0) {
48 printk(KERN_ERR
49 "Clock rate in Hz parse error: %s\n", s);
50 cpu_rate = 0;
51 }
52 }
53
54 if (cpu_rate == 0) {
55 s = prom_getenv("clkfreq");
56 cpu_rate = 1000 * simple_strtoul(s, &endp, 10);
57 if (endp != NULL && *endp != 0) {
58 printk(KERN_ERR
59 "Clock rate in MHz parse error: %s\n", s);
60 cpu_rate = 0;
61 }
62 }
63
64 if (cpu_rate == 0) {
65 #if defined(CONFIG_PMC_MSP7120_EVAL) \
66 || defined(CONFIG_PMC_MSP7120_GW)
67 cpu_rate = 400000000;
68 #elif defined(CONFIG_PMC_MSP7120_FPGA)
69 cpu_rate = 25000000;
70 #else
71 cpu_rate = 150000000;
72 #endif
73 printk(KERN_ERR
74 "Failed to determine CPU clock rate, "
75 "assuming %ld hz ...\n", cpu_rate);
76 }
77
78 printk(KERN_WARNING "Clock rate set to %ld\n", cpu_rate);
79
80 /* timer frequency is 1/2 clock rate */
81 mips_hpt_frequency = cpu_rate/2;
82 }
83
plat_timer_setup(struct irqaction * irq)84 void __init plat_timer_setup(struct irqaction *irq)
85 {
86 #ifdef CONFIG_IRQ_MSP_CIC
87 /* we are using the vpe0 counter for timer interrupts */
88 setup_irq(MSP_INT_VPE0_TIMER, irq);
89 #endif
90 }
91