1 /*
2 * Copyright 2001 MontaVista Software Inc.
3 * Author: MontaVista Software, Inc.
4 * ahennessy@mvista.com
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 *
10 * Copyright (C) 2000-2001 Toshiba Corporation
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 *
17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
18 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
23 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
24 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * You should have received a copy of the GNU General Public License along
29 * with this program; if not, write to the Free Software Foundation, Inc.,
30 * 675 Mass Ave, Cambridge, MA 02139, USA.
31 */
32 #include <linux/init.h>
33 #include <linux/types.h>
34 #include <linux/interrupt.h>
35
36 #include <asm/io.h>
37 #include <asm/mipsregs.h>
38 #include <asm/txx9/generic.h>
39 #include <asm/txx9/jmr3927.h>
40
41 #if JMR3927_IRQ_END > NR_IRQS
42 #error JMR3927_IRQ_END > NR_IRQS
43 #endif
44
45 /*
46 * CP0_STATUS is a thread's resource (saved/restored on context switch).
47 * So disable_irq/enable_irq MUST handle IOC/IRC registers.
48 */
mask_irq_ioc(unsigned int irq)49 static void mask_irq_ioc(unsigned int irq)
50 {
51 /* 0: mask */
52 unsigned int irq_nr = irq - JMR3927_IRQ_IOC;
53 unsigned char imask = jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR);
54 unsigned int bit = 1 << irq_nr;
55 jmr3927_ioc_reg_out(imask & ~bit, JMR3927_IOC_INTM_ADDR);
56 /* flush write buffer */
57 (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
58 }
unmask_irq_ioc(unsigned int irq)59 static void unmask_irq_ioc(unsigned int irq)
60 {
61 /* 0: mask */
62 unsigned int irq_nr = irq - JMR3927_IRQ_IOC;
63 unsigned char imask = jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR);
64 unsigned int bit = 1 << irq_nr;
65 jmr3927_ioc_reg_out(imask | bit, JMR3927_IOC_INTM_ADDR);
66 /* flush write buffer */
67 (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
68 }
69
jmr3927_ioc_irqroute(void)70 static int jmr3927_ioc_irqroute(void)
71 {
72 unsigned char istat = jmr3927_ioc_reg_in(JMR3927_IOC_INTS2_ADDR);
73 int i;
74
75 for (i = 0; i < JMR3927_NR_IRQ_IOC; i++) {
76 if (istat & (1 << i))
77 return JMR3927_IRQ_IOC + i;
78 }
79 return -1;
80 }
81
jmr3927_irq_dispatch(int pending)82 static int jmr3927_irq_dispatch(int pending)
83 {
84 int irq;
85
86 if ((pending & CAUSEF_IP7) == 0)
87 return -1;
88 irq = (pending >> CAUSEB_IP2) & 0x0f;
89 irq += JMR3927_IRQ_IRC;
90 if (irq == JMR3927_IRQ_IOCINT)
91 irq = jmr3927_ioc_irqroute();
92 return irq;
93 }
94
95 static struct irq_chip jmr3927_irq_ioc = {
96 .name = "jmr3927_ioc",
97 .ack = mask_irq_ioc,
98 .mask = mask_irq_ioc,
99 .mask_ack = mask_irq_ioc,
100 .unmask = unmask_irq_ioc,
101 };
102
jmr3927_irq_setup(void)103 void __init jmr3927_irq_setup(void)
104 {
105 int i;
106
107 txx9_irq_dispatch = jmr3927_irq_dispatch;
108 /* Now, interrupt control disabled, */
109 /* all IRC interrupts are masked, */
110 /* all IRC interrupt mode are Low Active. */
111
112 /* mask all IOC interrupts */
113 jmr3927_ioc_reg_out(0, JMR3927_IOC_INTM_ADDR);
114 /* setup IOC interrupt mode (SOFT:High Active, Others:Low Active) */
115 jmr3927_ioc_reg_out(JMR3927_IOC_INTF_SOFT, JMR3927_IOC_INTP_ADDR);
116
117 /* clear PCI Soft interrupts */
118 jmr3927_ioc_reg_out(0, JMR3927_IOC_INTS1_ADDR);
119 /* clear PCI Reset interrupts */
120 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
121
122 tx3927_irq_init();
123 for (i = JMR3927_IRQ_IOC; i < JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC; i++)
124 set_irq_chip_and_handler(i, &jmr3927_irq_ioc, handle_level_irq);
125
126 /* setup IOC interrupt 1 (PCI, MODEM) */
127 set_irq_chained_handler(JMR3927_IRQ_IOCINT, handle_simple_irq);
128 }
129