1/* 2 * MPC8360E EMDS Device Tree Source 3 * 4 * Copyright 2006 Freescale Semiconductor Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 */ 11 12 13/* 14/memreserve/ 00000000 1000000; 15*/ 16 17/dts-v1/; 18 19/ { 20 model = "MPC8360MDS"; 21 compatible = "MPC8360EMDS", "MPC836xMDS", "MPC83xxMDS"; 22 #address-cells = <1>; 23 #size-cells = <1>; 24 25 aliases { 26 ethernet0 = &enet0; 27 ethernet1 = &enet1; 28 serial0 = &serial0; 29 serial1 = &serial1; 30 pci0 = &pci0; 31 }; 32 33 cpus { 34 #address-cells = <1>; 35 #size-cells = <0>; 36 37 PowerPC,8360@0 { 38 device_type = "cpu"; 39 reg = <0x0>; 40 d-cache-line-size = <32>; // 32 bytes 41 i-cache-line-size = <32>; // 32 bytes 42 d-cache-size = <32768>; // L1, 32K 43 i-cache-size = <32768>; // L1, 32K 44 timebase-frequency = <66000000>; 45 bus-frequency = <264000000>; 46 clock-frequency = <528000000>; 47 }; 48 }; 49 50 memory { 51 device_type = "memory"; 52 reg = <0x00000000 0x10000000>; 53 }; 54 55 localbus@e0005000 { 56 #address-cells = <2>; 57 #size-cells = <1>; 58 compatible = "fsl,mpc8360-localbus", "fsl,pq2pro-localbus", 59 "simple-bus"; 60 reg = <0xe0005000 0xd8>; 61 ranges = <0 0 0xfe000000 0x02000000 62 1 0 0xf8000000 0x00008000>; 63 64 flash@0,0 { 65 compatible = "cfi-flash"; 66 reg = <0 0 0x2000000>; 67 bank-width = <2>; 68 device-width = <1>; 69 }; 70 71 bcsr@1,0 { 72 #address-cells = <1>; 73 #size-cells = <1>; 74 compatible = "fsl,mpc8360mds-bcsr"; 75 reg = <1 0 0x8000>; 76 ranges = <0 1 0 0x8000>; 77 78 bcsr13: gpio-controller@d { 79 #gpio-cells = <2>; 80 compatible = "fsl,mpc8360mds-bcsr-gpio"; 81 reg = <0xd 1>; 82 gpio-controller; 83 }; 84 }; 85 }; 86 87 soc8360@e0000000 { 88 #address-cells = <1>; 89 #size-cells = <1>; 90 device_type = "soc"; 91 compatible = "simple-bus"; 92 ranges = <0x0 0xe0000000 0x00100000>; 93 reg = <0xe0000000 0x00000200>; 94 bus-frequency = <264000000>; 95 96 wdt@200 { 97 device_type = "watchdog"; 98 compatible = "mpc83xx_wdt"; 99 reg = <0x200 0x100>; 100 }; 101 102 i2c@3000 { 103 #address-cells = <1>; 104 #size-cells = <0>; 105 cell-index = <0>; 106 compatible = "fsl-i2c"; 107 reg = <0x3000 0x100>; 108 interrupts = <14 0x8>; 109 interrupt-parent = <&ipic>; 110 dfsrr; 111 112 rtc@68 { 113 compatible = "dallas,ds1374"; 114 reg = <0x68>; 115 }; 116 }; 117 118 i2c@3100 { 119 #address-cells = <1>; 120 #size-cells = <0>; 121 cell-index = <1>; 122 compatible = "fsl-i2c"; 123 reg = <0x3100 0x100>; 124 interrupts = <15 0x8>; 125 interrupt-parent = <&ipic>; 126 dfsrr; 127 }; 128 129 serial0: serial@4500 { 130 cell-index = <0>; 131 device_type = "serial"; 132 compatible = "ns16550"; 133 reg = <0x4500 0x100>; 134 clock-frequency = <264000000>; 135 interrupts = <9 0x8>; 136 interrupt-parent = <&ipic>; 137 }; 138 139 serial1: serial@4600 { 140 cell-index = <1>; 141 device_type = "serial"; 142 compatible = "ns16550"; 143 reg = <0x4600 0x100>; 144 clock-frequency = <264000000>; 145 interrupts = <10 0x8>; 146 interrupt-parent = <&ipic>; 147 }; 148 149 dma@82a8 { 150 #address-cells = <1>; 151 #size-cells = <1>; 152 compatible = "fsl,mpc8360-dma", "fsl,elo-dma"; 153 reg = <0x82a8 4>; 154 ranges = <0 0x8100 0x1a8>; 155 interrupt-parent = <&ipic>; 156 interrupts = <71 8>; 157 cell-index = <0>; 158 dma-channel@0 { 159 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; 160 reg = <0 0x80>; 161 cell-index = <0>; 162 interrupt-parent = <&ipic>; 163 interrupts = <71 8>; 164 }; 165 dma-channel@80 { 166 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; 167 reg = <0x80 0x80>; 168 cell-index = <1>; 169 interrupt-parent = <&ipic>; 170 interrupts = <71 8>; 171 }; 172 dma-channel@100 { 173 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; 174 reg = <0x100 0x80>; 175 cell-index = <2>; 176 interrupt-parent = <&ipic>; 177 interrupts = <71 8>; 178 }; 179 dma-channel@180 { 180 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; 181 reg = <0x180 0x28>; 182 cell-index = <3>; 183 interrupt-parent = <&ipic>; 184 interrupts = <71 8>; 185 }; 186 }; 187 188 crypto@30000 { 189 compatible = "fsl,sec2.0"; 190 reg = <0x30000 0x10000>; 191 interrupts = <11 0x8>; 192 interrupt-parent = <&ipic>; 193 fsl,num-channels = <4>; 194 fsl,channel-fifo-len = <24>; 195 fsl,exec-units-mask = <0x7e>; 196 fsl,descriptor-types-mask = <0x01010ebf>; 197 }; 198 199 ipic: pic@700 { 200 interrupt-controller; 201 #address-cells = <0>; 202 #interrupt-cells = <2>; 203 reg = <0x700 0x100>; 204 device_type = "ipic"; 205 }; 206 207 par_io@1400 { 208 #address-cells = <1>; 209 #size-cells = <1>; 210 reg = <0x1400 0x100>; 211 ranges = <0 0x1400 0x100>; 212 device_type = "par_io"; 213 num-ports = <7>; 214 215 qe_pio_b: gpio-controller@18 { 216 #gpio-cells = <2>; 217 compatible = "fsl,mpc8360-qe-pario-bank", 218 "fsl,mpc8323-qe-pario-bank"; 219 reg = <0x18 0x18>; 220 gpio-controller; 221 }; 222 223 pio1: ucc_pin@01 { 224 pio-map = < 225 /* port pin dir open_drain assignment has_irq */ 226 0 3 1 0 1 0 /* TxD0 */ 227 0 4 1 0 1 0 /* TxD1 */ 228 0 5 1 0 1 0 /* TxD2 */ 229 0 6 1 0 1 0 /* TxD3 */ 230 1 6 1 0 3 0 /* TxD4 */ 231 1 7 1 0 1 0 /* TxD5 */ 232 1 9 1 0 2 0 /* TxD6 */ 233 1 10 1 0 2 0 /* TxD7 */ 234 0 9 2 0 1 0 /* RxD0 */ 235 0 10 2 0 1 0 /* RxD1 */ 236 0 11 2 0 1 0 /* RxD2 */ 237 0 12 2 0 1 0 /* RxD3 */ 238 0 13 2 0 1 0 /* RxD4 */ 239 1 1 2 0 2 0 /* RxD5 */ 240 1 0 2 0 2 0 /* RxD6 */ 241 1 4 2 0 2 0 /* RxD7 */ 242 0 7 1 0 1 0 /* TX_EN */ 243 0 8 1 0 1 0 /* TX_ER */ 244 0 15 2 0 1 0 /* RX_DV */ 245 0 16 2 0 1 0 /* RX_ER */ 246 0 0 2 0 1 0 /* RX_CLK */ 247 2 9 1 0 3 0 /* GTX_CLK - CLK10 */ 248 2 8 2 0 1 0>; /* GTX125 - CLK9 */ 249 }; 250 pio2: ucc_pin@02 { 251 pio-map = < 252 /* port pin dir open_drain assignment has_irq */ 253 0 17 1 0 1 0 /* TxD0 */ 254 0 18 1 0 1 0 /* TxD1 */ 255 0 19 1 0 1 0 /* TxD2 */ 256 0 20 1 0 1 0 /* TxD3 */ 257 1 2 1 0 1 0 /* TxD4 */ 258 1 3 1 0 2 0 /* TxD5 */ 259 1 5 1 0 3 0 /* TxD6 */ 260 1 8 1 0 3 0 /* TxD7 */ 261 0 23 2 0 1 0 /* RxD0 */ 262 0 24 2 0 1 0 /* RxD1 */ 263 0 25 2 0 1 0 /* RxD2 */ 264 0 26 2 0 1 0 /* RxD3 */ 265 0 27 2 0 1 0 /* RxD4 */ 266 1 12 2 0 2 0 /* RxD5 */ 267 1 13 2 0 3 0 /* RxD6 */ 268 1 11 2 0 2 0 /* RxD7 */ 269 0 21 1 0 1 0 /* TX_EN */ 270 0 22 1 0 1 0 /* TX_ER */ 271 0 29 2 0 1 0 /* RX_DV */ 272 0 30 2 0 1 0 /* RX_ER */ 273 0 31 2 0 1 0 /* RX_CLK */ 274 2 2 1 0 2 0 /* GTX_CLK - CLK10 */ 275 2 3 2 0 1 0 /* GTX125 - CLK4 */ 276 0 1 3 0 2 0 /* MDIO */ 277 0 2 1 0 1 0>; /* MDC */ 278 }; 279 280 }; 281 }; 282 283 qe@e0100000 { 284 #address-cells = <1>; 285 #size-cells = <1>; 286 device_type = "qe"; 287 compatible = "fsl,qe"; 288 ranges = <0x0 0xe0100000 0x00100000>; 289 reg = <0xe0100000 0x480>; 290 brg-frequency = <0>; 291 bus-frequency = <396000000>; 292 293 muram@10000 { 294 #address-cells = <1>; 295 #size-cells = <1>; 296 compatible = "fsl,qe-muram", "fsl,cpm-muram"; 297 ranges = <0x0 0x00010000 0x0000c000>; 298 299 data-only@0 { 300 compatible = "fsl,qe-muram-data", 301 "fsl,cpm-muram-data"; 302 reg = <0x0 0xc000>; 303 }; 304 }; 305 306 timer@440 { 307 compatible = "fsl,mpc8360-qe-gtm", 308 "fsl,qe-gtm", "fsl,gtm"; 309 reg = <0x440 0x40>; 310 clock-frequency = <132000000>; 311 interrupts = <12 13 14 15>; 312 interrupt-parent = <&qeic>; 313 }; 314 315 spi@4c0 { 316 cell-index = <0>; 317 compatible = "fsl,spi"; 318 reg = <0x4c0 0x40>; 319 interrupts = <2>; 320 interrupt-parent = <&qeic>; 321 mode = "cpu"; 322 }; 323 324 spi@500 { 325 cell-index = <1>; 326 compatible = "fsl,spi"; 327 reg = <0x500 0x40>; 328 interrupts = <1>; 329 interrupt-parent = <&qeic>; 330 mode = "cpu"; 331 }; 332 333 usb@6c0 { 334 compatible = "fsl,mpc8360-qe-usb", 335 "fsl,mpc8323-qe-usb"; 336 reg = <0x6c0 0x40 0x8b00 0x100>; 337 interrupts = <11>; 338 interrupt-parent = <&qeic>; 339 fsl,fullspeed-clock = "clk21"; 340 fsl,lowspeed-clock = "brg9"; 341 gpios = <&qe_pio_b 2 0 /* USBOE */ 342 &qe_pio_b 3 0 /* USBTP */ 343 &qe_pio_b 8 0 /* USBTN */ 344 &qe_pio_b 9 0 /* USBRP */ 345 &qe_pio_b 11 0 /* USBRN */ 346 &bcsr13 5 0 /* SPEED */ 347 &bcsr13 4 1>; /* POWER */ 348 }; 349 350 enet0: ucc@2000 { 351 device_type = "network"; 352 compatible = "ucc_geth"; 353 cell-index = <1>; 354 reg = <0x2000 0x200>; 355 interrupts = <32>; 356 interrupt-parent = <&qeic>; 357 local-mac-address = [ 00 00 00 00 00 00 ]; 358 rx-clock-name = "none"; 359 tx-clock-name = "clk9"; 360 phy-handle = <&phy0>; 361 phy-connection-type = "rgmii-id"; 362 pio-handle = <&pio1>; 363 }; 364 365 enet1: ucc@3000 { 366 device_type = "network"; 367 compatible = "ucc_geth"; 368 cell-index = <2>; 369 reg = <0x3000 0x200>; 370 interrupts = <33>; 371 interrupt-parent = <&qeic>; 372 local-mac-address = [ 00 00 00 00 00 00 ]; 373 rx-clock-name = "none"; 374 tx-clock-name = "clk4"; 375 phy-handle = <&phy1>; 376 phy-connection-type = "rgmii-id"; 377 pio-handle = <&pio2>; 378 }; 379 380 mdio@2120 { 381 #address-cells = <1>; 382 #size-cells = <0>; 383 reg = <0x2120 0x18>; 384 compatible = "fsl,ucc-mdio"; 385 386 phy0: ethernet-phy@00 { 387 interrupt-parent = <&ipic>; 388 interrupts = <17 0x8>; 389 reg = <0x0>; 390 device_type = "ethernet-phy"; 391 }; 392 phy1: ethernet-phy@01 { 393 interrupt-parent = <&ipic>; 394 interrupts = <18 0x8>; 395 reg = <0x1>; 396 device_type = "ethernet-phy"; 397 }; 398 }; 399 400 qeic: interrupt-controller@80 { 401 interrupt-controller; 402 compatible = "fsl,qe-ic"; 403 #address-cells = <0>; 404 #interrupt-cells = <1>; 405 reg = <0x80 0x80>; 406 big-endian; 407 interrupts = <32 0x8 33 0x8>; // high:32 low:33 408 interrupt-parent = <&ipic>; 409 }; 410 }; 411 412 pci0: pci@e0008500 { 413 cell-index = <1>; 414 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 415 interrupt-map = < 416 417 /* IDSEL 0x11 AD17 */ 418 0x8800 0x0 0x0 0x1 &ipic 20 0x8 419 0x8800 0x0 0x0 0x2 &ipic 21 0x8 420 0x8800 0x0 0x0 0x3 &ipic 22 0x8 421 0x8800 0x0 0x0 0x4 &ipic 23 0x8 422 423 /* IDSEL 0x12 AD18 */ 424 0x9000 0x0 0x0 0x1 &ipic 22 0x8 425 0x9000 0x0 0x0 0x2 &ipic 23 0x8 426 0x9000 0x0 0x0 0x3 &ipic 20 0x8 427 0x9000 0x0 0x0 0x4 &ipic 21 0x8 428 429 /* IDSEL 0x13 AD19 */ 430 0x9800 0x0 0x0 0x1 &ipic 23 0x8 431 0x9800 0x0 0x0 0x2 &ipic 20 0x8 432 0x9800 0x0 0x0 0x3 &ipic 21 0x8 433 0x9800 0x0 0x0 0x4 &ipic 22 0x8 434 435 /* IDSEL 0x15 AD21*/ 436 0xa800 0x0 0x0 0x1 &ipic 20 0x8 437 0xa800 0x0 0x0 0x2 &ipic 21 0x8 438 0xa800 0x0 0x0 0x3 &ipic 22 0x8 439 0xa800 0x0 0x0 0x4 &ipic 23 0x8 440 441 /* IDSEL 0x16 AD22*/ 442 0xb000 0x0 0x0 0x1 &ipic 23 0x8 443 0xb000 0x0 0x0 0x2 &ipic 20 0x8 444 0xb000 0x0 0x0 0x3 &ipic 21 0x8 445 0xb000 0x0 0x0 0x4 &ipic 22 0x8 446 447 /* IDSEL 0x17 AD23*/ 448 0xb800 0x0 0x0 0x1 &ipic 22 0x8 449 0xb800 0x0 0x0 0x2 &ipic 23 0x8 450 0xb800 0x0 0x0 0x3 &ipic 20 0x8 451 0xb800 0x0 0x0 0x4 &ipic 21 0x8 452 453 /* IDSEL 0x18 AD24*/ 454 0xc000 0x0 0x0 0x1 &ipic 21 0x8 455 0xc000 0x0 0x0 0x2 &ipic 22 0x8 456 0xc000 0x0 0x0 0x3 &ipic 23 0x8 457 0xc000 0x0 0x0 0x4 &ipic 20 0x8>; 458 interrupt-parent = <&ipic>; 459 interrupts = <66 0x8>; 460 bus-range = <0 0>; 461 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000 462 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000 463 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>; 464 clock-frequency = <66666666>; 465 #interrupt-cells = <1>; 466 #size-cells = <2>; 467 #address-cells = <3>; 468 reg = <0xe0008500 0x100 /* internal registers */ 469 0xe0008300 0x8>; /* config space access registers */ 470 compatible = "fsl,mpc8349-pci"; 471 device_type = "pci"; 472 }; 473}; 474