1/* 2 * MPC8379E MDS Device Tree Source 3 * 4 * Copyright 2007 Freescale Semiconductor Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 */ 11 12/dts-v1/; 13 14/ { 15 model = "fsl,mpc8379emds"; 16 compatible = "fsl,mpc8379emds","fsl,mpc837xmds"; 17 #address-cells = <1>; 18 #size-cells = <1>; 19 20 aliases { 21 ethernet0 = &enet0; 22 ethernet1 = &enet1; 23 serial0 = &serial0; 24 serial1 = &serial1; 25 pci0 = &pci0; 26 }; 27 28 cpus { 29 #address-cells = <1>; 30 #size-cells = <0>; 31 32 PowerPC,8379@0 { 33 device_type = "cpu"; 34 reg = <0x0>; 35 d-cache-line-size = <32>; 36 i-cache-line-size = <32>; 37 d-cache-size = <32768>; 38 i-cache-size = <32768>; 39 timebase-frequency = <0>; 40 bus-frequency = <0>; 41 clock-frequency = <0>; 42 }; 43 }; 44 45 memory { 46 device_type = "memory"; 47 reg = <0x00000000 0x20000000>; // 512MB at 0 48 }; 49 50 localbus@e0005000 { 51 #address-cells = <2>; 52 #size-cells = <1>; 53 compatible = "fsl,mpc8379-elbc", "fsl,elbc", "simple-bus"; 54 reg = <0xe0005000 0x1000>; 55 interrupts = <77 0x8>; 56 interrupt-parent = <&ipic>; 57 58 // booting from NOR flash 59 ranges = <0 0x0 0xfe000000 0x02000000 60 1 0x0 0xf8000000 0x00008000 61 3 0x0 0xe0600000 0x00008000>; 62 63 flash@0,0 { 64 #address-cells = <1>; 65 #size-cells = <1>; 66 compatible = "cfi-flash"; 67 reg = <0 0x0 0x2000000>; 68 bank-width = <2>; 69 device-width = <1>; 70 71 u-boot@0 { 72 reg = <0x0 0x100000>; 73 read-only; 74 }; 75 76 fs@100000 { 77 reg = <0x100000 0x800000>; 78 }; 79 80 kernel@1d00000 { 81 reg = <0x1d00000 0x200000>; 82 }; 83 84 dtb@1f00000 { 85 reg = <0x1f00000 0x100000>; 86 }; 87 }; 88 89 bcsr@1,0 { 90 reg = <1 0x0 0x8000>; 91 compatible = "fsl,mpc837xmds-bcsr"; 92 }; 93 94 nand@3,0 { 95 #address-cells = <1>; 96 #size-cells = <1>; 97 compatible = "fsl,mpc8379-fcm-nand", 98 "fsl,elbc-fcm-nand"; 99 reg = <3 0x0 0x8000>; 100 101 u-boot@0 { 102 reg = <0x0 0x100000>; 103 read-only; 104 }; 105 106 kernel@100000 { 107 reg = <0x100000 0x300000>; 108 }; 109 110 fs@400000 { 111 reg = <0x400000 0x1c00000>; 112 }; 113 }; 114 }; 115 116 soc@e0000000 { 117 #address-cells = <1>; 118 #size-cells = <1>; 119 device_type = "soc"; 120 compatible = "simple-bus"; 121 ranges = <0x0 0xe0000000 0x00100000>; 122 reg = <0xe0000000 0x00000200>; 123 bus-frequency = <0>; 124 125 wdt@200 { 126 compatible = "mpc83xx_wdt"; 127 reg = <0x200 0x100>; 128 }; 129 130 i2c@3000 { 131 #address-cells = <1>; 132 #size-cells = <0>; 133 cell-index = <0>; 134 compatible = "fsl-i2c"; 135 reg = <0x3000 0x100>; 136 interrupts = <14 0x8>; 137 interrupt-parent = <&ipic>; 138 dfsrr; 139 140 rtc@68 { 141 compatible = "dallas,ds1374"; 142 reg = <0x68>; 143 interrupts = <19 0x8>; 144 interrupt-parent = <&ipic>; 145 }; 146 }; 147 148 i2c@3100 { 149 #address-cells = <1>; 150 #size-cells = <0>; 151 cell-index = <1>; 152 compatible = "fsl-i2c"; 153 reg = <0x3100 0x100>; 154 interrupts = <15 0x8>; 155 interrupt-parent = <&ipic>; 156 dfsrr; 157 }; 158 159 spi@7000 { 160 cell-index = <0>; 161 compatible = "fsl,spi"; 162 reg = <0x7000 0x1000>; 163 interrupts = <16 0x8>; 164 interrupt-parent = <&ipic>; 165 mode = "cpu"; 166 }; 167 168 dma@82a8 { 169 #address-cells = <1>; 170 #size-cells = <1>; 171 compatible = "fsl,mpc8379-dma", "fsl,elo-dma"; 172 reg = <0x82a8 4>; 173 ranges = <0 0x8100 0x1a8>; 174 interrupt-parent = <&ipic>; 175 interrupts = <71 8>; 176 cell-index = <0>; 177 dma-channel@0 { 178 compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel"; 179 reg = <0 0x80>; 180 cell-index = <0>; 181 interrupt-parent = <&ipic>; 182 interrupts = <71 8>; 183 }; 184 dma-channel@80 { 185 compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel"; 186 reg = <0x80 0x80>; 187 cell-index = <1>; 188 interrupt-parent = <&ipic>; 189 interrupts = <71 8>; 190 }; 191 dma-channel@100 { 192 compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel"; 193 reg = <0x100 0x80>; 194 cell-index = <2>; 195 interrupt-parent = <&ipic>; 196 interrupts = <71 8>; 197 }; 198 dma-channel@180 { 199 compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel"; 200 reg = <0x180 0x28>; 201 cell-index = <3>; 202 interrupt-parent = <&ipic>; 203 interrupts = <71 8>; 204 }; 205 }; 206 207 usb@23000 { 208 compatible = "fsl-usb2-dr"; 209 reg = <0x23000 0x1000>; 210 #address-cells = <1>; 211 #size-cells = <0>; 212 interrupt-parent = <&ipic>; 213 interrupts = <38 0x8>; 214 dr_mode = "host"; 215 phy_type = "ulpi"; 216 }; 217 218 mdio@24520 { 219 #address-cells = <1>; 220 #size-cells = <0>; 221 compatible = "fsl,gianfar-mdio"; 222 reg = <0x24520 0x20>; 223 phy2: ethernet-phy@2 { 224 interrupt-parent = <&ipic>; 225 interrupts = <17 0x8>; 226 reg = <0x2>; 227 device_type = "ethernet-phy"; 228 }; 229 phy3: ethernet-phy@3 { 230 interrupt-parent = <&ipic>; 231 interrupts = <18 0x8>; 232 reg = <0x3>; 233 device_type = "ethernet-phy"; 234 }; 235 tbi0: tbi-phy@11 { 236 reg = <0x11>; 237 device_type = "tbi-phy"; 238 }; 239 }; 240 241 mdio@25520 { 242 #address-cells = <1>; 243 #size-cells = <0>; 244 compatible = "fsl,gianfar-tbi"; 245 reg = <0x25520 0x20>; 246 247 tbi1: tbi-phy@11 { 248 reg = <0x11>; 249 device_type = "tbi-phy"; 250 }; 251 }; 252 253 enet0: ethernet@24000 { 254 cell-index = <0>; 255 device_type = "network"; 256 model = "eTSEC"; 257 compatible = "gianfar"; 258 reg = <0x24000 0x1000>; 259 local-mac-address = [ 00 00 00 00 00 00 ]; 260 interrupts = <32 0x8 33 0x8 34 0x8>; 261 phy-connection-type = "mii"; 262 interrupt-parent = <&ipic>; 263 tbi-handle = <&tbi0>; 264 phy-handle = <&phy2>; 265 }; 266 267 enet1: ethernet@25000 { 268 cell-index = <1>; 269 device_type = "network"; 270 model = "eTSEC"; 271 compatible = "gianfar"; 272 reg = <0x25000 0x1000>; 273 local-mac-address = [ 00 00 00 00 00 00 ]; 274 interrupts = <35 0x8 36 0x8 37 0x8>; 275 phy-connection-type = "mii"; 276 interrupt-parent = <&ipic>; 277 tbi-handle = <&tbi1>; 278 phy-handle = <&phy3>; 279 }; 280 281 serial0: serial@4500 { 282 cell-index = <0>; 283 device_type = "serial"; 284 compatible = "ns16550"; 285 reg = <0x4500 0x100>; 286 clock-frequency = <0>; 287 interrupts = <9 0x8>; 288 interrupt-parent = <&ipic>; 289 }; 290 291 serial1: serial@4600 { 292 cell-index = <1>; 293 device_type = "serial"; 294 compatible = "ns16550"; 295 reg = <0x4600 0x100>; 296 clock-frequency = <0>; 297 interrupts = <10 0x8>; 298 interrupt-parent = <&ipic>; 299 }; 300 301 crypto@30000 { 302 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2", 303 "fsl,sec2.1", "fsl,sec2.0"; 304 reg = <0x30000 0x10000>; 305 interrupts = <11 0x8>; 306 interrupt-parent = <&ipic>; 307 fsl,num-channels = <4>; 308 fsl,channel-fifo-len = <24>; 309 fsl,exec-units-mask = <0x9fe>; 310 fsl,descriptor-types-mask = <0x3ab0ebf>; 311 }; 312 313 sdhc@2e000 { 314 model = "eSDHC"; 315 compatible = "fsl,esdhc"; 316 reg = <0x2e000 0x1000>; 317 interrupts = <42 0x8>; 318 interrupt-parent = <&ipic>; 319 }; 320 321 sata@18000 { 322 compatible = "fsl,mpc8379-sata", "fsl,pq-sata"; 323 reg = <0x18000 0x1000>; 324 interrupts = <44 0x8>; 325 interrupt-parent = <&ipic>; 326 }; 327 328 sata@19000 { 329 compatible = "fsl,mpc8379-sata", "fsl,pq-sata"; 330 reg = <0x19000 0x1000>; 331 interrupts = <45 0x8>; 332 interrupt-parent = <&ipic>; 333 }; 334 335 sata@1a000 { 336 compatible = "fsl,mpc8379-sata", "fsl,pq-sata"; 337 reg = <0x1a000 0x1000>; 338 interrupts = <46 0x8>; 339 interrupt-parent = <&ipic>; 340 }; 341 342 sata@1b000 { 343 compatible = "fsl,mpc8379-sata", "fsl,pq-sata"; 344 reg = <0x1b000 0x1000>; 345 interrupts = <47 0x8>; 346 interrupt-parent = <&ipic>; 347 }; 348 349 /* IPIC 350 * interrupts cell = <intr #, sense> 351 * sense values match linux IORESOURCE_IRQ_* defines: 352 * sense == 8: Level, low assertion 353 * sense == 2: Edge, high-to-low change 354 */ 355 ipic: pic@700 { 356 compatible = "fsl,ipic"; 357 interrupt-controller; 358 #address-cells = <0>; 359 #interrupt-cells = <2>; 360 reg = <0x700 0x100>; 361 }; 362 }; 363 364 pci0: pci@e0008500 { 365 cell-index = <0>; 366 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 367 interrupt-map = < 368 369 /* IDSEL 0x11 */ 370 0x8800 0x0 0x0 0x1 &ipic 20 0x8 371 0x8800 0x0 0x0 0x2 &ipic 21 0x8 372 0x8800 0x0 0x0 0x3 &ipic 22 0x8 373 0x8800 0x0 0x0 0x4 &ipic 23 0x8 374 375 /* IDSEL 0x12 */ 376 0x9000 0x0 0x0 0x1 &ipic 22 0x8 377 0x9000 0x0 0x0 0x2 &ipic 23 0x8 378 0x9000 0x0 0x0 0x3 &ipic 20 0x8 379 0x9000 0x0 0x0 0x4 &ipic 21 0x8 380 381 /* IDSEL 0x13 */ 382 0x9800 0x0 0x0 0x1 &ipic 23 0x8 383 0x9800 0x0 0x0 0x2 &ipic 20 0x8 384 0x9800 0x0 0x0 0x3 &ipic 21 0x8 385 0x9800 0x0 0x0 0x4 &ipic 22 0x8 386 387 /* IDSEL 0x15 */ 388 0xa800 0x0 0x0 0x1 &ipic 20 0x8 389 0xa800 0x0 0x0 0x2 &ipic 21 0x8 390 0xa800 0x0 0x0 0x3 &ipic 22 0x8 391 0xa800 0x0 0x0 0x4 &ipic 23 0x8 392 393 /* IDSEL 0x16 */ 394 0xb000 0x0 0x0 0x1 &ipic 23 0x8 395 0xb000 0x0 0x0 0x2 &ipic 20 0x8 396 0xb000 0x0 0x0 0x3 &ipic 21 0x8 397 0xb000 0x0 0x0 0x4 &ipic 22 0x8 398 399 /* IDSEL 0x17 */ 400 0xb800 0x0 0x0 0x1 &ipic 22 0x8 401 0xb800 0x0 0x0 0x2 &ipic 23 0x8 402 0xb800 0x0 0x0 0x3 &ipic 20 0x8 403 0xb800 0x0 0x0 0x4 &ipic 21 0x8 404 405 /* IDSEL 0x18 */ 406 0xc000 0x0 0x0 0x1 &ipic 21 0x8 407 0xc000 0x0 0x0 0x2 &ipic 22 0x8 408 0xc000 0x0 0x0 0x3 &ipic 23 0x8 409 0xc000 0x0 0x0 0x4 &ipic 20 0x8>; 410 interrupt-parent = <&ipic>; 411 interrupts = <66 0x8>; 412 bus-range = <0x0 0x0>; 413 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000 414 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000 415 0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>; 416 clock-frequency = <0>; 417 #interrupt-cells = <1>; 418 #size-cells = <2>; 419 #address-cells = <3>; 420 reg = <0xe0008500 0x100 /* internal registers */ 421 0xe0008300 0x8>; /* config space access registers */ 422 compatible = "fsl,mpc8349-pci"; 423 device_type = "pci"; 424 }; 425}; 426