1/* 2 * MPC8555 CDS Device Tree Source 3 * 4 * Copyright 2006, 2008 Freescale Semiconductor Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 */ 11 12/dts-v1/; 13 14/ { 15 model = "MPC8555CDS"; 16 compatible = "MPC8555CDS", "MPC85xxCDS"; 17 #address-cells = <1>; 18 #size-cells = <1>; 19 20 aliases { 21 ethernet0 = &enet0; 22 ethernet1 = &enet1; 23 serial0 = &serial0; 24 serial1 = &serial1; 25 pci0 = &pci0; 26 pci1 = &pci1; 27 }; 28 29 cpus { 30 #address-cells = <1>; 31 #size-cells = <0>; 32 33 PowerPC,8555@0 { 34 device_type = "cpu"; 35 reg = <0x0>; 36 d-cache-line-size = <32>; // 32 bytes 37 i-cache-line-size = <32>; // 32 bytes 38 d-cache-size = <0x8000>; // L1, 32K 39 i-cache-size = <0x8000>; // L1, 32K 40 timebase-frequency = <0>; // 33 MHz, from uboot 41 bus-frequency = <0>; // 166 MHz 42 clock-frequency = <0>; // 825 MHz, from uboot 43 next-level-cache = <&L2>; 44 }; 45 }; 46 47 memory { 48 device_type = "memory"; 49 reg = <0x0 0x8000000>; // 128M at 0x0 50 }; 51 52 soc8555@e0000000 { 53 #address-cells = <1>; 54 #size-cells = <1>; 55 device_type = "soc"; 56 compatible = "simple-bus"; 57 ranges = <0x0 0xe0000000 0x100000>; 58 reg = <0xe0000000 0x1000>; // CCSRBAR 1M 59 bus-frequency = <0>; 60 61 memory-controller@2000 { 62 compatible = "fsl,8555-memory-controller"; 63 reg = <0x2000 0x1000>; 64 interrupt-parent = <&mpic>; 65 interrupts = <18 2>; 66 }; 67 68 L2: l2-cache-controller@20000 { 69 compatible = "fsl,8555-l2-cache-controller"; 70 reg = <0x20000 0x1000>; 71 cache-line-size = <32>; // 32 bytes 72 cache-size = <0x40000>; // L2, 256K 73 interrupt-parent = <&mpic>; 74 interrupts = <16 2>; 75 }; 76 77 i2c@3000 { 78 #address-cells = <1>; 79 #size-cells = <0>; 80 cell-index = <0>; 81 compatible = "fsl-i2c"; 82 reg = <0x3000 0x100>; 83 interrupts = <43 2>; 84 interrupt-parent = <&mpic>; 85 dfsrr; 86 }; 87 88 dma@21300 { 89 #address-cells = <1>; 90 #size-cells = <1>; 91 compatible = "fsl,mpc8555-dma", "fsl,eloplus-dma"; 92 reg = <0x21300 0x4>; 93 ranges = <0x0 0x21100 0x200>; 94 cell-index = <0>; 95 dma-channel@0 { 96 compatible = "fsl,mpc8555-dma-channel", 97 "fsl,eloplus-dma-channel"; 98 reg = <0x0 0x80>; 99 cell-index = <0>; 100 interrupt-parent = <&mpic>; 101 interrupts = <20 2>; 102 }; 103 dma-channel@80 { 104 compatible = "fsl,mpc8555-dma-channel", 105 "fsl,eloplus-dma-channel"; 106 reg = <0x80 0x80>; 107 cell-index = <1>; 108 interrupt-parent = <&mpic>; 109 interrupts = <21 2>; 110 }; 111 dma-channel@100 { 112 compatible = "fsl,mpc8555-dma-channel", 113 "fsl,eloplus-dma-channel"; 114 reg = <0x100 0x80>; 115 cell-index = <2>; 116 interrupt-parent = <&mpic>; 117 interrupts = <22 2>; 118 }; 119 dma-channel@180 { 120 compatible = "fsl,mpc8555-dma-channel", 121 "fsl,eloplus-dma-channel"; 122 reg = <0x180 0x80>; 123 cell-index = <3>; 124 interrupt-parent = <&mpic>; 125 interrupts = <23 2>; 126 }; 127 }; 128 129 mdio@24520 { 130 #address-cells = <1>; 131 #size-cells = <0>; 132 compatible = "fsl,gianfar-mdio"; 133 reg = <0x24520 0x20>; 134 135 phy0: ethernet-phy@0 { 136 interrupt-parent = <&mpic>; 137 interrupts = <5 1>; 138 reg = <0x0>; 139 device_type = "ethernet-phy"; 140 }; 141 phy1: ethernet-phy@1 { 142 interrupt-parent = <&mpic>; 143 interrupts = <5 1>; 144 reg = <0x1>; 145 device_type = "ethernet-phy"; 146 }; 147 tbi0: tbi-phy@11 { 148 reg = <0x11>; 149 device_type = "tbi-phy"; 150 }; 151 }; 152 153 mdio@25520 { 154 #address-cells = <1>; 155 #size-cells = <0>; 156 compatible = "fsl,gianfar-tbi"; 157 reg = <0x25520 0x20>; 158 159 tbi1: tbi-phy@11 { 160 reg = <0x11>; 161 device_type = "tbi-phy"; 162 }; 163 }; 164 165 enet0: ethernet@24000 { 166 cell-index = <0>; 167 device_type = "network"; 168 model = "TSEC"; 169 compatible = "gianfar"; 170 reg = <0x24000 0x1000>; 171 local-mac-address = [ 00 00 00 00 00 00 ]; 172 interrupts = <29 2 30 2 34 2>; 173 interrupt-parent = <&mpic>; 174 tbi-handle = <&tbi0>; 175 phy-handle = <&phy0>; 176 }; 177 178 enet1: ethernet@25000 { 179 cell-index = <1>; 180 device_type = "network"; 181 model = "TSEC"; 182 compatible = "gianfar"; 183 reg = <0x25000 0x1000>; 184 local-mac-address = [ 00 00 00 00 00 00 ]; 185 interrupts = <35 2 36 2 40 2>; 186 interrupt-parent = <&mpic>; 187 tbi-handle = <&tbi1>; 188 phy-handle = <&phy1>; 189 }; 190 191 serial0: serial@4500 { 192 cell-index = <0>; 193 device_type = "serial"; 194 compatible = "ns16550"; 195 reg = <0x4500 0x100>; // reg base, size 196 clock-frequency = <0>; // should we fill in in uboot? 197 interrupts = <42 2>; 198 interrupt-parent = <&mpic>; 199 }; 200 201 serial1: serial@4600 { 202 cell-index = <1>; 203 device_type = "serial"; 204 compatible = "ns16550"; 205 reg = <0x4600 0x100>; // reg base, size 206 clock-frequency = <0>; // should we fill in in uboot? 207 interrupts = <42 2>; 208 interrupt-parent = <&mpic>; 209 }; 210 211 crypto@30000 { 212 compatible = "fsl,sec2.0"; 213 reg = <0x30000 0x10000>; 214 interrupts = <45 2>; 215 interrupt-parent = <&mpic>; 216 fsl,num-channels = <4>; 217 fsl,channel-fifo-len = <24>; 218 fsl,exec-units-mask = <0x7e>; 219 fsl,descriptor-types-mask = <0x01010ebf>; 220 }; 221 222 mpic: pic@40000 { 223 interrupt-controller; 224 #address-cells = <0>; 225 #interrupt-cells = <2>; 226 reg = <0x40000 0x40000>; 227 compatible = "chrp,open-pic"; 228 device_type = "open-pic"; 229 }; 230 231 cpm@919c0 { 232 #address-cells = <1>; 233 #size-cells = <1>; 234 compatible = "fsl,mpc8555-cpm", "fsl,cpm2"; 235 reg = <0x919c0 0x30>; 236 ranges; 237 238 muram@80000 { 239 #address-cells = <1>; 240 #size-cells = <1>; 241 ranges = <0x0 0x80000 0x10000>; 242 243 data@0 { 244 compatible = "fsl,cpm-muram-data"; 245 reg = <0x0 0x2000 0x9000 0x1000>; 246 }; 247 }; 248 249 brg@919f0 { 250 compatible = "fsl,mpc8555-brg", 251 "fsl,cpm2-brg", 252 "fsl,cpm-brg"; 253 reg = <0x919f0 0x10 0x915f0 0x10>; 254 }; 255 256 cpmpic: pic@90c00 { 257 interrupt-controller; 258 #address-cells = <0>; 259 #interrupt-cells = <2>; 260 interrupts = <46 2>; 261 interrupt-parent = <&mpic>; 262 reg = <0x90c00 0x80>; 263 compatible = "fsl,mpc8555-cpm-pic", "fsl,cpm2-pic"; 264 }; 265 }; 266 }; 267 268 pci0: pci@e0008000 { 269 cell-index = <0>; 270 interrupt-map-mask = <0x1f800 0x0 0x0 0x7>; 271 interrupt-map = < 272 273 /* IDSEL 0x10 */ 274 0x8000 0x0 0x0 0x1 &mpic 0x0 0x1 275 0x8000 0x0 0x0 0x2 &mpic 0x1 0x1 276 0x8000 0x0 0x0 0x3 &mpic 0x2 0x1 277 0x8000 0x0 0x0 0x4 &mpic 0x3 0x1 278 279 /* IDSEL 0x11 */ 280 0x8800 0x0 0x0 0x1 &mpic 0x0 0x1 281 0x8800 0x0 0x0 0x2 &mpic 0x1 0x1 282 0x8800 0x0 0x0 0x3 &mpic 0x2 0x1 283 0x8800 0x0 0x0 0x4 &mpic 0x3 0x1 284 285 /* IDSEL 0x12 (Slot 1) */ 286 0x9000 0x0 0x0 0x1 &mpic 0x0 0x1 287 0x9000 0x0 0x0 0x2 &mpic 0x1 0x1 288 0x9000 0x0 0x0 0x3 &mpic 0x2 0x1 289 0x9000 0x0 0x0 0x4 &mpic 0x3 0x1 290 291 /* IDSEL 0x13 (Slot 2) */ 292 0x9800 0x0 0x0 0x1 &mpic 0x1 0x1 293 0x9800 0x0 0x0 0x2 &mpic 0x2 0x1 294 0x9800 0x0 0x0 0x3 &mpic 0x3 0x1 295 0x9800 0x0 0x0 0x4 &mpic 0x0 0x1 296 297 /* IDSEL 0x14 (Slot 3) */ 298 0xa000 0x0 0x0 0x1 &mpic 0x2 0x1 299 0xa000 0x0 0x0 0x2 &mpic 0x3 0x1 300 0xa000 0x0 0x0 0x3 &mpic 0x0 0x1 301 0xa000 0x0 0x0 0x4 &mpic 0x1 0x1 302 303 /* IDSEL 0x15 (Slot 4) */ 304 0xa800 0x0 0x0 0x1 &mpic 0x3 0x1 305 0xa800 0x0 0x0 0x2 &mpic 0x0 0x1 306 0xa800 0x0 0x0 0x3 &mpic 0x1 0x1 307 0xa800 0x0 0x0 0x4 &mpic 0x2 0x1 308 309 /* Bus 1 (Tundra Bridge) */ 310 /* IDSEL 0x12 (ISA bridge) */ 311 0x19000 0x0 0x0 0x1 &mpic 0x0 0x1 312 0x19000 0x0 0x0 0x2 &mpic 0x1 0x1 313 0x19000 0x0 0x0 0x3 &mpic 0x2 0x1 314 0x19000 0x0 0x0 0x4 &mpic 0x3 0x1>; 315 interrupt-parent = <&mpic>; 316 interrupts = <24 2>; 317 bus-range = <0 0>; 318 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000 319 0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>; 320 clock-frequency = <66666666>; 321 #interrupt-cells = <1>; 322 #size-cells = <2>; 323 #address-cells = <3>; 324 reg = <0xe0008000 0x1000>; 325 compatible = "fsl,mpc8540-pci"; 326 device_type = "pci"; 327 328 i8259@19000 { 329 interrupt-controller; 330 device_type = "interrupt-controller"; 331 reg = <0x19000 0x0 0x0 0x0 0x1>; 332 #address-cells = <0>; 333 #interrupt-cells = <2>; 334 compatible = "chrp,iic"; 335 interrupts = <1>; 336 interrupt-parent = <&pci0>; 337 }; 338 }; 339 340 pci1: pci@e0009000 { 341 cell-index = <1>; 342 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 343 interrupt-map = < 344 345 /* IDSEL 0x15 */ 346 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1 347 0xa800 0x0 0x0 0x2 &mpic 0xb 0x1 348 0xa800 0x0 0x0 0x3 &mpic 0xb 0x1 349 0xa800 0x0 0x0 0x4 &mpic 0xb 0x1>; 350 interrupt-parent = <&mpic>; 351 interrupts = <25 2>; 352 bus-range = <0 0>; 353 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000 354 0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>; 355 clock-frequency = <66666666>; 356 #interrupt-cells = <1>; 357 #size-cells = <2>; 358 #address-cells = <3>; 359 reg = <0xe0009000 0x1000>; 360 compatible = "fsl,mpc8540-pci"; 361 device_type = "pci"; 362 }; 363}; 364