1/* 2 * MPC8568E MDS Device Tree Source 3 * 4 * Copyright 2007, 2008 Freescale Semiconductor Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 */ 11 12/dts-v1/; 13 14/ { 15 model = "MPC8568EMDS"; 16 compatible = "MPC8568EMDS", "MPC85xxMDS"; 17 #address-cells = <1>; 18 #size-cells = <1>; 19 20 aliases { 21 ethernet0 = &enet0; 22 ethernet1 = &enet1; 23 ethernet2 = &enet2; 24 ethernet3 = &enet3; 25 serial0 = &serial0; 26 serial1 = &serial1; 27 pci0 = &pci0; 28 pci1 = &pci1; 29 }; 30 31 cpus { 32 #address-cells = <1>; 33 #size-cells = <0>; 34 35 PowerPC,8568@0 { 36 device_type = "cpu"; 37 reg = <0x0>; 38 d-cache-line-size = <32>; // 32 bytes 39 i-cache-line-size = <32>; // 32 bytes 40 d-cache-size = <0x8000>; // L1, 32K 41 i-cache-size = <0x8000>; // L1, 32K 42 timebase-frequency = <0>; 43 bus-frequency = <0>; 44 clock-frequency = <0>; 45 next-level-cache = <&L2>; 46 }; 47 }; 48 49 memory { 50 device_type = "memory"; 51 reg = <0x0 0x10000000>; 52 }; 53 54 bcsr@f8000000 { 55 compatible = "fsl,mpc8568mds-bcsr"; 56 reg = <0xf8000000 0x8000>; 57 }; 58 59 soc8568@e0000000 { 60 #address-cells = <1>; 61 #size-cells = <1>; 62 device_type = "soc"; 63 compatible = "simple-bus"; 64 ranges = <0x0 0xe0000000 0x100000>; 65 reg = <0xe0000000 0x1000>; 66 bus-frequency = <0>; 67 68 memory-controller@2000 { 69 compatible = "fsl,8568-memory-controller"; 70 reg = <0x2000 0x1000>; 71 interrupt-parent = <&mpic>; 72 interrupts = <18 2>; 73 }; 74 75 L2: l2-cache-controller@20000 { 76 compatible = "fsl,8568-l2-cache-controller"; 77 reg = <0x20000 0x1000>; 78 cache-line-size = <32>; // 32 bytes 79 cache-size = <0x80000>; // L2, 512K 80 interrupt-parent = <&mpic>; 81 interrupts = <16 2>; 82 }; 83 84 i2c@3000 { 85 #address-cells = <1>; 86 #size-cells = <0>; 87 cell-index = <0>; 88 compatible = "fsl-i2c"; 89 reg = <0x3000 0x100>; 90 interrupts = <43 2>; 91 interrupt-parent = <&mpic>; 92 dfsrr; 93 94 rtc@68 { 95 compatible = "dallas,ds1374"; 96 reg = <0x68>; 97 }; 98 }; 99 100 i2c@3100 { 101 #address-cells = <1>; 102 #size-cells = <0>; 103 cell-index = <1>; 104 compatible = "fsl-i2c"; 105 reg = <0x3100 0x100>; 106 interrupts = <43 2>; 107 interrupt-parent = <&mpic>; 108 dfsrr; 109 }; 110 111 dma@21300 { 112 #address-cells = <1>; 113 #size-cells = <1>; 114 compatible = "fsl,mpc8568-dma", "fsl,eloplus-dma"; 115 reg = <0x21300 0x4>; 116 ranges = <0x0 0x21100 0x200>; 117 cell-index = <0>; 118 dma-channel@0 { 119 compatible = "fsl,mpc8568-dma-channel", 120 "fsl,eloplus-dma-channel"; 121 reg = <0x0 0x80>; 122 cell-index = <0>; 123 interrupt-parent = <&mpic>; 124 interrupts = <20 2>; 125 }; 126 dma-channel@80 { 127 compatible = "fsl,mpc8568-dma-channel", 128 "fsl,eloplus-dma-channel"; 129 reg = <0x80 0x80>; 130 cell-index = <1>; 131 interrupt-parent = <&mpic>; 132 interrupts = <21 2>; 133 }; 134 dma-channel@100 { 135 compatible = "fsl,mpc8568-dma-channel", 136 "fsl,eloplus-dma-channel"; 137 reg = <0x100 0x80>; 138 cell-index = <2>; 139 interrupt-parent = <&mpic>; 140 interrupts = <22 2>; 141 }; 142 dma-channel@180 { 143 compatible = "fsl,mpc8568-dma-channel", 144 "fsl,eloplus-dma-channel"; 145 reg = <0x180 0x80>; 146 cell-index = <3>; 147 interrupt-parent = <&mpic>; 148 interrupts = <23 2>; 149 }; 150 }; 151 152 mdio@24520 { 153 #address-cells = <1>; 154 #size-cells = <0>; 155 compatible = "fsl,gianfar-mdio"; 156 reg = <0x24520 0x20>; 157 158 phy0: ethernet-phy@7 { 159 interrupt-parent = <&mpic>; 160 interrupts = <1 1>; 161 reg = <0x7>; 162 device_type = "ethernet-phy"; 163 }; 164 phy1: ethernet-phy@1 { 165 interrupt-parent = <&mpic>; 166 interrupts = <2 1>; 167 reg = <0x1>; 168 device_type = "ethernet-phy"; 169 }; 170 phy2: ethernet-phy@2 { 171 interrupt-parent = <&mpic>; 172 interrupts = <1 1>; 173 reg = <0x2>; 174 device_type = "ethernet-phy"; 175 }; 176 phy3: ethernet-phy@3 { 177 interrupt-parent = <&mpic>; 178 interrupts = <2 1>; 179 reg = <0x3>; 180 device_type = "ethernet-phy"; 181 }; 182 tbi0: tbi-phy@11 { 183 reg = <0x11>; 184 device_type = "tbi-phy"; 185 }; 186 }; 187 188 mdio@25520 { 189 #address-cells = <1>; 190 #size-cells = <0>; 191 compatible = "fsl,gianfar-tbi"; 192 reg = <0x25520 0x20>; 193 194 tbi1: tbi-phy@11 { 195 reg = <0x11>; 196 device_type = "tbi-phy"; 197 }; 198 }; 199 200 enet0: ethernet@24000 { 201 cell-index = <0>; 202 device_type = "network"; 203 model = "eTSEC"; 204 compatible = "gianfar"; 205 reg = <0x24000 0x1000>; 206 local-mac-address = [ 00 00 00 00 00 00 ]; 207 interrupts = <29 2 30 2 34 2>; 208 interrupt-parent = <&mpic>; 209 tbi-handle = <&tbi0>; 210 phy-handle = <&phy2>; 211 }; 212 213 enet1: ethernet@25000 { 214 cell-index = <1>; 215 device_type = "network"; 216 model = "eTSEC"; 217 compatible = "gianfar"; 218 reg = <0x25000 0x1000>; 219 local-mac-address = [ 00 00 00 00 00 00 ]; 220 interrupts = <35 2 36 2 40 2>; 221 interrupt-parent = <&mpic>; 222 tbi-handle = <&tbi1>; 223 phy-handle = <&phy3>; 224 }; 225 226 serial0: serial@4500 { 227 cell-index = <0>; 228 device_type = "serial"; 229 compatible = "ns16550"; 230 reg = <0x4500 0x100>; 231 clock-frequency = <0>; 232 interrupts = <42 2>; 233 interrupt-parent = <&mpic>; 234 }; 235 236 global-utilities@e0000 { //global utilities block 237 compatible = "fsl,mpc8548-guts"; 238 reg = <0xe0000 0x1000>; 239 fsl,has-rstcr; 240 }; 241 242 serial1: serial@4600 { 243 cell-index = <1>; 244 device_type = "serial"; 245 compatible = "ns16550"; 246 reg = <0x4600 0x100>; 247 clock-frequency = <0>; 248 interrupts = <42 2>; 249 interrupt-parent = <&mpic>; 250 }; 251 252 crypto@30000 { 253 compatible = "fsl,sec2.1", "fsl,sec2.0"; 254 reg = <0x30000 0x10000>; 255 interrupts = <45 2>; 256 interrupt-parent = <&mpic>; 257 fsl,num-channels = <4>; 258 fsl,channel-fifo-len = <24>; 259 fsl,exec-units-mask = <0xfe>; 260 fsl,descriptor-types-mask = <0x12b0ebf>; 261 }; 262 263 mpic: pic@40000 { 264 interrupt-controller; 265 #address-cells = <0>; 266 #interrupt-cells = <2>; 267 reg = <0x40000 0x40000>; 268 compatible = "chrp,open-pic"; 269 device_type = "open-pic"; 270 }; 271 272 par_io@e0100 { 273 reg = <0xe0100 0x100>; 274 device_type = "par_io"; 275 num-ports = <7>; 276 277 pio1: ucc_pin@01 { 278 pio-map = < 279 /* port pin dir open_drain assignment has_irq */ 280 0x4 0xa 0x1 0x0 0x2 0x0 /* TxD0 */ 281 0x4 0x9 0x1 0x0 0x2 0x0 /* TxD1 */ 282 0x4 0x8 0x1 0x0 0x2 0x0 /* TxD2 */ 283 0x4 0x7 0x1 0x0 0x2 0x0 /* TxD3 */ 284 0x4 0x17 0x1 0x0 0x2 0x0 /* TxD4 */ 285 0x4 0x16 0x1 0x0 0x2 0x0 /* TxD5 */ 286 0x4 0x15 0x1 0x0 0x2 0x0 /* TxD6 */ 287 0x4 0x14 0x1 0x0 0x2 0x0 /* TxD7 */ 288 0x4 0xf 0x2 0x0 0x2 0x0 /* RxD0 */ 289 0x4 0xe 0x2 0x0 0x2 0x0 /* RxD1 */ 290 0x4 0xd 0x2 0x0 0x2 0x0 /* RxD2 */ 291 0x4 0xc 0x2 0x0 0x2 0x0 /* RxD3 */ 292 0x4 0x1d 0x2 0x0 0x2 0x0 /* RxD4 */ 293 0x4 0x1c 0x2 0x0 0x2 0x0 /* RxD5 */ 294 0x4 0x1b 0x2 0x0 0x2 0x0 /* RxD6 */ 295 0x4 0x1a 0x2 0x0 0x2 0x0 /* RxD7 */ 296 0x4 0xb 0x1 0x0 0x2 0x0 /* TX_EN */ 297 0x4 0x18 0x1 0x0 0x2 0x0 /* TX_ER */ 298 0x4 0x10 0x2 0x0 0x2 0x0 /* RX_DV */ 299 0x4 0x1e 0x2 0x0 0x2 0x0 /* RX_ER */ 300 0x4 0x11 0x2 0x0 0x2 0x0 /* RX_CLK */ 301 0x4 0x13 0x1 0x0 0x2 0x0 /* GTX_CLK */ 302 0x1 0x1f 0x2 0x0 0x3 0x0>; /* GTX125 */ 303 }; 304 305 pio2: ucc_pin@02 { 306 pio-map = < 307 /* port pin dir open_drain assignment has_irq */ 308 0x5 0xa 0x1 0x0 0x2 0x0 /* TxD0 */ 309 0x5 0x9 0x1 0x0 0x2 0x0 /* TxD1 */ 310 0x5 0x8 0x1 0x0 0x2 0x0 /* TxD2 */ 311 0x5 0x7 0x1 0x0 0x2 0x0 /* TxD3 */ 312 0x5 0x17 0x1 0x0 0x2 0x0 /* TxD4 */ 313 0x5 0x16 0x1 0x0 0x2 0x0 /* TxD5 */ 314 0x5 0x15 0x1 0x0 0x2 0x0 /* TxD6 */ 315 0x5 0x14 0x1 0x0 0x2 0x0 /* TxD7 */ 316 0x5 0xf 0x2 0x0 0x2 0x0 /* RxD0 */ 317 0x5 0xe 0x2 0x0 0x2 0x0 /* RxD1 */ 318 0x5 0xd 0x2 0x0 0x2 0x0 /* RxD2 */ 319 0x5 0xc 0x2 0x0 0x2 0x0 /* RxD3 */ 320 0x5 0x1d 0x2 0x0 0x2 0x0 /* RxD4 */ 321 0x5 0x1c 0x2 0x0 0x2 0x0 /* RxD5 */ 322 0x5 0x1b 0x2 0x0 0x2 0x0 /* RxD6 */ 323 0x5 0x1a 0x2 0x0 0x2 0x0 /* RxD7 */ 324 0x5 0xb 0x1 0x0 0x2 0x0 /* TX_EN */ 325 0x5 0x18 0x1 0x0 0x2 0x0 /* TX_ER */ 326 0x5 0x10 0x2 0x0 0x2 0x0 /* RX_DV */ 327 0x5 0x1e 0x2 0x0 0x2 0x0 /* RX_ER */ 328 0x5 0x11 0x2 0x0 0x2 0x0 /* RX_CLK */ 329 0x5 0x13 0x1 0x0 0x2 0x0 /* GTX_CLK */ 330 0x1 0x1f 0x2 0x0 0x3 0x0 /* GTX125 */ 331 0x4 0x6 0x3 0x0 0x2 0x0 /* MDIO */ 332 0x4 0x5 0x1 0x0 0x2 0x0>; /* MDC */ 333 }; 334 }; 335 }; 336 337 qe@e0080000 { 338 #address-cells = <1>; 339 #size-cells = <1>; 340 device_type = "qe"; 341 compatible = "fsl,qe"; 342 ranges = <0x0 0xe0080000 0x40000>; 343 reg = <0xe0080000 0x480>; 344 brg-frequency = <0>; 345 bus-frequency = <396000000>; 346 347 muram@10000 { 348 #address-cells = <1>; 349 #size-cells = <1>; 350 compatible = "fsl,qe-muram", "fsl,cpm-muram"; 351 ranges = <0x0 0x10000 0x10000>; 352 353 data-only@0 { 354 compatible = "fsl,qe-muram-data", 355 "fsl,cpm-muram-data"; 356 reg = <0x0 0x10000>; 357 }; 358 }; 359 360 spi@4c0 { 361 cell-index = <0>; 362 compatible = "fsl,spi"; 363 reg = <0x4c0 0x40>; 364 interrupts = <2>; 365 interrupt-parent = <&qeic>; 366 mode = "cpu"; 367 }; 368 369 spi@500 { 370 cell-index = <1>; 371 compatible = "fsl,spi"; 372 reg = <0x500 0x40>; 373 interrupts = <1>; 374 interrupt-parent = <&qeic>; 375 mode = "cpu"; 376 }; 377 378 enet2: ucc@2000 { 379 device_type = "network"; 380 compatible = "ucc_geth"; 381 cell-index = <1>; 382 reg = <0x2000 0x200>; 383 interrupts = <32>; 384 interrupt-parent = <&qeic>; 385 local-mac-address = [ 00 00 00 00 00 00 ]; 386 rx-clock-name = "none"; 387 tx-clock-name = "clk16"; 388 pio-handle = <&pio1>; 389 phy-handle = <&phy0>; 390 phy-connection-type = "rgmii-id"; 391 }; 392 393 enet3: ucc@3000 { 394 device_type = "network"; 395 compatible = "ucc_geth"; 396 cell-index = <2>; 397 reg = <0x3000 0x200>; 398 interrupts = <33>; 399 interrupt-parent = <&qeic>; 400 local-mac-address = [ 00 00 00 00 00 00 ]; 401 rx-clock-name = "none"; 402 tx-clock-name = "clk16"; 403 pio-handle = <&pio2>; 404 phy-handle = <&phy1>; 405 phy-connection-type = "rgmii-id"; 406 }; 407 408 mdio@2120 { 409 #address-cells = <1>; 410 #size-cells = <0>; 411 reg = <0x2120 0x18>; 412 compatible = "fsl,ucc-mdio"; 413 414 /* These are the same PHYs as on 415 * gianfar's MDIO bus */ 416 qe_phy0: ethernet-phy@07 { 417 interrupt-parent = <&mpic>; 418 interrupts = <1 1>; 419 reg = <0x7>; 420 device_type = "ethernet-phy"; 421 }; 422 qe_phy1: ethernet-phy@01 { 423 interrupt-parent = <&mpic>; 424 interrupts = <2 1>; 425 reg = <0x1>; 426 device_type = "ethernet-phy"; 427 }; 428 qe_phy2: ethernet-phy@02 { 429 interrupt-parent = <&mpic>; 430 interrupts = <1 1>; 431 reg = <0x2>; 432 device_type = "ethernet-phy"; 433 }; 434 qe_phy3: ethernet-phy@03 { 435 interrupt-parent = <&mpic>; 436 interrupts = <2 1>; 437 reg = <0x3>; 438 device_type = "ethernet-phy"; 439 }; 440 }; 441 442 qeic: interrupt-controller@80 { 443 interrupt-controller; 444 compatible = "fsl,qe-ic"; 445 #address-cells = <0>; 446 #interrupt-cells = <1>; 447 reg = <0x80 0x80>; 448 big-endian; 449 interrupts = <46 2 46 2>; //high:30 low:30 450 interrupt-parent = <&mpic>; 451 }; 452 453 }; 454 455 pci0: pci@e0008000 { 456 cell-index = <0>; 457 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 458 interrupt-map = < 459 /* IDSEL 0x12 AD18 */ 460 0x9000 0x0 0x0 0x1 &mpic 0x5 0x1 461 0x9000 0x0 0x0 0x2 &mpic 0x6 0x1 462 0x9000 0x0 0x0 0x3 &mpic 0x7 0x1 463 0x9000 0x0 0x0 0x4 &mpic 0x4 0x1 464 465 /* IDSEL 0x13 AD19 */ 466 0x9800 0x0 0x0 0x1 &mpic 0x6 0x1 467 0x9800 0x0 0x0 0x2 &mpic 0x7 0x1 468 0x9800 0x0 0x0 0x3 &mpic 0x4 0x1 469 0x9800 0x0 0x0 0x4 &mpic 0x5 0x1>; 470 471 interrupt-parent = <&mpic>; 472 interrupts = <24 2>; 473 bus-range = <0 255>; 474 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000 475 0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>; 476 clock-frequency = <66666666>; 477 #interrupt-cells = <1>; 478 #size-cells = <2>; 479 #address-cells = <3>; 480 reg = <0xe0008000 0x1000>; 481 compatible = "fsl,mpc8540-pci"; 482 device_type = "pci"; 483 }; 484 485 /* PCI Express */ 486 pci1: pcie@e000a000 { 487 cell-index = <2>; 488 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 489 interrupt-map = < 490 491 /* IDSEL 0x0 (PEX) */ 492 00000 0x0 0x0 0x1 &mpic 0x0 0x1 493 00000 0x0 0x0 0x2 &mpic 0x1 0x1 494 00000 0x0 0x0 0x3 &mpic 0x2 0x1 495 00000 0x0 0x0 0x4 &mpic 0x3 0x1>; 496 497 interrupt-parent = <&mpic>; 498 interrupts = <26 2>; 499 bus-range = <0 255>; 500 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000 501 0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>; 502 clock-frequency = <33333333>; 503 #interrupt-cells = <1>; 504 #size-cells = <2>; 505 #address-cells = <3>; 506 reg = <0xe000a000 0x1000>; 507 compatible = "fsl,mpc8548-pcie"; 508 device_type = "pci"; 509 pcie@0 { 510 reg = <0x0 0x0 0x0 0x0 0x0>; 511 #size-cells = <2>; 512 #address-cells = <3>; 513 device_type = "pci"; 514 ranges = <0x2000000 0x0 0xa0000000 515 0x2000000 0x0 0xa0000000 516 0x0 0x10000000 517 518 0x1000000 0x0 0x0 519 0x1000000 0x0 0x0 520 0x0 0x800000>; 521 }; 522 }; 523}; 524