1/* 2 * MPC8572 DS Device Tree Source 3 * 4 * Copyright 2007, 2008 Freescale Semiconductor Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 */ 11 12/dts-v1/; 13/ { 14 model = "fsl,MPC8572DS"; 15 compatible = "fsl,MPC8572DS"; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 ethernet0 = &enet0; 21 ethernet1 = &enet1; 22 ethernet2 = &enet2; 23 ethernet3 = &enet3; 24 serial0 = &serial0; 25 serial1 = &serial1; 26 pci0 = &pci0; 27 pci1 = &pci1; 28 pci2 = &pci2; 29 }; 30 31 cpus { 32 #address-cells = <1>; 33 #size-cells = <0>; 34 35 PowerPC,8572@0 { 36 device_type = "cpu"; 37 reg = <0x0>; 38 d-cache-line-size = <32>; // 32 bytes 39 i-cache-line-size = <32>; // 32 bytes 40 d-cache-size = <0x8000>; // L1, 32K 41 i-cache-size = <0x8000>; // L1, 32K 42 timebase-frequency = <0>; 43 bus-frequency = <0>; 44 clock-frequency = <0>; 45 next-level-cache = <&L2>; 46 }; 47 48 PowerPC,8572@1 { 49 device_type = "cpu"; 50 reg = <0x1>; 51 d-cache-line-size = <32>; // 32 bytes 52 i-cache-line-size = <32>; // 32 bytes 53 d-cache-size = <0x8000>; // L1, 32K 54 i-cache-size = <0x8000>; // L1, 32K 55 timebase-frequency = <0>; 56 bus-frequency = <0>; 57 clock-frequency = <0>; 58 next-level-cache = <&L2>; 59 }; 60 }; 61 62 memory { 63 device_type = "memory"; 64 }; 65 66 localbus@ffe05000 { 67 #address-cells = <2>; 68 #size-cells = <1>; 69 compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus"; 70 reg = <0 0xffe05000 0 0x1000>; 71 interrupts = <19 2>; 72 interrupt-parent = <&mpic>; 73 74 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000 75 0x1 0x0 0x0 0xe0000000 0x08000000 76 0x2 0x0 0x0 0xffa00000 0x00040000 77 0x3 0x0 0x0 0xffdf0000 0x00008000 78 0x4 0x0 0x0 0xffa40000 0x00040000 79 0x5 0x0 0x0 0xffa80000 0x00040000 80 0x6 0x0 0x0 0xffac0000 0x00040000>; 81 82 nor@0,0 { 83 #address-cells = <1>; 84 #size-cells = <1>; 85 compatible = "cfi-flash"; 86 reg = <0x0 0x0 0x8000000>; 87 bank-width = <2>; 88 device-width = <1>; 89 90 ramdisk@0 { 91 reg = <0x0 0x03000000>; 92 read-only; 93 }; 94 95 diagnostic@3000000 { 96 reg = <0x03000000 0x00e00000>; 97 read-only; 98 }; 99 100 dink@3e00000 { 101 reg = <0x03e00000 0x00200000>; 102 read-only; 103 }; 104 105 kernel@4000000 { 106 reg = <0x04000000 0x00400000>; 107 read-only; 108 }; 109 110 jffs2@4400000 { 111 reg = <0x04400000 0x03b00000>; 112 }; 113 114 dtb@7f00000 { 115 reg = <0x07f00000 0x00080000>; 116 read-only; 117 }; 118 119 u-boot@7f80000 { 120 reg = <0x07f80000 0x00080000>; 121 read-only; 122 }; 123 }; 124 125 nand@2,0 { 126 #address-cells = <1>; 127 #size-cells = <1>; 128 compatible = "fsl,mpc8572-fcm-nand", 129 "fsl,elbc-fcm-nand"; 130 reg = <0x2 0x0 0x40000>; 131 132 u-boot@0 { 133 reg = <0x0 0x02000000>; 134 read-only; 135 }; 136 137 jffs2@2000000 { 138 reg = <0x02000000 0x10000000>; 139 }; 140 141 ramdisk@12000000 { 142 reg = <0x12000000 0x08000000>; 143 read-only; 144 }; 145 146 kernel@1a000000 { 147 reg = <0x1a000000 0x04000000>; 148 }; 149 150 dtb@1e000000 { 151 reg = <0x1e000000 0x01000000>; 152 read-only; 153 }; 154 155 empty@1f000000 { 156 reg = <0x1f000000 0x21000000>; 157 }; 158 }; 159 160 nand@4,0 { 161 compatible = "fsl,mpc8572-fcm-nand", 162 "fsl,elbc-fcm-nand"; 163 reg = <0x4 0x0 0x40000>; 164 }; 165 166 nand@5,0 { 167 compatible = "fsl,mpc8572-fcm-nand", 168 "fsl,elbc-fcm-nand"; 169 reg = <0x5 0x0 0x40000>; 170 }; 171 172 nand@6,0 { 173 compatible = "fsl,mpc8572-fcm-nand", 174 "fsl,elbc-fcm-nand"; 175 reg = <0x6 0x0 0x40000>; 176 }; 177 }; 178 179 soc8572@ffe00000 { 180 #address-cells = <1>; 181 #size-cells = <1>; 182 device_type = "soc"; 183 compatible = "simple-bus"; 184 ranges = <0x0 0 0xffe00000 0x100000>; 185 reg = <0 0xffe00000 0 0x1000>; // CCSRBAR & soc regs, remove once parse code for immrbase fixed 186 bus-frequency = <0>; // Filled out by uboot. 187 188 memory-controller@2000 { 189 compatible = "fsl,mpc8572-memory-controller"; 190 reg = <0x2000 0x1000>; 191 interrupt-parent = <&mpic>; 192 interrupts = <18 2>; 193 }; 194 195 memory-controller@6000 { 196 compatible = "fsl,mpc8572-memory-controller"; 197 reg = <0x6000 0x1000>; 198 interrupt-parent = <&mpic>; 199 interrupts = <18 2>; 200 }; 201 202 L2: l2-cache-controller@20000 { 203 compatible = "fsl,mpc8572-l2-cache-controller"; 204 reg = <0x20000 0x1000>; 205 cache-line-size = <32>; // 32 bytes 206 cache-size = <0x100000>; // L2, 1M 207 interrupt-parent = <&mpic>; 208 interrupts = <16 2>; 209 }; 210 211 i2c@3000 { 212 #address-cells = <1>; 213 #size-cells = <0>; 214 cell-index = <0>; 215 compatible = "fsl-i2c"; 216 reg = <0x3000 0x100>; 217 interrupts = <43 2>; 218 interrupt-parent = <&mpic>; 219 dfsrr; 220 }; 221 222 i2c@3100 { 223 #address-cells = <1>; 224 #size-cells = <0>; 225 cell-index = <1>; 226 compatible = "fsl-i2c"; 227 reg = <0x3100 0x100>; 228 interrupts = <43 2>; 229 interrupt-parent = <&mpic>; 230 dfsrr; 231 }; 232 233 dma@c300 { 234 #address-cells = <1>; 235 #size-cells = <1>; 236 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma"; 237 reg = <0xc300 0x4>; 238 ranges = <0x0 0xc100 0x200>; 239 cell-index = <1>; 240 dma-channel@0 { 241 compatible = "fsl,mpc8572-dma-channel", 242 "fsl,eloplus-dma-channel"; 243 reg = <0x0 0x80>; 244 cell-index = <0>; 245 interrupt-parent = <&mpic>; 246 interrupts = <76 2>; 247 }; 248 dma-channel@80 { 249 compatible = "fsl,mpc8572-dma-channel", 250 "fsl,eloplus-dma-channel"; 251 reg = <0x80 0x80>; 252 cell-index = <1>; 253 interrupt-parent = <&mpic>; 254 interrupts = <77 2>; 255 }; 256 dma-channel@100 { 257 compatible = "fsl,mpc8572-dma-channel", 258 "fsl,eloplus-dma-channel"; 259 reg = <0x100 0x80>; 260 cell-index = <2>; 261 interrupt-parent = <&mpic>; 262 interrupts = <78 2>; 263 }; 264 dma-channel@180 { 265 compatible = "fsl,mpc8572-dma-channel", 266 "fsl,eloplus-dma-channel"; 267 reg = <0x180 0x80>; 268 cell-index = <3>; 269 interrupt-parent = <&mpic>; 270 interrupts = <79 2>; 271 }; 272 }; 273 274 dma@21300 { 275 #address-cells = <1>; 276 #size-cells = <1>; 277 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma"; 278 reg = <0x21300 0x4>; 279 ranges = <0x0 0x21100 0x200>; 280 cell-index = <0>; 281 dma-channel@0 { 282 compatible = "fsl,mpc8572-dma-channel", 283 "fsl,eloplus-dma-channel"; 284 reg = <0x0 0x80>; 285 cell-index = <0>; 286 interrupt-parent = <&mpic>; 287 interrupts = <20 2>; 288 }; 289 dma-channel@80 { 290 compatible = "fsl,mpc8572-dma-channel", 291 "fsl,eloplus-dma-channel"; 292 reg = <0x80 0x80>; 293 cell-index = <1>; 294 interrupt-parent = <&mpic>; 295 interrupts = <21 2>; 296 }; 297 dma-channel@100 { 298 compatible = "fsl,mpc8572-dma-channel", 299 "fsl,eloplus-dma-channel"; 300 reg = <0x100 0x80>; 301 cell-index = <2>; 302 interrupt-parent = <&mpic>; 303 interrupts = <22 2>; 304 }; 305 dma-channel@180 { 306 compatible = "fsl,mpc8572-dma-channel", 307 "fsl,eloplus-dma-channel"; 308 reg = <0x180 0x80>; 309 cell-index = <3>; 310 interrupt-parent = <&mpic>; 311 interrupts = <23 2>; 312 }; 313 }; 314 315 mdio@24520 { 316 #address-cells = <1>; 317 #size-cells = <0>; 318 compatible = "fsl,gianfar-mdio"; 319 reg = <0x24520 0x20>; 320 321 phy0: ethernet-phy@0 { 322 interrupt-parent = <&mpic>; 323 interrupts = <10 1>; 324 reg = <0x0>; 325 }; 326 phy1: ethernet-phy@1 { 327 interrupt-parent = <&mpic>; 328 interrupts = <10 1>; 329 reg = <0x1>; 330 }; 331 phy2: ethernet-phy@2 { 332 interrupt-parent = <&mpic>; 333 interrupts = <10 1>; 334 reg = <0x2>; 335 }; 336 phy3: ethernet-phy@3 { 337 interrupt-parent = <&mpic>; 338 interrupts = <10 1>; 339 reg = <0x3>; 340 }; 341 342 tbi0: tbi-phy@11 { 343 reg = <0x11>; 344 device_type = "tbi-phy"; 345 }; 346 }; 347 348 mdio@25520 { 349 #address-cells = <1>; 350 #size-cells = <0>; 351 compatible = "fsl,gianfar-tbi"; 352 reg = <0x25520 0x20>; 353 354 tbi1: tbi-phy@11 { 355 reg = <0x11>; 356 device_type = "tbi-phy"; 357 }; 358 }; 359 360 mdio@26520 { 361 #address-cells = <1>; 362 #size-cells = <0>; 363 compatible = "fsl,gianfar-tbi"; 364 reg = <0x26520 0x20>; 365 366 tbi2: tbi-phy@11 { 367 reg = <0x11>; 368 device_type = "tbi-phy"; 369 }; 370 }; 371 372 mdio@27520 { 373 #address-cells = <1>; 374 #size-cells = <0>; 375 compatible = "fsl,gianfar-tbi"; 376 reg = <0x27520 0x20>; 377 378 tbi3: tbi-phy@11 { 379 reg = <0x11>; 380 device_type = "tbi-phy"; 381 }; 382 }; 383 384 enet0: ethernet@24000 { 385 cell-index = <0>; 386 device_type = "network"; 387 model = "eTSEC"; 388 compatible = "gianfar"; 389 reg = <0x24000 0x1000>; 390 local-mac-address = [ 00 00 00 00 00 00 ]; 391 interrupts = <29 2 30 2 34 2>; 392 interrupt-parent = <&mpic>; 393 tbi-handle = <&tbi0>; 394 phy-handle = <&phy0>; 395 phy-connection-type = "rgmii-id"; 396 }; 397 398 enet1: ethernet@25000 { 399 cell-index = <1>; 400 device_type = "network"; 401 model = "eTSEC"; 402 compatible = "gianfar"; 403 reg = <0x25000 0x1000>; 404 local-mac-address = [ 00 00 00 00 00 00 ]; 405 interrupts = <35 2 36 2 40 2>; 406 interrupt-parent = <&mpic>; 407 tbi-handle = <&tbi1>; 408 phy-handle = <&phy1>; 409 phy-connection-type = "rgmii-id"; 410 }; 411 412 enet2: ethernet@26000 { 413 cell-index = <2>; 414 device_type = "network"; 415 model = "eTSEC"; 416 compatible = "gianfar"; 417 reg = <0x26000 0x1000>; 418 local-mac-address = [ 00 00 00 00 00 00 ]; 419 interrupts = <31 2 32 2 33 2>; 420 interrupt-parent = <&mpic>; 421 tbi-handle = <&tbi2>; 422 phy-handle = <&phy2>; 423 phy-connection-type = "rgmii-id"; 424 }; 425 426 enet3: ethernet@27000 { 427 cell-index = <3>; 428 device_type = "network"; 429 model = "eTSEC"; 430 compatible = "gianfar"; 431 reg = <0x27000 0x1000>; 432 local-mac-address = [ 00 00 00 00 00 00 ]; 433 interrupts = <37 2 38 2 39 2>; 434 interrupt-parent = <&mpic>; 435 tbi-handle = <&tbi3>; 436 phy-handle = <&phy3>; 437 phy-connection-type = "rgmii-id"; 438 }; 439 440 serial0: serial@4500 { 441 cell-index = <0>; 442 device_type = "serial"; 443 compatible = "ns16550"; 444 reg = <0x4500 0x100>; 445 clock-frequency = <0>; 446 interrupts = <42 2>; 447 interrupt-parent = <&mpic>; 448 }; 449 450 serial1: serial@4600 { 451 cell-index = <1>; 452 device_type = "serial"; 453 compatible = "ns16550"; 454 reg = <0x4600 0x100>; 455 clock-frequency = <0>; 456 interrupts = <42 2>; 457 interrupt-parent = <&mpic>; 458 }; 459 460 global-utilities@e0000 { //global utilities block 461 compatible = "fsl,mpc8572-guts"; 462 reg = <0xe0000 0x1000>; 463 fsl,has-rstcr; 464 }; 465 466 msi@41600 { 467 compatible = "fsl,mpc8572-msi", "fsl,mpic-msi"; 468 reg = <0x41600 0x80>; 469 msi-available-ranges = <0 0x100>; 470 interrupts = < 471 0xe0 0 472 0xe1 0 473 0xe2 0 474 0xe3 0 475 0xe4 0 476 0xe5 0 477 0xe6 0 478 0xe7 0>; 479 interrupt-parent = <&mpic>; 480 }; 481 482 crypto@30000 { 483 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2", 484 "fsl,sec2.1", "fsl,sec2.0"; 485 reg = <0x30000 0x10000>; 486 interrupts = <45 2 58 2>; 487 interrupt-parent = <&mpic>; 488 fsl,num-channels = <4>; 489 fsl,channel-fifo-len = <24>; 490 fsl,exec-units-mask = <0x9fe>; 491 fsl,descriptor-types-mask = <0x3ab0ebf>; 492 }; 493 494 mpic: pic@40000 { 495 interrupt-controller; 496 #address-cells = <0>; 497 #interrupt-cells = <2>; 498 reg = <0x40000 0x40000>; 499 compatible = "chrp,open-pic"; 500 device_type = "open-pic"; 501 }; 502 }; 503 504 pci0: pcie@ffe08000 { 505 cell-index = <0>; 506 compatible = "fsl,mpc8548-pcie"; 507 device_type = "pci"; 508 #interrupt-cells = <1>; 509 #size-cells = <2>; 510 #address-cells = <3>; 511 reg = <0 0xffe08000 0 0x1000>; 512 bus-range = <0 255>; 513 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000 514 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x00010000>; 515 clock-frequency = <33333333>; 516 interrupt-parent = <&mpic>; 517 interrupts = <24 2>; 518 interrupt-map-mask = <0xff00 0x0 0x0 0x7>; 519 interrupt-map = < 520 /* IDSEL 0x11 func 0 - PCI slot 1 */ 521 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1 522 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1 523 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1 524 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1 525 526 /* IDSEL 0x11 func 1 - PCI slot 1 */ 527 0x8900 0x0 0x0 0x1 &mpic 0x2 0x1 528 0x8900 0x0 0x0 0x2 &mpic 0x3 0x1 529 0x8900 0x0 0x0 0x3 &mpic 0x4 0x1 530 0x8900 0x0 0x0 0x4 &mpic 0x1 0x1 531 532 /* IDSEL 0x11 func 2 - PCI slot 1 */ 533 0x8a00 0x0 0x0 0x1 &mpic 0x2 0x1 534 0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1 535 0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1 536 0x8a00 0x0 0x0 0x4 &mpic 0x1 0x1 537 538 /* IDSEL 0x11 func 3 - PCI slot 1 */ 539 0x8b00 0x0 0x0 0x1 &mpic 0x2 0x1 540 0x8b00 0x0 0x0 0x2 &mpic 0x3 0x1 541 0x8b00 0x0 0x0 0x3 &mpic 0x4 0x1 542 0x8b00 0x0 0x0 0x4 &mpic 0x1 0x1 543 544 /* IDSEL 0x11 func 4 - PCI slot 1 */ 545 0x8c00 0x0 0x0 0x1 &mpic 0x2 0x1 546 0x8c00 0x0 0x0 0x2 &mpic 0x3 0x1 547 0x8c00 0x0 0x0 0x3 &mpic 0x4 0x1 548 0x8c00 0x0 0x0 0x4 &mpic 0x1 0x1 549 550 /* IDSEL 0x11 func 5 - PCI slot 1 */ 551 0x8d00 0x0 0x0 0x1 &mpic 0x2 0x1 552 0x8d00 0x0 0x0 0x2 &mpic 0x3 0x1 553 0x8d00 0x0 0x0 0x3 &mpic 0x4 0x1 554 0x8d00 0x0 0x0 0x4 &mpic 0x1 0x1 555 556 /* IDSEL 0x11 func 6 - PCI slot 1 */ 557 0x8e00 0x0 0x0 0x1 &mpic 0x2 0x1 558 0x8e00 0x0 0x0 0x2 &mpic 0x3 0x1 559 0x8e00 0x0 0x0 0x3 &mpic 0x4 0x1 560 0x8e00 0x0 0x0 0x4 &mpic 0x1 0x1 561 562 /* IDSEL 0x11 func 7 - PCI slot 1 */ 563 0x8f00 0x0 0x0 0x1 &mpic 0x2 0x1 564 0x8f00 0x0 0x0 0x2 &mpic 0x3 0x1 565 0x8f00 0x0 0x0 0x3 &mpic 0x4 0x1 566 0x8f00 0x0 0x0 0x4 &mpic 0x1 0x1 567 568 /* IDSEL 0x12 func 0 - PCI slot 2 */ 569 0x9000 0x0 0x0 0x1 &mpic 0x3 0x1 570 0x9000 0x0 0x0 0x2 &mpic 0x4 0x1 571 0x9000 0x0 0x0 0x3 &mpic 0x1 0x1 572 0x9000 0x0 0x0 0x4 &mpic 0x2 0x1 573 574 /* IDSEL 0x12 func 1 - PCI slot 2 */ 575 0x9100 0x0 0x0 0x1 &mpic 0x3 0x1 576 0x9100 0x0 0x0 0x2 &mpic 0x4 0x1 577 0x9100 0x0 0x0 0x3 &mpic 0x1 0x1 578 0x9100 0x0 0x0 0x4 &mpic 0x2 0x1 579 580 /* IDSEL 0x12 func 2 - PCI slot 2 */ 581 0x9200 0x0 0x0 0x1 &mpic 0x3 0x1 582 0x9200 0x0 0x0 0x2 &mpic 0x4 0x1 583 0x9200 0x0 0x0 0x3 &mpic 0x1 0x1 584 0x9200 0x0 0x0 0x4 &mpic 0x2 0x1 585 586 /* IDSEL 0x12 func 3 - PCI slot 2 */ 587 0x9300 0x0 0x0 0x1 &mpic 0x3 0x1 588 0x9300 0x0 0x0 0x2 &mpic 0x4 0x1 589 0x9300 0x0 0x0 0x3 &mpic 0x1 0x1 590 0x9300 0x0 0x0 0x4 &mpic 0x2 0x1 591 592 /* IDSEL 0x12 func 4 - PCI slot 2 */ 593 0x9400 0x0 0x0 0x1 &mpic 0x3 0x1 594 0x9400 0x0 0x0 0x2 &mpic 0x4 0x1 595 0x9400 0x0 0x0 0x3 &mpic 0x1 0x1 596 0x9400 0x0 0x0 0x4 &mpic 0x2 0x1 597 598 /* IDSEL 0x12 func 5 - PCI slot 2 */ 599 0x9500 0x0 0x0 0x1 &mpic 0x3 0x1 600 0x9500 0x0 0x0 0x2 &mpic 0x4 0x1 601 0x9500 0x0 0x0 0x3 &mpic 0x1 0x1 602 0x9500 0x0 0x0 0x4 &mpic 0x2 0x1 603 604 /* IDSEL 0x12 func 6 - PCI slot 2 */ 605 0x9600 0x0 0x0 0x1 &mpic 0x3 0x1 606 0x9600 0x0 0x0 0x2 &mpic 0x4 0x1 607 0x9600 0x0 0x0 0x3 &mpic 0x1 0x1 608 0x9600 0x0 0x0 0x4 &mpic 0x2 0x1 609 610 /* IDSEL 0x12 func 7 - PCI slot 2 */ 611 0x9700 0x0 0x0 0x1 &mpic 0x3 0x1 612 0x9700 0x0 0x0 0x2 &mpic 0x4 0x1 613 0x9700 0x0 0x0 0x3 &mpic 0x1 0x1 614 0x9700 0x0 0x0 0x4 &mpic 0x2 0x1 615 616 // IDSEL 0x1c USB 617 0xe000 0x0 0x0 0x1 &i8259 0xc 0x2 618 0xe100 0x0 0x0 0x2 &i8259 0x9 0x2 619 0xe200 0x0 0x0 0x3 &i8259 0xa 0x2 620 0xe300 0x0 0x0 0x4 &i8259 0xb 0x2 621 622 // IDSEL 0x1d Audio 623 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2 624 625 // IDSEL 0x1e Legacy 626 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2 627 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2 628 629 // IDSEL 0x1f IDE/SATA 630 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2 631 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2 632 633 >; 634 635 pcie@0 { 636 reg = <0x0 0x0 0x0 0x0 0x0>; 637 #size-cells = <2>; 638 #address-cells = <3>; 639 device_type = "pci"; 640 ranges = <0x2000000 0x0 0x80000000 641 0x2000000 0x0 0x80000000 642 0x0 0x20000000 643 644 0x1000000 0x0 0x0 645 0x1000000 0x0 0x0 646 0x0 0x100000>; 647 uli1575@0 { 648 reg = <0x0 0x0 0x0 0x0 0x0>; 649 #size-cells = <2>; 650 #address-cells = <3>; 651 ranges = <0x2000000 0x0 0x80000000 652 0x2000000 0x0 0x80000000 653 0x0 0x20000000 654 655 0x1000000 0x0 0x0 656 0x1000000 0x0 0x0 657 0x0 0x100000>; 658 isa@1e { 659 device_type = "isa"; 660 #interrupt-cells = <2>; 661 #size-cells = <1>; 662 #address-cells = <2>; 663 reg = <0xf000 0x0 0x0 0x0 0x0>; 664 ranges = <0x1 0x0 0x1000000 0x0 0x0 665 0x1000>; 666 interrupt-parent = <&i8259>; 667 668 i8259: interrupt-controller@20 { 669 reg = <0x1 0x20 0x2 670 0x1 0xa0 0x2 671 0x1 0x4d0 0x2>; 672 interrupt-controller; 673 device_type = "interrupt-controller"; 674 #address-cells = <0>; 675 #interrupt-cells = <2>; 676 compatible = "chrp,iic"; 677 interrupts = <9 2>; 678 interrupt-parent = <&mpic>; 679 }; 680 681 i8042@60 { 682 #size-cells = <0>; 683 #address-cells = <1>; 684 reg = <0x1 0x60 0x1 0x1 0x64 0x1>; 685 interrupts = <1 3 12 3>; 686 interrupt-parent = 687 <&i8259>; 688 689 keyboard@0 { 690 reg = <0x0>; 691 compatible = "pnpPNP,303"; 692 }; 693 694 mouse@1 { 695 reg = <0x1>; 696 compatible = "pnpPNP,f03"; 697 }; 698 }; 699 700 rtc@70 { 701 compatible = "pnpPNP,b00"; 702 reg = <0x1 0x70 0x2>; 703 }; 704 705 gpio@400 { 706 reg = <0x1 0x400 0x80>; 707 }; 708 }; 709 }; 710 }; 711 712 }; 713 714 pci1: pcie@ffe09000 { 715 cell-index = <1>; 716 compatible = "fsl,mpc8548-pcie"; 717 device_type = "pci"; 718 #interrupt-cells = <1>; 719 #size-cells = <2>; 720 #address-cells = <3>; 721 reg = <0 0xffe09000 0 0x1000>; 722 bus-range = <0 255>; 723 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 724 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x00010000>; 725 clock-frequency = <33333333>; 726 interrupt-parent = <&mpic>; 727 interrupts = <25 2>; 728 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 729 interrupt-map = < 730 /* IDSEL 0x0 */ 731 0000 0x0 0x0 0x1 &mpic 0x4 0x1 732 0000 0x0 0x0 0x2 &mpic 0x5 0x1 733 0000 0x0 0x0 0x3 &mpic 0x6 0x1 734 0000 0x0 0x0 0x4 &mpic 0x7 0x1 735 >; 736 pcie@0 { 737 reg = <0x0 0x0 0x0 0x0 0x0>; 738 #size-cells = <2>; 739 #address-cells = <3>; 740 device_type = "pci"; 741 ranges = <0x2000000 0x0 0xa0000000 742 0x2000000 0x0 0xa0000000 743 0x0 0x20000000 744 745 0x1000000 0x0 0x0 746 0x1000000 0x0 0x0 747 0x0 0x100000>; 748 }; 749 }; 750 751 pci2: pcie@ffe0a000 { 752 cell-index = <2>; 753 compatible = "fsl,mpc8548-pcie"; 754 device_type = "pci"; 755 #interrupt-cells = <1>; 756 #size-cells = <2>; 757 #address-cells = <3>; 758 reg = <0 0xffe0a000 0 0x1000>; 759 bus-range = <0 255>; 760 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000 761 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x00010000>; 762 clock-frequency = <33333333>; 763 interrupt-parent = <&mpic>; 764 interrupts = <26 2>; 765 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 766 interrupt-map = < 767 /* IDSEL 0x0 */ 768 0000 0x0 0x0 0x1 &mpic 0x0 0x1 769 0000 0x0 0x0 0x2 &mpic 0x1 0x1 770 0000 0x0 0x0 0x3 &mpic 0x2 0x1 771 0000 0x0 0x0 0x4 &mpic 0x3 0x1 772 >; 773 pcie@0 { 774 reg = <0x0 0x0 0x0 0x0 0x0>; 775 #size-cells = <2>; 776 #address-cells = <3>; 777 device_type = "pci"; 778 ranges = <0x2000000 0x0 0xc0000000 779 0x2000000 0x0 0xc0000000 780 0x0 0x20000000 781 782 0x1000000 0x0 0x0 783 0x1000000 0x0 0x0 784 0x0 0x100000>; 785 }; 786 }; 787}; 788