1/* 2 * SBC8560 Device Tree Source 3 * 4 * Copyright 2007 Wind River Systems Inc. 5 * 6 * Paul Gortmaker (see MAINTAINERS for contact information) 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 */ 13 14/dts-v1/; 15 16/ { 17 model = "SBC8560"; 18 compatible = "SBC8560"; 19 #address-cells = <1>; 20 #size-cells = <1>; 21 22 aliases { 23 ethernet0 = &enet0; 24 ethernet1 = &enet1; 25 ethernet2 = &enet2; 26 ethernet3 = &enet3; 27 serial0 = &serial0; 28 serial1 = &serial1; 29 pci0 = &pci0; 30 }; 31 32 cpus { 33 #address-cells = <1>; 34 #size-cells = <0>; 35 36 PowerPC,8560@0 { 37 device_type = "cpu"; 38 reg = <0>; 39 d-cache-line-size = <0x20>; // 32 bytes 40 i-cache-line-size = <0x20>; // 32 bytes 41 d-cache-size = <0x8000>; // L1, 32K 42 i-cache-size = <0x8000>; // L1, 32K 43 timebase-frequency = <0>; // From uboot 44 bus-frequency = <0>; 45 clock-frequency = <0>; 46 next-level-cache = <&L2>; 47 }; 48 }; 49 50 memory { 51 device_type = "memory"; 52 reg = <0x00000000 0x20000000>; 53 }; 54 55 soc@ff700000 { 56 #address-cells = <1>; 57 #size-cells = <1>; 58 device_type = "soc"; 59 ranges = <0x0 0xff700000 0x00100000>; 60 reg = <0xff700000 0x00100000>; 61 clock-frequency = <0>; 62 63 memory-controller@2000 { 64 compatible = "fsl,8560-memory-controller"; 65 reg = <0x2000 0x1000>; 66 interrupt-parent = <&mpic>; 67 interrupts = <0x12 0x2>; 68 }; 69 70 L2: l2-cache-controller@20000 { 71 compatible = "fsl,8560-l2-cache-controller"; 72 reg = <0x20000 0x1000>; 73 cache-line-size = <0x20>; // 32 bytes 74 cache-size = <0x40000>; // L2, 256K 75 interrupt-parent = <&mpic>; 76 interrupts = <0x10 0x2>; 77 }; 78 79 i2c@3000 { 80 #address-cells = <1>; 81 #size-cells = <0>; 82 cell-index = <0>; 83 compatible = "fsl-i2c"; 84 reg = <0x3000 0x100>; 85 interrupts = <0x2b 0x2>; 86 interrupt-parent = <&mpic>; 87 dfsrr; 88 }; 89 90 i2c@3100 { 91 #address-cells = <1>; 92 #size-cells = <0>; 93 cell-index = <1>; 94 compatible = "fsl-i2c"; 95 reg = <0x3100 0x100>; 96 interrupts = <0x2b 0x2>; 97 interrupt-parent = <&mpic>; 98 dfsrr; 99 }; 100 101 dma@21300 { 102 #address-cells = <1>; 103 #size-cells = <1>; 104 compatible = "fsl,mpc8560-dma", "fsl,eloplus-dma"; 105 reg = <0x21300 0x4>; 106 ranges = <0x0 0x21100 0x200>; 107 cell-index = <0>; 108 dma-channel@0 { 109 compatible = "fsl,mpc8560-dma-channel", 110 "fsl,eloplus-dma-channel"; 111 reg = <0x0 0x80>; 112 cell-index = <0>; 113 interrupt-parent = <&mpic>; 114 interrupts = <20 2>; 115 }; 116 dma-channel@80 { 117 compatible = "fsl,mpc8560-dma-channel", 118 "fsl,eloplus-dma-channel"; 119 reg = <0x80 0x80>; 120 cell-index = <1>; 121 interrupt-parent = <&mpic>; 122 interrupts = <21 2>; 123 }; 124 dma-channel@100 { 125 compatible = "fsl,mpc8560-dma-channel", 126 "fsl,eloplus-dma-channel"; 127 reg = <0x100 0x80>; 128 cell-index = <2>; 129 interrupt-parent = <&mpic>; 130 interrupts = <22 2>; 131 }; 132 dma-channel@180 { 133 compatible = "fsl,mpc8560-dma-channel", 134 "fsl,eloplus-dma-channel"; 135 reg = <0x180 0x80>; 136 cell-index = <3>; 137 interrupt-parent = <&mpic>; 138 interrupts = <23 2>; 139 }; 140 }; 141 142 mdio@24520 { 143 #address-cells = <1>; 144 #size-cells = <0>; 145 compatible = "fsl,gianfar-mdio"; 146 reg = <0x24520 0x20>; 147 phy0: ethernet-phy@19 { 148 interrupt-parent = <&mpic>; 149 interrupts = <0x6 0x1>; 150 reg = <0x19>; 151 device_type = "ethernet-phy"; 152 }; 153 phy1: ethernet-phy@1a { 154 interrupt-parent = <&mpic>; 155 interrupts = <0x7 0x1>; 156 reg = <0x1a>; 157 device_type = "ethernet-phy"; 158 }; 159 phy2: ethernet-phy@1b { 160 interrupt-parent = <&mpic>; 161 interrupts = <0x8 0x1>; 162 reg = <0x1b>; 163 device_type = "ethernet-phy"; 164 }; 165 phy3: ethernet-phy@1c { 166 interrupt-parent = <&mpic>; 167 interrupts = <0x8 0x1>; 168 reg = <0x1c>; 169 device_type = "ethernet-phy"; 170 }; 171 tbi0: tbi-phy@11 { 172 reg = <0x11>; 173 device_type = "tbi-phy"; 174 }; 175 }; 176 177 mdio@25520 { 178 #address-cells = <1>; 179 #size-cells = <0>; 180 compatible = "fsl,gianfar-tbi"; 181 reg = <0x25520 0x20>; 182 183 tbi1: tbi-phy@11 { 184 reg = <0x11>; 185 device_type = "tbi-phy"; 186 }; 187 }; 188 189 enet0: ethernet@24000 { 190 cell-index = <0>; 191 device_type = "network"; 192 model = "TSEC"; 193 compatible = "gianfar"; 194 reg = <0x24000 0x1000>; 195 local-mac-address = [ 00 00 00 00 00 00 ]; 196 interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>; 197 interrupt-parent = <&mpic>; 198 tbi-handle = <&tbi0>; 199 phy-handle = <&phy0>; 200 }; 201 202 enet1: ethernet@25000 { 203 cell-index = <1>; 204 device_type = "network"; 205 model = "TSEC"; 206 compatible = "gianfar"; 207 reg = <0x25000 0x1000>; 208 local-mac-address = [ 00 00 00 00 00 00 ]; 209 interrupts = <0x23 0x2 0x24 0x2 0x28 0x2>; 210 interrupt-parent = <&mpic>; 211 tbi-handle = <&tbi1>; 212 phy-handle = <&phy1>; 213 }; 214 215 mpic: pic@40000 { 216 interrupt-controller; 217 #address-cells = <0>; 218 #interrupt-cells = <2>; 219 compatible = "chrp,open-pic"; 220 reg = <0x40000 0x40000>; 221 device_type = "open-pic"; 222 }; 223 224 cpm@919c0 { 225 #address-cells = <1>; 226 #size-cells = <1>; 227 compatible = "fsl,mpc8560-cpm", "fsl,cpm2"; 228 reg = <0x919c0 0x30>; 229 ranges; 230 231 muram@80000 { 232 #address-cells = <1>; 233 #size-cells = <1>; 234 ranges = <0x0 0x80000 0x10000>; 235 236 data@0 { 237 compatible = "fsl,cpm-muram-data"; 238 reg = <0x0 0x4000 0x9000 0x2000>; 239 }; 240 }; 241 242 brg@919f0 { 243 compatible = "fsl,mpc8560-brg", 244 "fsl,cpm2-brg", 245 "fsl,cpm-brg"; 246 reg = <0x919f0 0x10 0x915f0 0x10>; 247 clock-frequency = <165000000>; 248 }; 249 250 cpmpic: pic@90c00 { 251 interrupt-controller; 252 #address-cells = <0>; 253 #interrupt-cells = <2>; 254 interrupts = <0x2e 0x2>; 255 interrupt-parent = <&mpic>; 256 reg = <0x90c00 0x80>; 257 compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic"; 258 }; 259 260 enet2: ethernet@91320 { 261 device_type = "network"; 262 compatible = "fsl,mpc8560-fcc-enet", 263 "fsl,cpm2-fcc-enet"; 264 reg = <0x91320 0x20 0x88500 0x100 0x913b0 0x1>; 265 local-mac-address = [ 00 00 00 00 00 00 ]; 266 fsl,cpm-command = <0x16200300>; 267 interrupts = <0x21 0x8>; 268 interrupt-parent = <&cpmpic>; 269 phy-handle = <&phy2>; 270 }; 271 272 enet3: ethernet@91340 { 273 device_type = "network"; 274 compatible = "fsl,mpc8560-fcc-enet", 275 "fsl,cpm2-fcc-enet"; 276 reg = <0x91340 0x20 0x88600 0x100 0x913d0 0x1>; 277 local-mac-address = [ 00 00 00 00 00 00 ]; 278 fsl,cpm-command = <0x1a400300>; 279 interrupts = <0x22 0x8>; 280 interrupt-parent = <&cpmpic>; 281 phy-handle = <&phy3>; 282 }; 283 }; 284 285 global-utilities@e0000 { 286 compatible = "fsl,mpc8560-guts"; 287 reg = <0xe0000 0x1000>; 288 fsl,has-rstcr; 289 }; 290 }; 291 292 pci0: pci@ff708000 { 293 cell-index = <0>; 294 #interrupt-cells = <1>; 295 #size-cells = <2>; 296 #address-cells = <3>; 297 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; 298 device_type = "pci"; 299 reg = <0xff708000 0x1000>; 300 clock-frequency = <66666666>; 301 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 302 interrupt-map = < 303 304 /* IDSEL 0x02 */ 305 0x1000 0x0 0x0 0x1 &mpic 0x2 0x1 306 0x1000 0x0 0x0 0x2 &mpic 0x3 0x1 307 0x1000 0x0 0x0 0x3 &mpic 0x4 0x1 308 0x1000 0x0 0x0 0x4 &mpic 0x5 0x1>; 309 310 interrupt-parent = <&mpic>; 311 interrupts = <0x18 0x2>; 312 bus-range = <0x0 0x0>; 313 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000 314 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>; 315 }; 316 317 localbus@ff705000 { 318 compatible = "fsl,mpc8560-localbus"; 319 #address-cells = <2>; 320 #size-cells = <1>; 321 reg = <0xff705000 0x100>; // BRx, ORx, etc. 322 323 ranges = < 324 0x0 0x0 0xff800000 0x0800000 // 8MB boot flash 325 0x1 0x0 0xe4000000 0x4000000 // 64MB flash 326 0x3 0x0 0x20000000 0x4000000 // 64MB SDRAM 327 0x4 0x0 0x24000000 0x4000000 // 64MB SDRAM 328 0x5 0x0 0xfc000000 0x0c00000 // EPLD 329 0x6 0x0 0xe0000000 0x4000000 // 64MB flash 330 0x7 0x0 0x80000000 0x0200000 // ATM1,2 331 >; 332 333 epld@5,0 { 334 compatible = "wrs,epld-localbus"; 335 #address-cells = <2>; 336 #size-cells = <1>; 337 reg = <0x5 0x0 0xc00000>; 338 ranges = < 339 0x0 0x0 0x5 0x000000 0x1fff // LED disp. 340 0x1 0x0 0x5 0x100000 0x1fff // switches 341 0x2 0x0 0x5 0x200000 0x1fff // ID reg. 342 0x3 0x0 0x5 0x300000 0x1fff // status reg. 343 0x4 0x0 0x5 0x400000 0x1fff // reset reg. 344 0x5 0x0 0x5 0x500000 0x1fff // Wind port 345 0x7 0x0 0x5 0x700000 0x1fff // UART #1 346 0x8 0x0 0x5 0x800000 0x1fff // UART #2 347 0x9 0x0 0x5 0x900000 0x1fff // RTC 348 0xb 0x0 0x5 0xb00000 0x1fff // EEPROM 349 >; 350 351 bidr@2,0 { 352 compatible = "wrs,sbc8560-bidr"; 353 reg = <0x2 0x0 0x10>; 354 }; 355 356 bcsr@3,0 { 357 compatible = "wrs,sbc8560-bcsr"; 358 reg = <0x3 0x0 0x10>; 359 }; 360 361 brstcr@4,0 { 362 compatible = "wrs,sbc8560-brstcr"; 363 reg = <0x4 0x0 0x10>; 364 }; 365 366 serial0: serial@7,0 { 367 device_type = "serial"; 368 compatible = "ns16550"; 369 reg = <0x7 0x0 0x100>; 370 clock-frequency = <1843200>; 371 interrupts = <0x9 0x2>; 372 interrupt-parent = <&mpic>; 373 }; 374 375 serial1: serial@8,0 { 376 device_type = "serial"; 377 compatible = "ns16550"; 378 reg = <0x8 0x0 0x100>; 379 clock-frequency = <1843200>; 380 interrupts = <0xa 0x2>; 381 interrupt-parent = <&mpic>; 382 }; 383 384 rtc@9,0 { 385 compatible = "m48t59"; 386 reg = <0x9 0x0 0x1fff>; 387 }; 388 }; 389 }; 390}; 391