1 /*
2 * Driver for GE Fanuc's FPGA based GPIO pins
3 *
4 * Author: Martyn Welch <martyn.welch@gefanuc.com>
5 *
6 * 2008 (c) GE Fanuc Intelligent Platforms Embedded Systems, Inc.
7 *
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
11 */
12
13 /* TODO
14 *
15 * Configuration of output modes (totem-pole/open-drain)
16 * Interrupt configuration - interrupts are always generated the FPGA relies on
17 * the I/O interrupt controllers mask to stop them propergating
18 */
19
20 #include <linux/kernel.h>
21 #include <linux/compiler.h>
22 #include <linux/init.h>
23 #include <linux/io.h>
24 #include <linux/of.h>
25 #include <linux/of_device.h>
26 #include <linux/of_platform.h>
27 #include <linux/of_gpio.h>
28 #include <linux/gpio.h>
29
30 #define GEF_GPIO_DIRECT 0x00
31 #define GEF_GPIO_IN 0x04
32 #define GEF_GPIO_OUT 0x08
33 #define GEF_GPIO_TRIG 0x0C
34 #define GEF_GPIO_POLAR_A 0x10
35 #define GEF_GPIO_POLAR_B 0x14
36 #define GEF_GPIO_INT_STAT 0x18
37 #define GEF_GPIO_OVERRUN 0x1C
38 #define GEF_GPIO_MODE 0x20
39
40 #define NUM_GPIO 19
41
_gef_gpio_set(void __iomem * reg,unsigned int offset,int value)42 static void _gef_gpio_set(void __iomem *reg, unsigned int offset, int value)
43 {
44 unsigned int data;
45
46 data = ioread32be(reg);
47 /* value: 0=low; 1=high */
48 if (value & 0x1)
49 data = data | (0x1 << offset);
50 else
51 data = data & ~(0x1 << offset);
52
53 iowrite32be(data, reg);
54 }
55
56
gef_gpio_dir_in(struct gpio_chip * chip,unsigned offset)57 static int gef_gpio_dir_in(struct gpio_chip *chip, unsigned offset)
58 {
59 unsigned int data;
60 struct of_mm_gpio_chip *mmchip = to_of_mm_gpio_chip(chip);
61
62 data = ioread32be(mmchip->regs + GEF_GPIO_DIRECT);
63 data = data | (0x1 << offset);
64 iowrite32be(data, mmchip->regs + GEF_GPIO_DIRECT);
65
66 return 0;
67 }
68
gef_gpio_dir_out(struct gpio_chip * chip,unsigned offset,int value)69 static int gef_gpio_dir_out(struct gpio_chip *chip, unsigned offset, int value)
70 {
71 unsigned int data;
72 struct of_mm_gpio_chip *mmchip = to_of_mm_gpio_chip(chip);
73
74 /* Set direction before switching to input */
75 _gef_gpio_set(mmchip->regs + GEF_GPIO_OUT, offset, value);
76
77 data = ioread32be(mmchip->regs + GEF_GPIO_DIRECT);
78 data = data & ~(0x1 << offset);
79 iowrite32be(data, mmchip->regs + GEF_GPIO_DIRECT);
80
81 return 0;
82 }
83
gef_gpio_get(struct gpio_chip * chip,unsigned offset)84 static int gef_gpio_get(struct gpio_chip *chip, unsigned offset)
85 {
86 unsigned int data;
87 int state = 0;
88 struct of_mm_gpio_chip *mmchip = to_of_mm_gpio_chip(chip);
89
90 data = ioread32be(mmchip->regs + GEF_GPIO_IN);
91 state = (int)((data >> offset) & 0x1);
92
93 return state;
94 }
95
gef_gpio_set(struct gpio_chip * chip,unsigned offset,int value)96 static void gef_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
97 {
98 struct of_mm_gpio_chip *mmchip = to_of_mm_gpio_chip(chip);
99
100 _gef_gpio_set(mmchip->regs + GEF_GPIO_OUT, offset, value);
101 }
102
gef_gpio_init(void)103 static int __init gef_gpio_init(void)
104 {
105 struct device_node *np;
106
107 for_each_compatible_node(np, NULL, "gef,sbc610-gpio") {
108 int retval;
109 struct of_mm_gpio_chip *gef_gpio_chip;
110
111 pr_debug("%s: Initialising GEF GPIO\n", np->full_name);
112
113 /* Allocate chip structure */
114 gef_gpio_chip = kzalloc(sizeof(*gef_gpio_chip), GFP_KERNEL);
115 if (!gef_gpio_chip) {
116 pr_err("%s: Unable to allocate structure\n",
117 np->full_name);
118 continue;
119 }
120
121 /* Setup pointers to chip functions */
122 gef_gpio_chip->of_gc.gpio_cells = 2;
123 gef_gpio_chip->of_gc.gc.ngpio = NUM_GPIO;
124 gef_gpio_chip->of_gc.gc.direction_input = gef_gpio_dir_in;
125 gef_gpio_chip->of_gc.gc.direction_output = gef_gpio_dir_out;
126 gef_gpio_chip->of_gc.gc.get = gef_gpio_get;
127 gef_gpio_chip->of_gc.gc.set = gef_gpio_set;
128
129 /* This function adds a memory mapped GPIO chip */
130 retval = of_mm_gpiochip_add(np, gef_gpio_chip);
131 if (retval) {
132 kfree(gef_gpio_chip);
133 pr_err("%s: Unable to add GPIO\n", np->full_name);
134 }
135 }
136
137 return 0;
138 };
139 arch_initcall(gef_gpio_init);
140
141 MODULE_DESCRIPTION("GE Fanuc I/O FPGA GPIO driver");
142 MODULE_AUTHOR("Martyn Welch <martyn.welch@gefanuc.com");
143 MODULE_LICENSE("GPL");
144