1 /*
2 * MPC8610 HPCD board specific routines
3 *
4 * Initial author: Xianghua Xiao <x.xiao@freescale.com>
5 * Recode: Jason Jin <jason.jin@freescale.com>
6 * York Sun <yorksun@freescale.com>
7 *
8 * Rewrite the interrupt routing. remove the 8259PIC support,
9 * All the integrated device in ULI use sideband interrupt.
10 *
11 * Copyright 2008 Freescale Semiconductor Inc.
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 */
18
19 #include <linux/stddef.h>
20 #include <linux/kernel.h>
21 #include <linux/pci.h>
22 #include <linux/kdev_t.h>
23 #include <linux/delay.h>
24 #include <linux/seq_file.h>
25 #include <linux/of.h>
26
27 #include <asm/system.h>
28 #include <asm/time.h>
29 #include <asm/machdep.h>
30 #include <asm/pci-bridge.h>
31 #include <asm/mpc86xx.h>
32 #include <asm/prom.h>
33 #include <mm/mmu_decl.h>
34 #include <asm/udbg.h>
35
36 #include <asm/mpic.h>
37
38 #include <linux/of_platform.h>
39 #include <sysdev/fsl_pci.h>
40 #include <sysdev/fsl_soc.h>
41
42 #include "mpc86xx.h"
43
44 static unsigned char *pixis_bdcfg0, *pixis_arch;
45
46 static struct of_device_id __initdata mpc8610_ids[] = {
47 { .compatible = "fsl,mpc8610-immr", },
48 { .compatible = "simple-bus", },
49 {}
50 };
51
mpc8610_declare_of_platform_devices(void)52 static int __init mpc8610_declare_of_platform_devices(void)
53 {
54 /* Without this call, the SSI device driver won't get probed. */
55 of_platform_bus_probe(NULL, mpc8610_ids, NULL);
56
57 return 0;
58 }
59 machine_device_initcall(mpc86xx_hpcd, mpc8610_declare_of_platform_devices);
60
61 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
62
get_busfreq(void)63 static u32 get_busfreq(void)
64 {
65 struct device_node *node;
66
67 u32 fs_busfreq = 0;
68 node = of_find_node_by_type(NULL, "cpu");
69 if (node) {
70 unsigned int size;
71 const unsigned int *prop =
72 of_get_property(node, "bus-frequency", &size);
73 if (prop)
74 fs_busfreq = *prop;
75 of_node_put(node);
76 };
77 return fs_busfreq;
78 }
79
mpc8610hpcd_get_pixel_format(unsigned int bits_per_pixel,int monitor_port)80 unsigned int mpc8610hpcd_get_pixel_format(unsigned int bits_per_pixel,
81 int monitor_port)
82 {
83 static const unsigned long pixelformat[][3] = {
84 {0x88882317, 0x88083218, 0x65052119},
85 {0x88883316, 0x88082219, 0x65053118},
86 };
87 unsigned int pix_fmt, arch_monitor;
88
89 arch_monitor = ((*pixis_arch == 0x01) && (monitor_port == 0))? 0 : 1;
90 /* DVI port for board version 0x01 */
91
92 if (bits_per_pixel == 32)
93 pix_fmt = pixelformat[arch_monitor][0];
94 else if (bits_per_pixel == 24)
95 pix_fmt = pixelformat[arch_monitor][1];
96 else if (bits_per_pixel == 16)
97 pix_fmt = pixelformat[arch_monitor][2];
98 else
99 pix_fmt = pixelformat[1][0];
100
101 return pix_fmt;
102 }
103
mpc8610hpcd_set_gamma_table(int monitor_port,char * gamma_table_base)104 void mpc8610hpcd_set_gamma_table(int monitor_port, char *gamma_table_base)
105 {
106 int i;
107 if (monitor_port == 2) { /* dual link LVDS */
108 for (i = 0; i < 256*3; i++)
109 gamma_table_base[i] = (gamma_table_base[i] << 2) |
110 ((gamma_table_base[i] >> 6) & 0x03);
111 }
112 }
113
114 #define PX_BRDCFG0_DVISEL (1 << 3)
115 #define PX_BRDCFG0_DLINK (1 << 4)
116 #define PX_BRDCFG0_DIU_MASK (PX_BRDCFG0_DVISEL | PX_BRDCFG0_DLINK)
117
mpc8610hpcd_set_monitor_port(int monitor_port)118 void mpc8610hpcd_set_monitor_port(int monitor_port)
119 {
120 static const u8 bdcfg[] = {
121 PX_BRDCFG0_DVISEL | PX_BRDCFG0_DLINK,
122 PX_BRDCFG0_DLINK,
123 0,
124 };
125
126 if (monitor_port < 3)
127 clrsetbits_8(pixis_bdcfg0, PX_BRDCFG0_DIU_MASK,
128 bdcfg[monitor_port]);
129 }
130
mpc8610hpcd_set_pixel_clock(unsigned int pixclock)131 void mpc8610hpcd_set_pixel_clock(unsigned int pixclock)
132 {
133 u32 __iomem *clkdvdr;
134 u32 temp;
135 /* variables for pixel clock calcs */
136 ulong bestval, bestfreq, speed_ccb, minpixclock, maxpixclock;
137 ulong pixval;
138 long err;
139 int i;
140
141 clkdvdr = ioremap(get_immrbase() + 0xe0800, sizeof(u32));
142 if (!clkdvdr) {
143 printk(KERN_ERR "Err: can't map clock divider register!\n");
144 return;
145 }
146
147 /* Pixel Clock configuration */
148 pr_debug("DIU: Bus Frequency = %d\n", get_busfreq());
149 speed_ccb = get_busfreq();
150
151 /* Calculate the pixel clock with the smallest error */
152 /* calculate the following in steps to avoid overflow */
153 pr_debug("DIU pixclock in ps - %d\n", pixclock);
154 temp = 1000000000/pixclock;
155 temp *= 1000;
156 pixclock = temp;
157 pr_debug("DIU pixclock freq - %u\n", pixclock);
158
159 temp = pixclock * 5 / 100;
160 pr_debug("deviation = %d\n", temp);
161 minpixclock = pixclock - temp;
162 maxpixclock = pixclock + temp;
163 pr_debug("DIU minpixclock - %lu\n", minpixclock);
164 pr_debug("DIU maxpixclock - %lu\n", maxpixclock);
165 pixval = speed_ccb/pixclock;
166 pr_debug("DIU pixval = %lu\n", pixval);
167
168 err = 100000000;
169 bestval = pixval;
170 pr_debug("DIU bestval = %lu\n", bestval);
171
172 bestfreq = 0;
173 for (i = -1; i <= 1; i++) {
174 temp = speed_ccb / ((pixval+i) + 1);
175 pr_debug("DIU test pixval i= %d, pixval=%lu, temp freq. = %u\n",
176 i, pixval, temp);
177 if ((temp < minpixclock) || (temp > maxpixclock))
178 pr_debug("DIU exceeds monitor range (%lu to %lu)\n",
179 minpixclock, maxpixclock);
180 else if (abs(temp - pixclock) < err) {
181 pr_debug("Entered the else if block %d\n", i);
182 err = abs(temp - pixclock);
183 bestval = pixval+i;
184 bestfreq = temp;
185 }
186 }
187
188 pr_debug("DIU chose = %lx\n", bestval);
189 pr_debug("DIU error = %ld\n NomPixClk ", err);
190 pr_debug("DIU: Best Freq = %lx\n", bestfreq);
191 /* Modify PXCLK in GUTS CLKDVDR */
192 pr_debug("DIU: Current value of CLKDVDR = 0x%08x\n", (*clkdvdr));
193 temp = (*clkdvdr) & 0x2000FFFF;
194 *clkdvdr = temp; /* turn off clock */
195 *clkdvdr = temp | 0x80000000 | (((bestval) & 0x1F) << 16);
196 pr_debug("DIU: Modified value of CLKDVDR = 0x%08x\n", (*clkdvdr));
197 iounmap(clkdvdr);
198 }
199
mpc8610hpcd_show_monitor_port(int monitor_port,char * buf)200 ssize_t mpc8610hpcd_show_monitor_port(int monitor_port, char *buf)
201 {
202 return snprintf(buf, PAGE_SIZE,
203 "%c0 - DVI\n"
204 "%c1 - Single link LVDS\n"
205 "%c2 - Dual link LVDS\n",
206 monitor_port == 0 ? '*' : ' ',
207 monitor_port == 1 ? '*' : ' ',
208 monitor_port == 2 ? '*' : ' ');
209 }
210
mpc8610hpcd_set_sysfs_monitor_port(int val)211 int mpc8610hpcd_set_sysfs_monitor_port(int val)
212 {
213 return val < 3 ? val : 0;
214 }
215
216 #endif
217
mpc86xx_hpcd_setup_arch(void)218 static void __init mpc86xx_hpcd_setup_arch(void)
219 {
220 struct resource r;
221 struct device_node *np;
222 unsigned char *pixis;
223
224 if (ppc_md.progress)
225 ppc_md.progress("mpc86xx_hpcd_setup_arch()", 0);
226
227 #ifdef CONFIG_PCI
228 for_each_node_by_type(np, "pci") {
229 if (of_device_is_compatible(np, "fsl,mpc8610-pci")
230 || of_device_is_compatible(np, "fsl,mpc8641-pcie")) {
231 struct resource rsrc;
232 of_address_to_resource(np, 0, &rsrc);
233 if ((rsrc.start & 0xfffff) == 0xa000)
234 fsl_add_bridge(np, 1);
235 else
236 fsl_add_bridge(np, 0);
237 }
238 }
239 #endif
240 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
241 diu_ops.get_pixel_format = mpc8610hpcd_get_pixel_format;
242 diu_ops.set_gamma_table = mpc8610hpcd_set_gamma_table;
243 diu_ops.set_monitor_port = mpc8610hpcd_set_monitor_port;
244 diu_ops.set_pixel_clock = mpc8610hpcd_set_pixel_clock;
245 diu_ops.show_monitor_port = mpc8610hpcd_show_monitor_port;
246 diu_ops.set_sysfs_monitor_port = mpc8610hpcd_set_sysfs_monitor_port;
247 #endif
248
249 np = of_find_compatible_node(NULL, NULL, "fsl,fpga-pixis");
250 if (np) {
251 of_address_to_resource(np, 0, &r);
252 of_node_put(np);
253 pixis = ioremap(r.start, 32);
254 if (!pixis) {
255 printk(KERN_ERR "Err: can't map FPGA cfg register!\n");
256 return;
257 }
258 pixis_bdcfg0 = pixis + 8;
259 pixis_arch = pixis + 1;
260 } else
261 printk(KERN_ERR "Err: "
262 "can't find device node 'fsl,fpga-pixis'\n");
263
264 printk("MPC86xx HPCD board from Freescale Semiconductor\n");
265 }
266
267 /*
268 * Called very early, device-tree isn't unflattened
269 */
mpc86xx_hpcd_probe(void)270 static int __init mpc86xx_hpcd_probe(void)
271 {
272 unsigned long root = of_get_flat_dt_root();
273
274 if (of_flat_dt_is_compatible(root, "fsl,MPC8610HPCD"))
275 return 1; /* Looks good */
276
277 return 0;
278 }
279
mpc86xx_time_init(void)280 static long __init mpc86xx_time_init(void)
281 {
282 unsigned int temp;
283
284 /* Set the time base to zero */
285 mtspr(SPRN_TBWL, 0);
286 mtspr(SPRN_TBWU, 0);
287
288 temp = mfspr(SPRN_HID0);
289 temp |= HID0_TBEN;
290 mtspr(SPRN_HID0, temp);
291 asm volatile("isync");
292
293 return 0;
294 }
295
define_machine(mpc86xx_hpcd)296 define_machine(mpc86xx_hpcd) {
297 .name = "MPC86xx HPCD",
298 .probe = mpc86xx_hpcd_probe,
299 .setup_arch = mpc86xx_hpcd_setup_arch,
300 .init_IRQ = mpc86xx_init_irq,
301 .get_irq = mpic_get_irq,
302 .restart = fsl_rstcr_restart,
303 .time_init = mpc86xx_time_init,
304 .calibrate_decr = generic_calibrate_decr,
305 .progress = udbg_progress,
306 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
307 };
308