1 /*
2 * PCI / PCI-X / PCI-Express support for 4xx parts
3 *
4 * Copyright 2007 Ben. Herrenschmidt <benh@kernel.crashing.org>, IBM Corp.
5 *
6 * Most PCI Express code is coming from Stefan Roese implementation for
7 * arch/ppc in the Denx tree, slightly reworked by me.
8 *
9 * Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de>
10 *
11 * Some of that comes itself from a previous implementation for 440SPE only
12 * by Roland Dreier:
13 *
14 * Copyright (c) 2005 Cisco Systems. All rights reserved.
15 * Roland Dreier <rolandd@cisco.com>
16 *
17 */
18
19 #undef DEBUG
20
21 #include <linux/kernel.h>
22 #include <linux/pci.h>
23 #include <linux/init.h>
24 #include <linux/of.h>
25 #include <linux/bootmem.h>
26 #include <linux/delay.h>
27
28 #include <asm/io.h>
29 #include <asm/pci-bridge.h>
30 #include <asm/machdep.h>
31 #include <asm/dcr.h>
32 #include <asm/dcr-regs.h>
33 #include <mm/mmu_decl.h>
34
35 #include "ppc4xx_pci.h"
36
37 static int dma_offset_set;
38
39 #define U64_TO_U32_LOW(val) ((u32)((val) & 0x00000000ffffffffULL))
40 #define U64_TO_U32_HIGH(val) ((u32)((val) >> 32))
41
42 #define RES_TO_U32_LOW(val) \
43 ((sizeof(resource_size_t) > sizeof(u32)) ? U64_TO_U32_LOW(val) : (val))
44 #define RES_TO_U32_HIGH(val) \
45 ((sizeof(resource_size_t) > sizeof(u32)) ? U64_TO_U32_HIGH(val) : (0))
46
ppc440spe_revA(void)47 static inline int ppc440spe_revA(void)
48 {
49 /* Catch both 440SPe variants, with and without RAID6 support */
50 if ((mfspr(SPRN_PVR) & 0xffefffff) == 0x53421890)
51 return 1;
52 else
53 return 0;
54 }
55
fixup_ppc4xx_pci_bridge(struct pci_dev * dev)56 static void fixup_ppc4xx_pci_bridge(struct pci_dev *dev)
57 {
58 struct pci_controller *hose;
59 int i;
60
61 if (dev->devfn != 0 || dev->bus->self != NULL)
62 return;
63
64 hose = pci_bus_to_host(dev->bus);
65 if (hose == NULL)
66 return;
67
68 if (!of_device_is_compatible(hose->dn, "ibm,plb-pciex") &&
69 !of_device_is_compatible(hose->dn, "ibm,plb-pcix") &&
70 !of_device_is_compatible(hose->dn, "ibm,plb-pci"))
71 return;
72
73 if (of_device_is_compatible(hose->dn, "ibm,plb440epx-pci") ||
74 of_device_is_compatible(hose->dn, "ibm,plb440grx-pci")) {
75 hose->indirect_type |= PPC_INDIRECT_TYPE_BROKEN_MRM;
76 }
77
78 /* Hide the PCI host BARs from the kernel as their content doesn't
79 * fit well in the resource management
80 */
81 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
82 dev->resource[i].start = dev->resource[i].end = 0;
83 dev->resource[i].flags = 0;
84 }
85
86 printk(KERN_INFO "PCI: Hiding 4xx host bridge resources %s\n",
87 pci_name(dev));
88 }
89 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, fixup_ppc4xx_pci_bridge);
90
ppc4xx_parse_dma_ranges(struct pci_controller * hose,void __iomem * reg,struct resource * res)91 static int __init ppc4xx_parse_dma_ranges(struct pci_controller *hose,
92 void __iomem *reg,
93 struct resource *res)
94 {
95 u64 size;
96 const u32 *ranges;
97 int rlen;
98 int pna = of_n_addr_cells(hose->dn);
99 int np = pna + 5;
100
101 /* Default */
102 res->start = 0;
103 size = 0x80000000;
104 res->end = size - 1;
105 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
106
107 /* Get dma-ranges property */
108 ranges = of_get_property(hose->dn, "dma-ranges", &rlen);
109 if (ranges == NULL)
110 goto out;
111
112 /* Walk it */
113 while ((rlen -= np * 4) >= 0) {
114 u32 pci_space = ranges[0];
115 u64 pci_addr = of_read_number(ranges + 1, 2);
116 u64 cpu_addr = of_translate_dma_address(hose->dn, ranges + 3);
117 size = of_read_number(ranges + pna + 3, 2);
118 ranges += np;
119 if (cpu_addr == OF_BAD_ADDR || size == 0)
120 continue;
121
122 /* We only care about memory */
123 if ((pci_space & 0x03000000) != 0x02000000)
124 continue;
125
126 /* We currently only support memory at 0, and pci_addr
127 * within 32 bits space
128 */
129 if (cpu_addr != 0 || pci_addr > 0xffffffff) {
130 printk(KERN_WARNING "%s: Ignored unsupported dma range"
131 " 0x%016llx...0x%016llx -> 0x%016llx\n",
132 hose->dn->full_name,
133 pci_addr, pci_addr + size - 1, cpu_addr);
134 continue;
135 }
136
137 /* Check if not prefetchable */
138 if (!(pci_space & 0x40000000))
139 res->flags &= ~IORESOURCE_PREFETCH;
140
141
142 /* Use that */
143 res->start = pci_addr;
144 /* Beware of 32 bits resources */
145 if (sizeof(resource_size_t) == sizeof(u32) &&
146 (pci_addr + size) > 0x100000000ull)
147 res->end = 0xffffffff;
148 else
149 res->end = res->start + size - 1;
150 break;
151 }
152
153 /* We only support one global DMA offset */
154 if (dma_offset_set && pci_dram_offset != res->start) {
155 printk(KERN_ERR "%s: dma-ranges(s) mismatch\n",
156 hose->dn->full_name);
157 return -ENXIO;
158 }
159
160 /* Check that we can fit all of memory as we don't support
161 * DMA bounce buffers
162 */
163 if (size < total_memory) {
164 printk(KERN_ERR "%s: dma-ranges too small "
165 "(size=%llx total_memory=%llx)\n",
166 hose->dn->full_name, size, (u64)total_memory);
167 return -ENXIO;
168 }
169
170 /* Check we are a power of 2 size and that base is a multiple of size*/
171 if ((size & (size - 1)) != 0 ||
172 (res->start & (size - 1)) != 0) {
173 printk(KERN_ERR "%s: dma-ranges unaligned\n",
174 hose->dn->full_name);
175 return -ENXIO;
176 }
177
178 /* Check that we are fully contained within 32 bits space */
179 if (res->end > 0xffffffff) {
180 printk(KERN_ERR "%s: dma-ranges outside of 32 bits space\n",
181 hose->dn->full_name);
182 return -ENXIO;
183 }
184 out:
185 dma_offset_set = 1;
186 pci_dram_offset = res->start;
187
188 printk(KERN_INFO "4xx PCI DMA offset set to 0x%08lx\n",
189 pci_dram_offset);
190 return 0;
191 }
192
193 /*
194 * 4xx PCI 2.x part
195 */
196
ppc4xx_setup_one_pci_PMM(struct pci_controller * hose,void __iomem * reg,u64 plb_addr,u64 pci_addr,u64 size,unsigned int flags,int index)197 static int __init ppc4xx_setup_one_pci_PMM(struct pci_controller *hose,
198 void __iomem *reg,
199 u64 plb_addr,
200 u64 pci_addr,
201 u64 size,
202 unsigned int flags,
203 int index)
204 {
205 u32 ma, pcila, pciha;
206
207 /* Hack warning ! The "old" PCI 2.x cell only let us configure the low
208 * 32-bit of incoming PLB addresses. The top 4 bits of the 36-bit
209 * address are actually hard wired to a value that appears to depend
210 * on the specific SoC. For example, it's 0 on 440EP and 1 on 440EPx.
211 *
212 * The trick here is we just crop those top bits and ignore them when
213 * programming the chip. That means the device-tree has to be right
214 * for the specific part used (we don't print a warning if it's wrong
215 * but on the other hand, you'll crash quickly enough), but at least
216 * this code should work whatever the hard coded value is
217 */
218 plb_addr &= 0xffffffffull;
219
220 /* Note: Due to the above hack, the test below doesn't actually test
221 * if you address is above 4G, but it tests that address and
222 * (address + size) are both contained in the same 4G
223 */
224 if ((plb_addr + size) > 0xffffffffull || !is_power_of_2(size) ||
225 size < 0x1000 || (plb_addr & (size - 1)) != 0) {
226 printk(KERN_WARNING "%s: Resource out of range\n",
227 hose->dn->full_name);
228 return -1;
229 }
230 ma = (0xffffffffu << ilog2(size)) | 1;
231 if (flags & IORESOURCE_PREFETCH)
232 ma |= 2;
233
234 pciha = RES_TO_U32_HIGH(pci_addr);
235 pcila = RES_TO_U32_LOW(pci_addr);
236
237 writel(plb_addr, reg + PCIL0_PMM0LA + (0x10 * index));
238 writel(pcila, reg + PCIL0_PMM0PCILA + (0x10 * index));
239 writel(pciha, reg + PCIL0_PMM0PCIHA + (0x10 * index));
240 writel(ma, reg + PCIL0_PMM0MA + (0x10 * index));
241
242 return 0;
243 }
244
ppc4xx_configure_pci_PMMs(struct pci_controller * hose,void __iomem * reg)245 static void __init ppc4xx_configure_pci_PMMs(struct pci_controller *hose,
246 void __iomem *reg)
247 {
248 int i, j, found_isa_hole = 0;
249
250 /* Setup outbound memory windows */
251 for (i = j = 0; i < 3; i++) {
252 struct resource *res = &hose->mem_resources[i];
253
254 /* we only care about memory windows */
255 if (!(res->flags & IORESOURCE_MEM))
256 continue;
257 if (j > 2) {
258 printk(KERN_WARNING "%s: Too many ranges\n",
259 hose->dn->full_name);
260 break;
261 }
262
263 /* Configure the resource */
264 if (ppc4xx_setup_one_pci_PMM(hose, reg,
265 res->start,
266 res->start - hose->pci_mem_offset,
267 res->end + 1 - res->start,
268 res->flags,
269 j) == 0) {
270 j++;
271
272 /* If the resource PCI address is 0 then we have our
273 * ISA memory hole
274 */
275 if (res->start == hose->pci_mem_offset)
276 found_isa_hole = 1;
277 }
278 }
279
280 /* Handle ISA memory hole if not already covered */
281 if (j <= 2 && !found_isa_hole && hose->isa_mem_size)
282 if (ppc4xx_setup_one_pci_PMM(hose, reg, hose->isa_mem_phys, 0,
283 hose->isa_mem_size, 0, j) == 0)
284 printk(KERN_INFO "%s: Legacy ISA memory support enabled\n",
285 hose->dn->full_name);
286 }
287
ppc4xx_configure_pci_PTMs(struct pci_controller * hose,void __iomem * reg,const struct resource * res)288 static void __init ppc4xx_configure_pci_PTMs(struct pci_controller *hose,
289 void __iomem *reg,
290 const struct resource *res)
291 {
292 resource_size_t size = res->end - res->start + 1;
293 u32 sa;
294
295 /* Calculate window size */
296 sa = (0xffffffffu << ilog2(size)) | 1;
297 sa |= 0x1;
298
299 /* RAM is always at 0 local for now */
300 writel(0, reg + PCIL0_PTM1LA);
301 writel(sa, reg + PCIL0_PTM1MS);
302
303 /* Map on PCI side */
304 early_write_config_dword(hose, hose->first_busno, 0,
305 PCI_BASE_ADDRESS_1, res->start);
306 early_write_config_dword(hose, hose->first_busno, 0,
307 PCI_BASE_ADDRESS_2, 0x00000000);
308 early_write_config_word(hose, hose->first_busno, 0,
309 PCI_COMMAND, 0x0006);
310 }
311
ppc4xx_probe_pci_bridge(struct device_node * np)312 static void __init ppc4xx_probe_pci_bridge(struct device_node *np)
313 {
314 /* NYI */
315 struct resource rsrc_cfg;
316 struct resource rsrc_reg;
317 struct resource dma_window;
318 struct pci_controller *hose = NULL;
319 void __iomem *reg = NULL;
320 const int *bus_range;
321 int primary = 0;
322
323 /* Check if device is enabled */
324 if (!of_device_is_available(np)) {
325 printk(KERN_INFO "%s: Port disabled via device-tree\n",
326 np->full_name);
327 return;
328 }
329
330 /* Fetch config space registers address */
331 if (of_address_to_resource(np, 0, &rsrc_cfg)) {
332 printk(KERN_ERR "%s: Can't get PCI config register base !",
333 np->full_name);
334 return;
335 }
336 /* Fetch host bridge internal registers address */
337 if (of_address_to_resource(np, 3, &rsrc_reg)) {
338 printk(KERN_ERR "%s: Can't get PCI internal register base !",
339 np->full_name);
340 return;
341 }
342
343 /* Check if primary bridge */
344 if (of_get_property(np, "primary", NULL))
345 primary = 1;
346
347 /* Get bus range if any */
348 bus_range = of_get_property(np, "bus-range", NULL);
349
350 /* Map registers */
351 reg = ioremap(rsrc_reg.start, rsrc_reg.end + 1 - rsrc_reg.start);
352 if (reg == NULL) {
353 printk(KERN_ERR "%s: Can't map registers !", np->full_name);
354 goto fail;
355 }
356
357 /* Allocate the host controller data structure */
358 hose = pcibios_alloc_controller(np);
359 if (!hose)
360 goto fail;
361
362 hose->first_busno = bus_range ? bus_range[0] : 0x0;
363 hose->last_busno = bus_range ? bus_range[1] : 0xff;
364
365 /* Setup config space */
366 setup_indirect_pci(hose, rsrc_cfg.start, rsrc_cfg.start + 0x4, 0);
367
368 /* Disable all windows */
369 writel(0, reg + PCIL0_PMM0MA);
370 writel(0, reg + PCIL0_PMM1MA);
371 writel(0, reg + PCIL0_PMM2MA);
372 writel(0, reg + PCIL0_PTM1MS);
373 writel(0, reg + PCIL0_PTM2MS);
374
375 /* Parse outbound mapping resources */
376 pci_process_bridge_OF_ranges(hose, np, primary);
377
378 /* Parse inbound mapping resources */
379 if (ppc4xx_parse_dma_ranges(hose, reg, &dma_window) != 0)
380 goto fail;
381
382 /* Configure outbound ranges POMs */
383 ppc4xx_configure_pci_PMMs(hose, reg);
384
385 /* Configure inbound ranges PIMs */
386 ppc4xx_configure_pci_PTMs(hose, reg, &dma_window);
387
388 /* We don't need the registers anymore */
389 iounmap(reg);
390 return;
391
392 fail:
393 if (hose)
394 pcibios_free_controller(hose);
395 if (reg)
396 iounmap(reg);
397 }
398
399 /*
400 * 4xx PCI-X part
401 */
402
ppc4xx_setup_one_pcix_POM(struct pci_controller * hose,void __iomem * reg,u64 plb_addr,u64 pci_addr,u64 size,unsigned int flags,int index)403 static int __init ppc4xx_setup_one_pcix_POM(struct pci_controller *hose,
404 void __iomem *reg,
405 u64 plb_addr,
406 u64 pci_addr,
407 u64 size,
408 unsigned int flags,
409 int index)
410 {
411 u32 lah, lal, pciah, pcial, sa;
412
413 if (!is_power_of_2(size) || size < 0x1000 ||
414 (plb_addr & (size - 1)) != 0) {
415 printk(KERN_WARNING "%s: Resource out of range\n",
416 hose->dn->full_name);
417 return -1;
418 }
419
420 /* Calculate register values */
421 lah = RES_TO_U32_HIGH(plb_addr);
422 lal = RES_TO_U32_LOW(plb_addr);
423 pciah = RES_TO_U32_HIGH(pci_addr);
424 pcial = RES_TO_U32_LOW(pci_addr);
425 sa = (0xffffffffu << ilog2(size)) | 0x1;
426
427 /* Program register values */
428 if (index == 0) {
429 writel(lah, reg + PCIX0_POM0LAH);
430 writel(lal, reg + PCIX0_POM0LAL);
431 writel(pciah, reg + PCIX0_POM0PCIAH);
432 writel(pcial, reg + PCIX0_POM0PCIAL);
433 writel(sa, reg + PCIX0_POM0SA);
434 } else {
435 writel(lah, reg + PCIX0_POM1LAH);
436 writel(lal, reg + PCIX0_POM1LAL);
437 writel(pciah, reg + PCIX0_POM1PCIAH);
438 writel(pcial, reg + PCIX0_POM1PCIAL);
439 writel(sa, reg + PCIX0_POM1SA);
440 }
441
442 return 0;
443 }
444
ppc4xx_configure_pcix_POMs(struct pci_controller * hose,void __iomem * reg)445 static void __init ppc4xx_configure_pcix_POMs(struct pci_controller *hose,
446 void __iomem *reg)
447 {
448 int i, j, found_isa_hole = 0;
449
450 /* Setup outbound memory windows */
451 for (i = j = 0; i < 3; i++) {
452 struct resource *res = &hose->mem_resources[i];
453
454 /* we only care about memory windows */
455 if (!(res->flags & IORESOURCE_MEM))
456 continue;
457 if (j > 1) {
458 printk(KERN_WARNING "%s: Too many ranges\n",
459 hose->dn->full_name);
460 break;
461 }
462
463 /* Configure the resource */
464 if (ppc4xx_setup_one_pcix_POM(hose, reg,
465 res->start,
466 res->start - hose->pci_mem_offset,
467 res->end + 1 - res->start,
468 res->flags,
469 j) == 0) {
470 j++;
471
472 /* If the resource PCI address is 0 then we have our
473 * ISA memory hole
474 */
475 if (res->start == hose->pci_mem_offset)
476 found_isa_hole = 1;
477 }
478 }
479
480 /* Handle ISA memory hole if not already covered */
481 if (j <= 1 && !found_isa_hole && hose->isa_mem_size)
482 if (ppc4xx_setup_one_pcix_POM(hose, reg, hose->isa_mem_phys, 0,
483 hose->isa_mem_size, 0, j) == 0)
484 printk(KERN_INFO "%s: Legacy ISA memory support enabled\n",
485 hose->dn->full_name);
486 }
487
ppc4xx_configure_pcix_PIMs(struct pci_controller * hose,void __iomem * reg,const struct resource * res,int big_pim,int enable_msi_hole)488 static void __init ppc4xx_configure_pcix_PIMs(struct pci_controller *hose,
489 void __iomem *reg,
490 const struct resource *res,
491 int big_pim,
492 int enable_msi_hole)
493 {
494 resource_size_t size = res->end - res->start + 1;
495 u32 sa;
496
497 /* RAM is always at 0 */
498 writel(0x00000000, reg + PCIX0_PIM0LAH);
499 writel(0x00000000, reg + PCIX0_PIM0LAL);
500
501 /* Calculate window size */
502 sa = (0xffffffffu << ilog2(size)) | 1;
503 sa |= 0x1;
504 if (res->flags & IORESOURCE_PREFETCH)
505 sa |= 0x2;
506 if (enable_msi_hole)
507 sa |= 0x4;
508 writel(sa, reg + PCIX0_PIM0SA);
509 if (big_pim)
510 writel(0xffffffff, reg + PCIX0_PIM0SAH);
511
512 /* Map on PCI side */
513 writel(0x00000000, reg + PCIX0_BAR0H);
514 writel(res->start, reg + PCIX0_BAR0L);
515 writew(0x0006, reg + PCIX0_COMMAND);
516 }
517
ppc4xx_probe_pcix_bridge(struct device_node * np)518 static void __init ppc4xx_probe_pcix_bridge(struct device_node *np)
519 {
520 struct resource rsrc_cfg;
521 struct resource rsrc_reg;
522 struct resource dma_window;
523 struct pci_controller *hose = NULL;
524 void __iomem *reg = NULL;
525 const int *bus_range;
526 int big_pim = 0, msi = 0, primary = 0;
527
528 /* Fetch config space registers address */
529 if (of_address_to_resource(np, 0, &rsrc_cfg)) {
530 printk(KERN_ERR "%s:Can't get PCI-X config register base !",
531 np->full_name);
532 return;
533 }
534 /* Fetch host bridge internal registers address */
535 if (of_address_to_resource(np, 3, &rsrc_reg)) {
536 printk(KERN_ERR "%s: Can't get PCI-X internal register base !",
537 np->full_name);
538 return;
539 }
540
541 /* Check if it supports large PIMs (440GX) */
542 if (of_get_property(np, "large-inbound-windows", NULL))
543 big_pim = 1;
544
545 /* Check if we should enable MSIs inbound hole */
546 if (of_get_property(np, "enable-msi-hole", NULL))
547 msi = 1;
548
549 /* Check if primary bridge */
550 if (of_get_property(np, "primary", NULL))
551 primary = 1;
552
553 /* Get bus range if any */
554 bus_range = of_get_property(np, "bus-range", NULL);
555
556 /* Map registers */
557 reg = ioremap(rsrc_reg.start, rsrc_reg.end + 1 - rsrc_reg.start);
558 if (reg == NULL) {
559 printk(KERN_ERR "%s: Can't map registers !", np->full_name);
560 goto fail;
561 }
562
563 /* Allocate the host controller data structure */
564 hose = pcibios_alloc_controller(np);
565 if (!hose)
566 goto fail;
567
568 hose->first_busno = bus_range ? bus_range[0] : 0x0;
569 hose->last_busno = bus_range ? bus_range[1] : 0xff;
570
571 /* Setup config space */
572 setup_indirect_pci(hose, rsrc_cfg.start, rsrc_cfg.start + 0x4, 0);
573
574 /* Disable all windows */
575 writel(0, reg + PCIX0_POM0SA);
576 writel(0, reg + PCIX0_POM1SA);
577 writel(0, reg + PCIX0_POM2SA);
578 writel(0, reg + PCIX0_PIM0SA);
579 writel(0, reg + PCIX0_PIM1SA);
580 writel(0, reg + PCIX0_PIM2SA);
581 if (big_pim) {
582 writel(0, reg + PCIX0_PIM0SAH);
583 writel(0, reg + PCIX0_PIM2SAH);
584 }
585
586 /* Parse outbound mapping resources */
587 pci_process_bridge_OF_ranges(hose, np, primary);
588
589 /* Parse inbound mapping resources */
590 if (ppc4xx_parse_dma_ranges(hose, reg, &dma_window) != 0)
591 goto fail;
592
593 /* Configure outbound ranges POMs */
594 ppc4xx_configure_pcix_POMs(hose, reg);
595
596 /* Configure inbound ranges PIMs */
597 ppc4xx_configure_pcix_PIMs(hose, reg, &dma_window, big_pim, msi);
598
599 /* We don't need the registers anymore */
600 iounmap(reg);
601 return;
602
603 fail:
604 if (hose)
605 pcibios_free_controller(hose);
606 if (reg)
607 iounmap(reg);
608 }
609
610 #ifdef CONFIG_PPC4xx_PCI_EXPRESS
611
612 /*
613 * 4xx PCI-Express part
614 *
615 * We support 3 parts currently based on the compatible property:
616 *
617 * ibm,plb-pciex-440spe
618 * ibm,plb-pciex-405ex
619 * ibm,plb-pciex-460ex
620 *
621 * Anything else will be rejected for now as they are all subtly
622 * different unfortunately.
623 *
624 */
625
626 #define MAX_PCIE_BUS_MAPPED 0x40
627
628 struct ppc4xx_pciex_port
629 {
630 struct pci_controller *hose;
631 struct device_node *node;
632 unsigned int index;
633 int endpoint;
634 int link;
635 int has_ibpre;
636 unsigned int sdr_base;
637 dcr_host_t dcrs;
638 struct resource cfg_space;
639 struct resource utl_regs;
640 void __iomem *utl_base;
641 };
642
643 static struct ppc4xx_pciex_port *ppc4xx_pciex_ports;
644 static unsigned int ppc4xx_pciex_port_count;
645
646 struct ppc4xx_pciex_hwops
647 {
648 int (*core_init)(struct device_node *np);
649 int (*port_init_hw)(struct ppc4xx_pciex_port *port);
650 int (*setup_utl)(struct ppc4xx_pciex_port *port);
651 };
652
653 static struct ppc4xx_pciex_hwops *ppc4xx_pciex_hwops;
654
655 #ifdef CONFIG_44x
656
657 /* Check various reset bits of the 440SPe PCIe core */
ppc440spe_pciex_check_reset(struct device_node * np)658 static int __init ppc440spe_pciex_check_reset(struct device_node *np)
659 {
660 u32 valPE0, valPE1, valPE2;
661 int err = 0;
662
663 /* SDR0_PEGPLLLCT1 reset */
664 if (!(mfdcri(SDR0, PESDR0_PLLLCT1) & 0x01000000)) {
665 /*
666 * the PCIe core was probably already initialised
667 * by firmware - let's re-reset RCSSET regs
668 *
669 * -- Shouldn't we also re-reset the whole thing ? -- BenH
670 */
671 pr_debug("PCIE: SDR0_PLLLCT1 already reset.\n");
672 mtdcri(SDR0, PESDR0_440SPE_RCSSET, 0x01010000);
673 mtdcri(SDR0, PESDR1_440SPE_RCSSET, 0x01010000);
674 mtdcri(SDR0, PESDR2_440SPE_RCSSET, 0x01010000);
675 }
676
677 valPE0 = mfdcri(SDR0, PESDR0_440SPE_RCSSET);
678 valPE1 = mfdcri(SDR0, PESDR1_440SPE_RCSSET);
679 valPE2 = mfdcri(SDR0, PESDR2_440SPE_RCSSET);
680
681 /* SDR0_PExRCSSET rstgu */
682 if (!(valPE0 & 0x01000000) ||
683 !(valPE1 & 0x01000000) ||
684 !(valPE2 & 0x01000000)) {
685 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstgu error\n");
686 err = -1;
687 }
688
689 /* SDR0_PExRCSSET rstdl */
690 if (!(valPE0 & 0x00010000) ||
691 !(valPE1 & 0x00010000) ||
692 !(valPE2 & 0x00010000)) {
693 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstdl error\n");
694 err = -1;
695 }
696
697 /* SDR0_PExRCSSET rstpyn */
698 if ((valPE0 & 0x00001000) ||
699 (valPE1 & 0x00001000) ||
700 (valPE2 & 0x00001000)) {
701 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstpyn error\n");
702 err = -1;
703 }
704
705 /* SDR0_PExRCSSET hldplb */
706 if ((valPE0 & 0x10000000) ||
707 (valPE1 & 0x10000000) ||
708 (valPE2 & 0x10000000)) {
709 printk(KERN_INFO "PCIE: SDR0_PExRCSSET hldplb error\n");
710 err = -1;
711 }
712
713 /* SDR0_PExRCSSET rdy */
714 if ((valPE0 & 0x00100000) ||
715 (valPE1 & 0x00100000) ||
716 (valPE2 & 0x00100000)) {
717 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rdy error\n");
718 err = -1;
719 }
720
721 /* SDR0_PExRCSSET shutdown */
722 if ((valPE0 & 0x00000100) ||
723 (valPE1 & 0x00000100) ||
724 (valPE2 & 0x00000100)) {
725 printk(KERN_INFO "PCIE: SDR0_PExRCSSET shutdown error\n");
726 err = -1;
727 }
728
729 return err;
730 }
731
732 /* Global PCIe core initializations for 440SPe core */
ppc440spe_pciex_core_init(struct device_node * np)733 static int __init ppc440spe_pciex_core_init(struct device_node *np)
734 {
735 int time_out = 20;
736
737 /* Set PLL clock receiver to LVPECL */
738 dcri_clrset(SDR0, PESDR0_PLLLCT1, 0, 1 << 28);
739
740 /* Shouldn't we do all the calibration stuff etc... here ? */
741 if (ppc440spe_pciex_check_reset(np))
742 return -ENXIO;
743
744 if (!(mfdcri(SDR0, PESDR0_PLLLCT2) & 0x10000)) {
745 printk(KERN_INFO "PCIE: PESDR_PLLCT2 resistance calibration "
746 "failed (0x%08x)\n",
747 mfdcri(SDR0, PESDR0_PLLLCT2));
748 return -1;
749 }
750
751 /* De-assert reset of PCIe PLL, wait for lock */
752 dcri_clrset(SDR0, PESDR0_PLLLCT1, 1 << 24, 0);
753 udelay(3);
754
755 while (time_out) {
756 if (!(mfdcri(SDR0, PESDR0_PLLLCT3) & 0x10000000)) {
757 time_out--;
758 udelay(1);
759 } else
760 break;
761 }
762 if (!time_out) {
763 printk(KERN_INFO "PCIE: VCO output not locked\n");
764 return -1;
765 }
766
767 pr_debug("PCIE initialization OK\n");
768
769 return 3;
770 }
771
ppc440spe_pciex_init_port_hw(struct ppc4xx_pciex_port * port)772 static int ppc440spe_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
773 {
774 u32 val = 1 << 24;
775
776 if (port->endpoint)
777 val = PTYPE_LEGACY_ENDPOINT << 20;
778 else
779 val = PTYPE_ROOT_PORT << 20;
780
781 if (port->index == 0)
782 val |= LNKW_X8 << 12;
783 else
784 val |= LNKW_X4 << 12;
785
786 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);
787 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x20222222);
788 if (ppc440spe_revA())
789 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x11000000);
790 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL0SET1, 0x35000000);
791 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL1SET1, 0x35000000);
792 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL2SET1, 0x35000000);
793 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL3SET1, 0x35000000);
794 if (port->index == 0) {
795 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL4SET1,
796 0x35000000);
797 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL5SET1,
798 0x35000000);
799 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL6SET1,
800 0x35000000);
801 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL7SET1,
802 0x35000000);
803 }
804 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET,
805 (1 << 24) | (1 << 16), 1 << 12);
806
807 return 0;
808 }
809
ppc440speA_pciex_init_port_hw(struct ppc4xx_pciex_port * port)810 static int ppc440speA_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
811 {
812 return ppc440spe_pciex_init_port_hw(port);
813 }
814
ppc440speB_pciex_init_port_hw(struct ppc4xx_pciex_port * port)815 static int ppc440speB_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
816 {
817 int rc = ppc440spe_pciex_init_port_hw(port);
818
819 port->has_ibpre = 1;
820
821 return rc;
822 }
823
ppc440speA_pciex_init_utl(struct ppc4xx_pciex_port * port)824 static int ppc440speA_pciex_init_utl(struct ppc4xx_pciex_port *port)
825 {
826 /* XXX Check what that value means... I hate magic */
827 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x68782800);
828
829 /*
830 * Set buffer allocations and then assert VRB and TXE.
831 */
832 out_be32(port->utl_base + PEUTL_OUTTR, 0x08000000);
833 out_be32(port->utl_base + PEUTL_INTR, 0x02000000);
834 out_be32(port->utl_base + PEUTL_OPDBSZ, 0x10000000);
835 out_be32(port->utl_base + PEUTL_PBBSZ, 0x53000000);
836 out_be32(port->utl_base + PEUTL_IPHBSZ, 0x08000000);
837 out_be32(port->utl_base + PEUTL_IPDBSZ, 0x10000000);
838 out_be32(port->utl_base + PEUTL_RCIRQEN, 0x00f00000);
839 out_be32(port->utl_base + PEUTL_PCTL, 0x80800066);
840
841 return 0;
842 }
843
ppc440speB_pciex_init_utl(struct ppc4xx_pciex_port * port)844 static int ppc440speB_pciex_init_utl(struct ppc4xx_pciex_port *port)
845 {
846 /* Report CRS to the operating system */
847 out_be32(port->utl_base + PEUTL_PBCTL, 0x08000000);
848
849 return 0;
850 }
851
852 static struct ppc4xx_pciex_hwops ppc440speA_pcie_hwops __initdata =
853 {
854 .core_init = ppc440spe_pciex_core_init,
855 .port_init_hw = ppc440speA_pciex_init_port_hw,
856 .setup_utl = ppc440speA_pciex_init_utl,
857 };
858
859 static struct ppc4xx_pciex_hwops ppc440speB_pcie_hwops __initdata =
860 {
861 .core_init = ppc440spe_pciex_core_init,
862 .port_init_hw = ppc440speB_pciex_init_port_hw,
863 .setup_utl = ppc440speB_pciex_init_utl,
864 };
865
ppc460ex_pciex_core_init(struct device_node * np)866 static int __init ppc460ex_pciex_core_init(struct device_node *np)
867 {
868 /* Nothing to do, return 2 ports */
869 return 2;
870 }
871
ppc460ex_pciex_init_port_hw(struct ppc4xx_pciex_port * port)872 static int ppc460ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
873 {
874 u32 val;
875 u32 utlset1;
876
877 if (port->endpoint)
878 val = PTYPE_LEGACY_ENDPOINT << 20;
879 else
880 val = PTYPE_ROOT_PORT << 20;
881
882 if (port->index == 0) {
883 val |= LNKW_X1 << 12;
884 utlset1 = 0x20000000;
885 } else {
886 val |= LNKW_X4 << 12;
887 utlset1 = 0x20101101;
888 }
889
890 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);
891 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, utlset1);
892 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01210000);
893
894 switch (port->index) {
895 case 0:
896 mtdcri(SDR0, PESDR0_460EX_L0CDRCTL, 0x00003230);
897 mtdcri(SDR0, PESDR0_460EX_L0DRV, 0x00000130);
898 mtdcri(SDR0, PESDR0_460EX_L0CLK, 0x00000006);
899
900 mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST,0x10000000);
901 break;
902
903 case 1:
904 mtdcri(SDR0, PESDR1_460EX_L0CDRCTL, 0x00003230);
905 mtdcri(SDR0, PESDR1_460EX_L1CDRCTL, 0x00003230);
906 mtdcri(SDR0, PESDR1_460EX_L2CDRCTL, 0x00003230);
907 mtdcri(SDR0, PESDR1_460EX_L3CDRCTL, 0x00003230);
908 mtdcri(SDR0, PESDR1_460EX_L0DRV, 0x00000130);
909 mtdcri(SDR0, PESDR1_460EX_L1DRV, 0x00000130);
910 mtdcri(SDR0, PESDR1_460EX_L2DRV, 0x00000130);
911 mtdcri(SDR0, PESDR1_460EX_L3DRV, 0x00000130);
912 mtdcri(SDR0, PESDR1_460EX_L0CLK, 0x00000006);
913 mtdcri(SDR0, PESDR1_460EX_L1CLK, 0x00000006);
914 mtdcri(SDR0, PESDR1_460EX_L2CLK, 0x00000006);
915 mtdcri(SDR0, PESDR1_460EX_L3CLK, 0x00000006);
916
917 mtdcri(SDR0, PESDR1_460EX_PHY_CTL_RST,0x10000000);
918 break;
919 }
920
921 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
922 mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) |
923 (PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTPYN));
924
925 /* Poll for PHY reset */
926 /* XXX FIXME add timeout */
927 switch (port->index) {
928 case 0:
929 while (!(mfdcri(SDR0, PESDR0_460EX_RSTSTA) & 0x1))
930 udelay(10);
931 break;
932 case 1:
933 while (!(mfdcri(SDR0, PESDR1_460EX_RSTSTA) & 0x1))
934 udelay(10);
935 break;
936 }
937
938 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
939 (mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) &
940 ~(PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTDL)) |
941 PESDRx_RCSSET_RSTPYN);
942
943 port->has_ibpre = 1;
944
945 return 0;
946 }
947
ppc460ex_pciex_init_utl(struct ppc4xx_pciex_port * port)948 static int ppc460ex_pciex_init_utl(struct ppc4xx_pciex_port *port)
949 {
950 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x0);
951
952 /*
953 * Set buffer allocations and then assert VRB and TXE.
954 */
955 out_be32(port->utl_base + PEUTL_PBCTL, 0x0800000c);
956 out_be32(port->utl_base + PEUTL_OUTTR, 0x08000000);
957 out_be32(port->utl_base + PEUTL_INTR, 0x02000000);
958 out_be32(port->utl_base + PEUTL_OPDBSZ, 0x04000000);
959 out_be32(port->utl_base + PEUTL_PBBSZ, 0x00000000);
960 out_be32(port->utl_base + PEUTL_IPHBSZ, 0x02000000);
961 out_be32(port->utl_base + PEUTL_IPDBSZ, 0x04000000);
962 out_be32(port->utl_base + PEUTL_RCIRQEN,0x00f00000);
963 out_be32(port->utl_base + PEUTL_PCTL, 0x80800066);
964
965 return 0;
966 }
967
968 static struct ppc4xx_pciex_hwops ppc460ex_pcie_hwops __initdata =
969 {
970 .core_init = ppc460ex_pciex_core_init,
971 .port_init_hw = ppc460ex_pciex_init_port_hw,
972 .setup_utl = ppc460ex_pciex_init_utl,
973 };
974
975 #endif /* CONFIG_44x */
976
977 #ifdef CONFIG_40x
978
ppc405ex_pciex_core_init(struct device_node * np)979 static int __init ppc405ex_pciex_core_init(struct device_node *np)
980 {
981 /* Nothing to do, return 2 ports */
982 return 2;
983 }
984
ppc405ex_pcie_phy_reset(struct ppc4xx_pciex_port * port)985 static void ppc405ex_pcie_phy_reset(struct ppc4xx_pciex_port *port)
986 {
987 /* Assert the PE0_PHY reset */
988 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01010000);
989 msleep(1);
990
991 /* deassert the PE0_hotreset */
992 if (port->endpoint)
993 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01111000);
994 else
995 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01101000);
996
997 /* poll for phy !reset */
998 /* XXX FIXME add timeout */
999 while (!(mfdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSTA) & 0x00001000))
1000 ;
1001
1002 /* deassert the PE0_gpl_utl_reset */
1003 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x00101000);
1004 }
1005
ppc405ex_pciex_init_port_hw(struct ppc4xx_pciex_port * port)1006 static int ppc405ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
1007 {
1008 u32 val;
1009
1010 if (port->endpoint)
1011 val = PTYPE_LEGACY_ENDPOINT;
1012 else
1013 val = PTYPE_ROOT_PORT;
1014
1015 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET,
1016 1 << 24 | val << 20 | LNKW_X1 << 12);
1017
1018 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x00000000);
1019 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01010000);
1020 mtdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSET1, 0x720F0000);
1021 mtdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSET2, 0x70600003);
1022
1023 /*
1024 * Only reset the PHY when no link is currently established.
1025 * This is for the Atheros PCIe board which has problems to establish
1026 * the link (again) after this PHY reset. All other currently tested
1027 * PCIe boards don't show this problem.
1028 * This has to be re-tested and fixed in a later release!
1029 */
1030 val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP);
1031 if (!(val & 0x00001000))
1032 ppc405ex_pcie_phy_reset(port);
1033
1034 dcr_write(port->dcrs, DCRO_PEGPL_CFG, 0x10000000); /* guarded on */
1035
1036 port->has_ibpre = 1;
1037
1038 return 0;
1039 }
1040
ppc405ex_pciex_init_utl(struct ppc4xx_pciex_port * port)1041 static int ppc405ex_pciex_init_utl(struct ppc4xx_pciex_port *port)
1042 {
1043 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x0);
1044
1045 /*
1046 * Set buffer allocations and then assert VRB and TXE.
1047 */
1048 out_be32(port->utl_base + PEUTL_OUTTR, 0x02000000);
1049 out_be32(port->utl_base + PEUTL_INTR, 0x02000000);
1050 out_be32(port->utl_base + PEUTL_OPDBSZ, 0x04000000);
1051 out_be32(port->utl_base + PEUTL_PBBSZ, 0x21000000);
1052 out_be32(port->utl_base + PEUTL_IPHBSZ, 0x02000000);
1053 out_be32(port->utl_base + PEUTL_IPDBSZ, 0x04000000);
1054 out_be32(port->utl_base + PEUTL_RCIRQEN, 0x00f00000);
1055 out_be32(port->utl_base + PEUTL_PCTL, 0x80800066);
1056
1057 out_be32(port->utl_base + PEUTL_PBCTL, 0x08000000);
1058
1059 return 0;
1060 }
1061
1062 static struct ppc4xx_pciex_hwops ppc405ex_pcie_hwops __initdata =
1063 {
1064 .core_init = ppc405ex_pciex_core_init,
1065 .port_init_hw = ppc405ex_pciex_init_port_hw,
1066 .setup_utl = ppc405ex_pciex_init_utl,
1067 };
1068
1069 #endif /* CONFIG_40x */
1070
1071
1072 /* Check that the core has been initied and if not, do it */
ppc4xx_pciex_check_core_init(struct device_node * np)1073 static int __init ppc4xx_pciex_check_core_init(struct device_node *np)
1074 {
1075 static int core_init;
1076 int count = -ENODEV;
1077
1078 if (core_init++)
1079 return 0;
1080
1081 #ifdef CONFIG_44x
1082 if (of_device_is_compatible(np, "ibm,plb-pciex-440spe")) {
1083 if (ppc440spe_revA())
1084 ppc4xx_pciex_hwops = &ppc440speA_pcie_hwops;
1085 else
1086 ppc4xx_pciex_hwops = &ppc440speB_pcie_hwops;
1087 }
1088 if (of_device_is_compatible(np, "ibm,plb-pciex-460ex"))
1089 ppc4xx_pciex_hwops = &ppc460ex_pcie_hwops;
1090 #endif /* CONFIG_44x */
1091 #ifdef CONFIG_40x
1092 if (of_device_is_compatible(np, "ibm,plb-pciex-405ex"))
1093 ppc4xx_pciex_hwops = &ppc405ex_pcie_hwops;
1094 #endif
1095 if (ppc4xx_pciex_hwops == NULL) {
1096 printk(KERN_WARNING "PCIE: unknown host type %s\n",
1097 np->full_name);
1098 return -ENODEV;
1099 }
1100
1101 count = ppc4xx_pciex_hwops->core_init(np);
1102 if (count > 0) {
1103 ppc4xx_pciex_ports =
1104 kzalloc(count * sizeof(struct ppc4xx_pciex_port),
1105 GFP_KERNEL);
1106 if (ppc4xx_pciex_ports) {
1107 ppc4xx_pciex_port_count = count;
1108 return 0;
1109 }
1110 printk(KERN_WARNING "PCIE: failed to allocate ports array\n");
1111 return -ENOMEM;
1112 }
1113 return -ENODEV;
1114 }
1115
ppc4xx_pciex_port_init_mapping(struct ppc4xx_pciex_port * port)1116 static void __init ppc4xx_pciex_port_init_mapping(struct ppc4xx_pciex_port *port)
1117 {
1118 /* We map PCI Express configuration based on the reg property */
1119 dcr_write(port->dcrs, DCRO_PEGPL_CFGBAH,
1120 RES_TO_U32_HIGH(port->cfg_space.start));
1121 dcr_write(port->dcrs, DCRO_PEGPL_CFGBAL,
1122 RES_TO_U32_LOW(port->cfg_space.start));
1123
1124 /* XXX FIXME: Use size from reg property. For now, map 512M */
1125 dcr_write(port->dcrs, DCRO_PEGPL_CFGMSK, 0xe0000001);
1126
1127 /* We map UTL registers based on the reg property */
1128 dcr_write(port->dcrs, DCRO_PEGPL_REGBAH,
1129 RES_TO_U32_HIGH(port->utl_regs.start));
1130 dcr_write(port->dcrs, DCRO_PEGPL_REGBAL,
1131 RES_TO_U32_LOW(port->utl_regs.start));
1132
1133 /* XXX FIXME: Use size from reg property */
1134 dcr_write(port->dcrs, DCRO_PEGPL_REGMSK, 0x00007001);
1135
1136 /* Disable all other outbound windows */
1137 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL, 0);
1138 dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKL, 0);
1139 dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKL, 0);
1140 dcr_write(port->dcrs, DCRO_PEGPL_MSGMSK, 0);
1141 }
1142
ppc4xx_pciex_wait_on_sdr(struct ppc4xx_pciex_port * port,unsigned int sdr_offset,unsigned int mask,unsigned int value,int timeout_ms)1143 static int __init ppc4xx_pciex_wait_on_sdr(struct ppc4xx_pciex_port *port,
1144 unsigned int sdr_offset,
1145 unsigned int mask,
1146 unsigned int value,
1147 int timeout_ms)
1148 {
1149 u32 val;
1150
1151 while(timeout_ms--) {
1152 val = mfdcri(SDR0, port->sdr_base + sdr_offset);
1153 if ((val & mask) == value) {
1154 pr_debug("PCIE%d: Wait on SDR %x success with tm %d (%08x)\n",
1155 port->index, sdr_offset, timeout_ms, val);
1156 return 0;
1157 }
1158 msleep(1);
1159 }
1160 return -1;
1161 }
1162
ppc4xx_pciex_port_init(struct ppc4xx_pciex_port * port)1163 static int __init ppc4xx_pciex_port_init(struct ppc4xx_pciex_port *port)
1164 {
1165 int rc = 0;
1166
1167 /* Init HW */
1168 if (ppc4xx_pciex_hwops->port_init_hw)
1169 rc = ppc4xx_pciex_hwops->port_init_hw(port);
1170 if (rc != 0)
1171 return rc;
1172
1173 printk(KERN_INFO "PCIE%d: Checking link...\n",
1174 port->index);
1175
1176 /* Wait for reset to complete */
1177 if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS, 1 << 20, 0, 10)) {
1178 printk(KERN_WARNING "PCIE%d: PGRST failed\n",
1179 port->index);
1180 return -1;
1181 }
1182
1183 /* Check for card presence detect if supported, if not, just wait for
1184 * link unconditionally.
1185 *
1186 * note that we don't fail if there is no link, we just filter out
1187 * config space accesses. That way, it will be easier to implement
1188 * hotplug later on.
1189 */
1190 if (!port->has_ibpre ||
1191 !ppc4xx_pciex_wait_on_sdr(port, PESDRn_LOOP,
1192 1 << 28, 1 << 28, 100)) {
1193 printk(KERN_INFO
1194 "PCIE%d: Device detected, waiting for link...\n",
1195 port->index);
1196 if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_LOOP,
1197 0x1000, 0x1000, 2000))
1198 printk(KERN_WARNING
1199 "PCIE%d: Link up failed\n", port->index);
1200 else {
1201 printk(KERN_INFO
1202 "PCIE%d: link is up !\n", port->index);
1203 port->link = 1;
1204 }
1205 } else
1206 printk(KERN_INFO "PCIE%d: No device detected.\n", port->index);
1207
1208 /*
1209 * Initialize mapping: disable all regions and configure
1210 * CFG and REG regions based on resources in the device tree
1211 */
1212 ppc4xx_pciex_port_init_mapping(port);
1213
1214 /*
1215 * Map UTL
1216 */
1217 port->utl_base = ioremap(port->utl_regs.start, 0x100);
1218 BUG_ON(port->utl_base == NULL);
1219
1220 /*
1221 * Setup UTL registers --BenH.
1222 */
1223 if (ppc4xx_pciex_hwops->setup_utl)
1224 ppc4xx_pciex_hwops->setup_utl(port);
1225
1226 /*
1227 * Check for VC0 active and assert RDY.
1228 */
1229 if (port->link &&
1230 ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS,
1231 1 << 16, 1 << 16, 5000)) {
1232 printk(KERN_INFO "PCIE%d: VC0 not active\n", port->index);
1233 port->link = 0;
1234 }
1235
1236 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, 0, 1 << 20);
1237 msleep(100);
1238
1239 return 0;
1240 }
1241
ppc4xx_pciex_validate_bdf(struct ppc4xx_pciex_port * port,struct pci_bus * bus,unsigned int devfn)1242 static int ppc4xx_pciex_validate_bdf(struct ppc4xx_pciex_port *port,
1243 struct pci_bus *bus,
1244 unsigned int devfn)
1245 {
1246 static int message;
1247
1248 /* Endpoint can not generate upstream(remote) config cycles */
1249 if (port->endpoint && bus->number != port->hose->first_busno)
1250 return PCIBIOS_DEVICE_NOT_FOUND;
1251
1252 /* Check we are within the mapped range */
1253 if (bus->number > port->hose->last_busno) {
1254 if (!message) {
1255 printk(KERN_WARNING "Warning! Probing bus %u"
1256 " out of range !\n", bus->number);
1257 message++;
1258 }
1259 return PCIBIOS_DEVICE_NOT_FOUND;
1260 }
1261
1262 /* The root complex has only one device / function */
1263 if (bus->number == port->hose->first_busno && devfn != 0)
1264 return PCIBIOS_DEVICE_NOT_FOUND;
1265
1266 /* The other side of the RC has only one device as well */
1267 if (bus->number == (port->hose->first_busno + 1) &&
1268 PCI_SLOT(devfn) != 0)
1269 return PCIBIOS_DEVICE_NOT_FOUND;
1270
1271 /* Check if we have a link */
1272 if ((bus->number != port->hose->first_busno) && !port->link)
1273 return PCIBIOS_DEVICE_NOT_FOUND;
1274
1275 return 0;
1276 }
1277
ppc4xx_pciex_get_config_base(struct ppc4xx_pciex_port * port,struct pci_bus * bus,unsigned int devfn)1278 static void __iomem *ppc4xx_pciex_get_config_base(struct ppc4xx_pciex_port *port,
1279 struct pci_bus *bus,
1280 unsigned int devfn)
1281 {
1282 int relbus;
1283
1284 /* Remove the casts when we finally remove the stupid volatile
1285 * in struct pci_controller
1286 */
1287 if (bus->number == port->hose->first_busno)
1288 return (void __iomem *)port->hose->cfg_addr;
1289
1290 relbus = bus->number - (port->hose->first_busno + 1);
1291 return (void __iomem *)port->hose->cfg_data +
1292 ((relbus << 20) | (devfn << 12));
1293 }
1294
ppc4xx_pciex_read_config(struct pci_bus * bus,unsigned int devfn,int offset,int len,u32 * val)1295 static int ppc4xx_pciex_read_config(struct pci_bus *bus, unsigned int devfn,
1296 int offset, int len, u32 *val)
1297 {
1298 struct pci_controller *hose = (struct pci_controller *) bus->sysdata;
1299 struct ppc4xx_pciex_port *port =
1300 &ppc4xx_pciex_ports[hose->indirect_type];
1301 void __iomem *addr;
1302 u32 gpl_cfg;
1303
1304 BUG_ON(hose != port->hose);
1305
1306 if (ppc4xx_pciex_validate_bdf(port, bus, devfn) != 0)
1307 return PCIBIOS_DEVICE_NOT_FOUND;
1308
1309 addr = ppc4xx_pciex_get_config_base(port, bus, devfn);
1310
1311 /*
1312 * Reading from configuration space of non-existing device can
1313 * generate transaction errors. For the read duration we suppress
1314 * assertion of machine check exceptions to avoid those.
1315 */
1316 gpl_cfg = dcr_read(port->dcrs, DCRO_PEGPL_CFG);
1317 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg | GPL_DMER_MASK_DISA);
1318
1319 /* Make sure no CRS is recorded */
1320 out_be32(port->utl_base + PEUTL_RCSTA, 0x00040000);
1321
1322 switch (len) {
1323 case 1:
1324 *val = in_8((u8 *)(addr + offset));
1325 break;
1326 case 2:
1327 *val = in_le16((u16 *)(addr + offset));
1328 break;
1329 default:
1330 *val = in_le32((u32 *)(addr + offset));
1331 break;
1332 }
1333
1334 pr_debug("pcie-config-read: bus=%3d [%3d..%3d] devfn=0x%04x"
1335 " offset=0x%04x len=%d, addr=0x%p val=0x%08x\n",
1336 bus->number, hose->first_busno, hose->last_busno,
1337 devfn, offset, len, addr + offset, *val);
1338
1339 /* Check for CRS (440SPe rev B does that for us but heh ..) */
1340 if (in_be32(port->utl_base + PEUTL_RCSTA) & 0x00040000) {
1341 pr_debug("Got CRS !\n");
1342 if (len != 4 || offset != 0)
1343 return PCIBIOS_DEVICE_NOT_FOUND;
1344 *val = 0xffff0001;
1345 }
1346
1347 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg);
1348
1349 return PCIBIOS_SUCCESSFUL;
1350 }
1351
ppc4xx_pciex_write_config(struct pci_bus * bus,unsigned int devfn,int offset,int len,u32 val)1352 static int ppc4xx_pciex_write_config(struct pci_bus *bus, unsigned int devfn,
1353 int offset, int len, u32 val)
1354 {
1355 struct pci_controller *hose = (struct pci_controller *) bus->sysdata;
1356 struct ppc4xx_pciex_port *port =
1357 &ppc4xx_pciex_ports[hose->indirect_type];
1358 void __iomem *addr;
1359 u32 gpl_cfg;
1360
1361 if (ppc4xx_pciex_validate_bdf(port, bus, devfn) != 0)
1362 return PCIBIOS_DEVICE_NOT_FOUND;
1363
1364 addr = ppc4xx_pciex_get_config_base(port, bus, devfn);
1365
1366 /*
1367 * Reading from configuration space of non-existing device can
1368 * generate transaction errors. For the read duration we suppress
1369 * assertion of machine check exceptions to avoid those.
1370 */
1371 gpl_cfg = dcr_read(port->dcrs, DCRO_PEGPL_CFG);
1372 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg | GPL_DMER_MASK_DISA);
1373
1374 pr_debug("pcie-config-write: bus=%3d [%3d..%3d] devfn=0x%04x"
1375 " offset=0x%04x len=%d, addr=0x%p val=0x%08x\n",
1376 bus->number, hose->first_busno, hose->last_busno,
1377 devfn, offset, len, addr + offset, val);
1378
1379 switch (len) {
1380 case 1:
1381 out_8((u8 *)(addr + offset), val);
1382 break;
1383 case 2:
1384 out_le16((u16 *)(addr + offset), val);
1385 break;
1386 default:
1387 out_le32((u32 *)(addr + offset), val);
1388 break;
1389 }
1390
1391 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg);
1392
1393 return PCIBIOS_SUCCESSFUL;
1394 }
1395
1396 static struct pci_ops ppc4xx_pciex_pci_ops =
1397 {
1398 .read = ppc4xx_pciex_read_config,
1399 .write = ppc4xx_pciex_write_config,
1400 };
1401
ppc4xx_setup_one_pciex_POM(struct ppc4xx_pciex_port * port,struct pci_controller * hose,void __iomem * mbase,u64 plb_addr,u64 pci_addr,u64 size,unsigned int flags,int index)1402 static int __init ppc4xx_setup_one_pciex_POM(struct ppc4xx_pciex_port *port,
1403 struct pci_controller *hose,
1404 void __iomem *mbase,
1405 u64 plb_addr,
1406 u64 pci_addr,
1407 u64 size,
1408 unsigned int flags,
1409 int index)
1410 {
1411 u32 lah, lal, pciah, pcial, sa;
1412
1413 if (!is_power_of_2(size) ||
1414 (index < 2 && size < 0x100000) ||
1415 (index == 2 && size < 0x100) ||
1416 (plb_addr & (size - 1)) != 0) {
1417 printk(KERN_WARNING "%s: Resource out of range\n",
1418 hose->dn->full_name);
1419 return -1;
1420 }
1421
1422 /* Calculate register values */
1423 lah = RES_TO_U32_HIGH(plb_addr);
1424 lal = RES_TO_U32_LOW(plb_addr);
1425 pciah = RES_TO_U32_HIGH(pci_addr);
1426 pcial = RES_TO_U32_LOW(pci_addr);
1427 sa = (0xffffffffu << ilog2(size)) | 0x1;
1428
1429 /* Program register values */
1430 switch (index) {
1431 case 0:
1432 out_le32(mbase + PECFG_POM0LAH, pciah);
1433 out_le32(mbase + PECFG_POM0LAL, pcial);
1434 dcr_write(port->dcrs, DCRO_PEGPL_OMR1BAH, lah);
1435 dcr_write(port->dcrs, DCRO_PEGPL_OMR1BAL, lal);
1436 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKH, 0x7fffffff);
1437 /* Note that 3 here means enabled | single region */
1438 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL, sa | 3);
1439 break;
1440 case 1:
1441 out_le32(mbase + PECFG_POM1LAH, pciah);
1442 out_le32(mbase + PECFG_POM1LAL, pcial);
1443 dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAH, lah);
1444 dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAL, lal);
1445 dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKH, 0x7fffffff);
1446 /* Note that 3 here means enabled | single region */
1447 dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKL, sa | 3);
1448 break;
1449 case 2:
1450 out_le32(mbase + PECFG_POM2LAH, pciah);
1451 out_le32(mbase + PECFG_POM2LAL, pcial);
1452 dcr_write(port->dcrs, DCRO_PEGPL_OMR3BAH, lah);
1453 dcr_write(port->dcrs, DCRO_PEGPL_OMR3BAL, lal);
1454 dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKH, 0x7fffffff);
1455 /* Note that 3 here means enabled | IO space !!! */
1456 dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKL, sa | 3);
1457 break;
1458 }
1459
1460 return 0;
1461 }
1462
ppc4xx_configure_pciex_POMs(struct ppc4xx_pciex_port * port,struct pci_controller * hose,void __iomem * mbase)1463 static void __init ppc4xx_configure_pciex_POMs(struct ppc4xx_pciex_port *port,
1464 struct pci_controller *hose,
1465 void __iomem *mbase)
1466 {
1467 int i, j, found_isa_hole = 0;
1468
1469 /* Setup outbound memory windows */
1470 for (i = j = 0; i < 3; i++) {
1471 struct resource *res = &hose->mem_resources[i];
1472
1473 /* we only care about memory windows */
1474 if (!(res->flags & IORESOURCE_MEM))
1475 continue;
1476 if (j > 1) {
1477 printk(KERN_WARNING "%s: Too many ranges\n",
1478 port->node->full_name);
1479 break;
1480 }
1481
1482 /* Configure the resource */
1483 if (ppc4xx_setup_one_pciex_POM(port, hose, mbase,
1484 res->start,
1485 res->start - hose->pci_mem_offset,
1486 res->end + 1 - res->start,
1487 res->flags,
1488 j) == 0) {
1489 j++;
1490
1491 /* If the resource PCI address is 0 then we have our
1492 * ISA memory hole
1493 */
1494 if (res->start == hose->pci_mem_offset)
1495 found_isa_hole = 1;
1496 }
1497 }
1498
1499 /* Handle ISA memory hole if not already covered */
1500 if (j <= 1 && !found_isa_hole && hose->isa_mem_size)
1501 if (ppc4xx_setup_one_pciex_POM(port, hose, mbase,
1502 hose->isa_mem_phys, 0,
1503 hose->isa_mem_size, 0, j) == 0)
1504 printk(KERN_INFO "%s: Legacy ISA memory support enabled\n",
1505 hose->dn->full_name);
1506
1507 /* Configure IO, always 64K starting at 0. We hard wire it to 64K !
1508 * Note also that it -has- to be region index 2 on this HW
1509 */
1510 if (hose->io_resource.flags & IORESOURCE_IO)
1511 ppc4xx_setup_one_pciex_POM(port, hose, mbase,
1512 hose->io_base_phys, 0,
1513 0x10000, IORESOURCE_IO, 2);
1514 }
1515
ppc4xx_configure_pciex_PIMs(struct ppc4xx_pciex_port * port,struct pci_controller * hose,void __iomem * mbase,struct resource * res)1516 static void __init ppc4xx_configure_pciex_PIMs(struct ppc4xx_pciex_port *port,
1517 struct pci_controller *hose,
1518 void __iomem *mbase,
1519 struct resource *res)
1520 {
1521 resource_size_t size = res->end - res->start + 1;
1522 u64 sa;
1523
1524 if (port->endpoint) {
1525 resource_size_t ep_addr = 0;
1526 resource_size_t ep_size = 32 << 20;
1527
1528 /* Currently we map a fixed 64MByte window to PLB address
1529 * 0 (SDRAM). This should probably be configurable via a dts
1530 * property.
1531 */
1532
1533 /* Calculate window size */
1534 sa = (0xffffffffffffffffull << ilog2(ep_size));;
1535
1536 /* Setup BAR0 */
1537 out_le32(mbase + PECFG_BAR0HMPA, RES_TO_U32_HIGH(sa));
1538 out_le32(mbase + PECFG_BAR0LMPA, RES_TO_U32_LOW(sa) |
1539 PCI_BASE_ADDRESS_MEM_TYPE_64);
1540
1541 /* Disable BAR1 & BAR2 */
1542 out_le32(mbase + PECFG_BAR1MPA, 0);
1543 out_le32(mbase + PECFG_BAR2HMPA, 0);
1544 out_le32(mbase + PECFG_BAR2LMPA, 0);
1545
1546 out_le32(mbase + PECFG_PIM01SAH, RES_TO_U32_HIGH(sa));
1547 out_le32(mbase + PECFG_PIM01SAL, RES_TO_U32_LOW(sa));
1548
1549 out_le32(mbase + PCI_BASE_ADDRESS_0, RES_TO_U32_LOW(ep_addr));
1550 out_le32(mbase + PCI_BASE_ADDRESS_1, RES_TO_U32_HIGH(ep_addr));
1551 } else {
1552 /* Calculate window size */
1553 sa = (0xffffffffffffffffull << ilog2(size));;
1554 if (res->flags & IORESOURCE_PREFETCH)
1555 sa |= 0x8;
1556
1557 out_le32(mbase + PECFG_BAR0HMPA, RES_TO_U32_HIGH(sa));
1558 out_le32(mbase + PECFG_BAR0LMPA, RES_TO_U32_LOW(sa));
1559
1560 /* The setup of the split looks weird to me ... let's see
1561 * if it works
1562 */
1563 out_le32(mbase + PECFG_PIM0LAL, 0x00000000);
1564 out_le32(mbase + PECFG_PIM0LAH, 0x00000000);
1565 out_le32(mbase + PECFG_PIM1LAL, 0x00000000);
1566 out_le32(mbase + PECFG_PIM1LAH, 0x00000000);
1567 out_le32(mbase + PECFG_PIM01SAH, 0xffff0000);
1568 out_le32(mbase + PECFG_PIM01SAL, 0x00000000);
1569
1570 out_le32(mbase + PCI_BASE_ADDRESS_0, RES_TO_U32_LOW(res->start));
1571 out_le32(mbase + PCI_BASE_ADDRESS_1, RES_TO_U32_HIGH(res->start));
1572 }
1573
1574 /* Enable inbound mapping */
1575 out_le32(mbase + PECFG_PIMEN, 0x1);
1576
1577 /* Enable I/O, Mem, and Busmaster cycles */
1578 out_le16(mbase + PCI_COMMAND,
1579 in_le16(mbase + PCI_COMMAND) |
1580 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
1581 }
1582
ppc4xx_pciex_port_setup_hose(struct ppc4xx_pciex_port * port)1583 static void __init ppc4xx_pciex_port_setup_hose(struct ppc4xx_pciex_port *port)
1584 {
1585 struct resource dma_window;
1586 struct pci_controller *hose = NULL;
1587 const int *bus_range;
1588 int primary = 0, busses;
1589 void __iomem *mbase = NULL, *cfg_data = NULL;
1590 const u32 *pval;
1591 u32 val;
1592
1593 /* Check if primary bridge */
1594 if (of_get_property(port->node, "primary", NULL))
1595 primary = 1;
1596
1597 /* Get bus range if any */
1598 bus_range = of_get_property(port->node, "bus-range", NULL);
1599
1600 /* Allocate the host controller data structure */
1601 hose = pcibios_alloc_controller(port->node);
1602 if (!hose)
1603 goto fail;
1604
1605 /* We stick the port number in "indirect_type" so the config space
1606 * ops can retrieve the port data structure easily
1607 */
1608 hose->indirect_type = port->index;
1609
1610 /* Get bus range */
1611 hose->first_busno = bus_range ? bus_range[0] : 0x0;
1612 hose->last_busno = bus_range ? bus_range[1] : 0xff;
1613
1614 /* Because of how big mapping the config space is (1M per bus), we
1615 * limit how many busses we support. In the long run, we could replace
1616 * that with something akin to kmap_atomic instead. We set aside 1 bus
1617 * for the host itself too.
1618 */
1619 busses = hose->last_busno - hose->first_busno; /* This is off by 1 */
1620 if (busses > MAX_PCIE_BUS_MAPPED) {
1621 busses = MAX_PCIE_BUS_MAPPED;
1622 hose->last_busno = hose->first_busno + busses;
1623 }
1624
1625 if (!port->endpoint) {
1626 /* Only map the external config space in cfg_data for
1627 * PCIe root-complexes. External space is 1M per bus
1628 */
1629 cfg_data = ioremap(port->cfg_space.start +
1630 (hose->first_busno + 1) * 0x100000,
1631 busses * 0x100000);
1632 if (cfg_data == NULL) {
1633 printk(KERN_ERR "%s: Can't map external config space !",
1634 port->node->full_name);
1635 goto fail;
1636 }
1637 hose->cfg_data = cfg_data;
1638 }
1639
1640 /* Always map the host config space in cfg_addr.
1641 * Internal space is 4K
1642 */
1643 mbase = ioremap(port->cfg_space.start + 0x10000000, 0x1000);
1644 if (mbase == NULL) {
1645 printk(KERN_ERR "%s: Can't map internal config space !",
1646 port->node->full_name);
1647 goto fail;
1648 }
1649 hose->cfg_addr = mbase;
1650
1651 pr_debug("PCIE %s, bus %d..%d\n", port->node->full_name,
1652 hose->first_busno, hose->last_busno);
1653 pr_debug(" config space mapped at: root @0x%p, other @0x%p\n",
1654 hose->cfg_addr, hose->cfg_data);
1655
1656 /* Setup config space */
1657 hose->ops = &ppc4xx_pciex_pci_ops;
1658 port->hose = hose;
1659 mbase = (void __iomem *)hose->cfg_addr;
1660
1661 if (!port->endpoint) {
1662 /*
1663 * Set bus numbers on our root port
1664 */
1665 out_8(mbase + PCI_PRIMARY_BUS, hose->first_busno);
1666 out_8(mbase + PCI_SECONDARY_BUS, hose->first_busno + 1);
1667 out_8(mbase + PCI_SUBORDINATE_BUS, hose->last_busno);
1668 }
1669
1670 /*
1671 * OMRs are already reset, also disable PIMs
1672 */
1673 out_le32(mbase + PECFG_PIMEN, 0);
1674
1675 /* Parse outbound mapping resources */
1676 pci_process_bridge_OF_ranges(hose, port->node, primary);
1677
1678 /* Parse inbound mapping resources */
1679 if (ppc4xx_parse_dma_ranges(hose, mbase, &dma_window) != 0)
1680 goto fail;
1681
1682 /* Configure outbound ranges POMs */
1683 ppc4xx_configure_pciex_POMs(port, hose, mbase);
1684
1685 /* Configure inbound ranges PIMs */
1686 ppc4xx_configure_pciex_PIMs(port, hose, mbase, &dma_window);
1687
1688 /* The root complex doesn't show up if we don't set some vendor
1689 * and device IDs into it. The defaults below are the same bogus
1690 * one that the initial code in arch/ppc had. This can be
1691 * overwritten by setting the "vendor-id/device-id" properties
1692 * in the pciex node.
1693 */
1694
1695 /* Get the (optional) vendor-/device-id from the device-tree */
1696 pval = of_get_property(port->node, "vendor-id", NULL);
1697 if (pval) {
1698 val = *pval;
1699 } else {
1700 if (!port->endpoint)
1701 val = 0xaaa0 + port->index;
1702 else
1703 val = 0xeee0 + port->index;
1704 }
1705 out_le16(mbase + 0x200, val);
1706
1707 pval = of_get_property(port->node, "device-id", NULL);
1708 if (pval) {
1709 val = *pval;
1710 } else {
1711 if (!port->endpoint)
1712 val = 0xbed0 + port->index;
1713 else
1714 val = 0xfed0 + port->index;
1715 }
1716 out_le16(mbase + 0x202, val);
1717
1718 if (!port->endpoint) {
1719 /* Set Class Code to PCI-PCI bridge and Revision Id to 1 */
1720 out_le32(mbase + 0x208, 0x06040001);
1721
1722 printk(KERN_INFO "PCIE%d: successfully set as root-complex\n",
1723 port->index);
1724 } else {
1725 /* Set Class Code to Processor/PPC */
1726 out_le32(mbase + 0x208, 0x0b200001);
1727
1728 printk(KERN_INFO "PCIE%d: successfully set as endpoint\n",
1729 port->index);
1730 }
1731
1732 return;
1733 fail:
1734 if (hose)
1735 pcibios_free_controller(hose);
1736 if (cfg_data)
1737 iounmap(cfg_data);
1738 if (mbase)
1739 iounmap(mbase);
1740 }
1741
ppc4xx_probe_pciex_bridge(struct device_node * np)1742 static void __init ppc4xx_probe_pciex_bridge(struct device_node *np)
1743 {
1744 struct ppc4xx_pciex_port *port;
1745 const u32 *pval;
1746 int portno;
1747 unsigned int dcrs;
1748 const char *val;
1749
1750 /* First, proceed to core initialization as we assume there's
1751 * only one PCIe core in the system
1752 */
1753 if (ppc4xx_pciex_check_core_init(np))
1754 return;
1755
1756 /* Get the port number from the device-tree */
1757 pval = of_get_property(np, "port", NULL);
1758 if (pval == NULL) {
1759 printk(KERN_ERR "PCIE: Can't find port number for %s\n",
1760 np->full_name);
1761 return;
1762 }
1763 portno = *pval;
1764 if (portno >= ppc4xx_pciex_port_count) {
1765 printk(KERN_ERR "PCIE: port number out of range for %s\n",
1766 np->full_name);
1767 return;
1768 }
1769 port = &ppc4xx_pciex_ports[portno];
1770 port->index = portno;
1771
1772 /*
1773 * Check if device is enabled
1774 */
1775 if (!of_device_is_available(np)) {
1776 printk(KERN_INFO "PCIE%d: Port disabled via device-tree\n", port->index);
1777 return;
1778 }
1779
1780 port->node = of_node_get(np);
1781 pval = of_get_property(np, "sdr-base", NULL);
1782 if (pval == NULL) {
1783 printk(KERN_ERR "PCIE: missing sdr-base for %s\n",
1784 np->full_name);
1785 return;
1786 }
1787 port->sdr_base = *pval;
1788
1789 /* Check if device_type property is set to "pci" or "pci-endpoint".
1790 * Resulting from this setup this PCIe port will be configured
1791 * as root-complex or as endpoint.
1792 */
1793 val = of_get_property(port->node, "device_type", NULL);
1794 if (!strcmp(val, "pci-endpoint")) {
1795 port->endpoint = 1;
1796 } else if (!strcmp(val, "pci")) {
1797 port->endpoint = 0;
1798 } else {
1799 printk(KERN_ERR "PCIE: missing or incorrect device_type for %s\n",
1800 np->full_name);
1801 return;
1802 }
1803
1804 /* Fetch config space registers address */
1805 if (of_address_to_resource(np, 0, &port->cfg_space)) {
1806 printk(KERN_ERR "%s: Can't get PCI-E config space !",
1807 np->full_name);
1808 return;
1809 }
1810 /* Fetch host bridge internal registers address */
1811 if (of_address_to_resource(np, 1, &port->utl_regs)) {
1812 printk(KERN_ERR "%s: Can't get UTL register base !",
1813 np->full_name);
1814 return;
1815 }
1816
1817 /* Map DCRs */
1818 dcrs = dcr_resource_start(np, 0);
1819 if (dcrs == 0) {
1820 printk(KERN_ERR "%s: Can't get DCR register base !",
1821 np->full_name);
1822 return;
1823 }
1824 port->dcrs = dcr_map(np, dcrs, dcr_resource_len(np, 0));
1825
1826 /* Initialize the port specific registers */
1827 if (ppc4xx_pciex_port_init(port)) {
1828 printk(KERN_WARNING "PCIE%d: Port init failed\n", port->index);
1829 return;
1830 }
1831
1832 /* Setup the linux hose data structure */
1833 ppc4xx_pciex_port_setup_hose(port);
1834 }
1835
1836 #endif /* CONFIG_PPC4xx_PCI_EXPRESS */
1837
ppc4xx_pci_find_bridges(void)1838 static int __init ppc4xx_pci_find_bridges(void)
1839 {
1840 struct device_node *np;
1841
1842 #ifdef CONFIG_PPC4xx_PCI_EXPRESS
1843 for_each_compatible_node(np, NULL, "ibm,plb-pciex")
1844 ppc4xx_probe_pciex_bridge(np);
1845 #endif
1846 for_each_compatible_node(np, NULL, "ibm,plb-pcix")
1847 ppc4xx_probe_pcix_bridge(np);
1848 for_each_compatible_node(np, NULL, "ibm,plb-pci")
1849 ppc4xx_probe_pci_bridge(np);
1850
1851 return 0;
1852 }
1853 arch_initcall(ppc4xx_pci_find_bridges);
1854
1855