1 #ifndef _ASM_X86_MMU_CONTEXT_32_H
2 #define _ASM_X86_MMU_CONTEXT_32_H
3
enter_lazy_tlb(struct mm_struct * mm,struct task_struct * tsk)4 static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
5 {
6 #ifdef CONFIG_SMP
7 if (x86_read_percpu(cpu_tlbstate.state) == TLBSTATE_OK)
8 x86_write_percpu(cpu_tlbstate.state, TLBSTATE_LAZY);
9 #endif
10 }
11
switch_mm(struct mm_struct * prev,struct mm_struct * next,struct task_struct * tsk)12 static inline void switch_mm(struct mm_struct *prev,
13 struct mm_struct *next,
14 struct task_struct *tsk)
15 {
16 int cpu = smp_processor_id();
17
18 if (likely(prev != next)) {
19 /* stop flush ipis for the previous mm */
20 cpu_clear(cpu, prev->cpu_vm_mask);
21 #ifdef CONFIG_SMP
22 x86_write_percpu(cpu_tlbstate.state, TLBSTATE_OK);
23 x86_write_percpu(cpu_tlbstate.active_mm, next);
24 #endif
25 cpu_set(cpu, next->cpu_vm_mask);
26
27 /* Re-load page tables */
28 load_cr3(next->pgd);
29
30 /*
31 * load the LDT, if the LDT is different:
32 */
33 if (unlikely(prev->context.ldt != next->context.ldt))
34 load_LDT_nolock(&next->context);
35 }
36 #ifdef CONFIG_SMP
37 else {
38 x86_write_percpu(cpu_tlbstate.state, TLBSTATE_OK);
39 BUG_ON(x86_read_percpu(cpu_tlbstate.active_mm) != next);
40
41 if (!cpu_test_and_set(cpu, next->cpu_vm_mask)) {
42 /* We were in lazy tlb mode and leave_mm disabled
43 * tlb flush IPI delivery. We must reload %cr3.
44 */
45 load_cr3(next->pgd);
46 load_LDT_nolock(&next->context);
47 }
48 }
49 #endif
50 }
51
52 #define deactivate_mm(tsk, mm) \
53 asm("movl %0,%%gs": :"r" (0));
54
55 #endif /* _ASM_X86_MMU_CONTEXT_32_H */
56