1 #ifndef _ASM_X86_MSR_H
2 #define _ASM_X86_MSR_H
3
4 #include <asm/msr-index.h>
5
6 #ifndef __ASSEMBLY__
7 # include <linux/types.h>
8 #endif
9
10 #ifdef __KERNEL__
11 #ifndef __ASSEMBLY__
12
13 #include <asm/asm.h>
14 #include <asm/errno.h>
15
native_read_tscp(unsigned int * aux)16 static inline unsigned long long native_read_tscp(unsigned int *aux)
17 {
18 unsigned long low, high;
19 asm volatile(".byte 0x0f,0x01,0xf9"
20 : "=a" (low), "=d" (high), "=c" (*aux));
21 return low | ((u64)high << 32);
22 }
23
24 /*
25 * both i386 and x86_64 returns 64-bit value in edx:eax, but gcc's "A"
26 * constraint has different meanings. For i386, "A" means exactly
27 * edx:eax, while for x86_64 it doesn't mean rdx:rax or edx:eax. Instead,
28 * it means rax *or* rdx.
29 */
30 #ifdef CONFIG_X86_64
31 #define DECLARE_ARGS(val, low, high) unsigned low, high
32 #define EAX_EDX_VAL(val, low, high) ((low) | ((u64)(high) << 32))
33 #define EAX_EDX_ARGS(val, low, high) "a" (low), "d" (high)
34 #define EAX_EDX_RET(val, low, high) "=a" (low), "=d" (high)
35 #else
36 #define DECLARE_ARGS(val, low, high) unsigned long long val
37 #define EAX_EDX_VAL(val, low, high) (val)
38 #define EAX_EDX_ARGS(val, low, high) "A" (val)
39 #define EAX_EDX_RET(val, low, high) "=A" (val)
40 #endif
41
native_read_msr(unsigned int msr)42 static inline unsigned long long native_read_msr(unsigned int msr)
43 {
44 DECLARE_ARGS(val, low, high);
45
46 asm volatile("rdmsr" : EAX_EDX_RET(val, low, high) : "c" (msr));
47 return EAX_EDX_VAL(val, low, high);
48 }
49
native_read_msr_safe(unsigned int msr,int * err)50 static inline unsigned long long native_read_msr_safe(unsigned int msr,
51 int *err)
52 {
53 DECLARE_ARGS(val, low, high);
54
55 asm volatile("2: rdmsr ; xor %[err],%[err]\n"
56 "1:\n\t"
57 ".section .fixup,\"ax\"\n\t"
58 "3: mov %[fault],%[err] ; jmp 1b\n\t"
59 ".previous\n\t"
60 _ASM_EXTABLE(2b, 3b)
61 : [err] "=r" (*err), EAX_EDX_RET(val, low, high)
62 : "c" (msr), [fault] "i" (-EFAULT));
63 return EAX_EDX_VAL(val, low, high);
64 }
65
native_read_msr_amd_safe(unsigned int msr,int * err)66 static inline unsigned long long native_read_msr_amd_safe(unsigned int msr,
67 int *err)
68 {
69 DECLARE_ARGS(val, low, high);
70
71 asm volatile("2: rdmsr ; xor %0,%0\n"
72 "1:\n\t"
73 ".section .fixup,\"ax\"\n\t"
74 "3: mov %3,%0 ; jmp 1b\n\t"
75 ".previous\n\t"
76 _ASM_EXTABLE(2b, 3b)
77 : "=r" (*err), EAX_EDX_RET(val, low, high)
78 : "c" (msr), "D" (0x9c5a203a), "i" (-EFAULT));
79 return EAX_EDX_VAL(val, low, high);
80 }
81
native_write_msr(unsigned int msr,unsigned low,unsigned high)82 static inline void native_write_msr(unsigned int msr,
83 unsigned low, unsigned high)
84 {
85 asm volatile("wrmsr" : : "c" (msr), "a"(low), "d" (high) : "memory");
86 }
87
88 /* Can be uninlined because referenced by paravirt */
native_write_msr_safe(unsigned int msr,unsigned low,unsigned high)89 notrace static inline int native_write_msr_safe(unsigned int msr,
90 unsigned low, unsigned high)
91 {
92 int err;
93 asm volatile("2: wrmsr ; xor %[err],%[err]\n"
94 "1:\n\t"
95 ".section .fixup,\"ax\"\n\t"
96 "3: mov %[fault],%[err] ; jmp 1b\n\t"
97 ".previous\n\t"
98 _ASM_EXTABLE(2b, 3b)
99 : [err] "=a" (err)
100 : "c" (msr), "0" (low), "d" (high),
101 [fault] "i" (-EFAULT)
102 : "memory");
103 return err;
104 }
105
106 extern unsigned long long native_read_tsc(void);
107
__native_read_tsc(void)108 static __always_inline unsigned long long __native_read_tsc(void)
109 {
110 DECLARE_ARGS(val, low, high);
111
112 asm volatile("rdtsc" : EAX_EDX_RET(val, low, high));
113
114 return EAX_EDX_VAL(val, low, high);
115 }
116
native_read_pmc(int counter)117 static inline unsigned long long native_read_pmc(int counter)
118 {
119 DECLARE_ARGS(val, low, high);
120
121 asm volatile("rdpmc" : EAX_EDX_RET(val, low, high) : "c" (counter));
122 return EAX_EDX_VAL(val, low, high);
123 }
124
125 #ifdef CONFIG_PARAVIRT
126 #include <asm/paravirt.h>
127 #else
128 #include <linux/errno.h>
129 /*
130 * Access to machine-specific registers (available on 586 and better only)
131 * Note: the rd* operations modify the parameters directly (without using
132 * pointer indirection), this allows gcc to optimize better
133 */
134
135 #define rdmsr(msr, val1, val2) \
136 do { \
137 u64 __val = native_read_msr((msr)); \
138 (val1) = (u32)__val; \
139 (val2) = (u32)(__val >> 32); \
140 } while (0)
141
wrmsr(unsigned msr,unsigned low,unsigned high)142 static inline void wrmsr(unsigned msr, unsigned low, unsigned high)
143 {
144 native_write_msr(msr, low, high);
145 }
146
147 #define rdmsrl(msr, val) \
148 ((val) = native_read_msr((msr)))
149
150 #define wrmsrl(msr, val) \
151 native_write_msr((msr), (u32)((u64)(val)), (u32)((u64)(val) >> 32))
152
153 /* wrmsr with exception handling */
wrmsr_safe(unsigned msr,unsigned low,unsigned high)154 static inline int wrmsr_safe(unsigned msr, unsigned low, unsigned high)
155 {
156 return native_write_msr_safe(msr, low, high);
157 }
158
159 /* rdmsr with exception handling */
160 #define rdmsr_safe(msr, p1, p2) \
161 ({ \
162 int __err; \
163 u64 __val = native_read_msr_safe((msr), &__err); \
164 (*p1) = (u32)__val; \
165 (*p2) = (u32)(__val >> 32); \
166 __err; \
167 })
168
rdmsrl_safe(unsigned msr,unsigned long long * p)169 static inline int rdmsrl_safe(unsigned msr, unsigned long long *p)
170 {
171 int err;
172
173 *p = native_read_msr_safe(msr, &err);
174 return err;
175 }
rdmsrl_amd_safe(unsigned msr,unsigned long long * p)176 static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)
177 {
178 int err;
179
180 *p = native_read_msr_amd_safe(msr, &err);
181 return err;
182 }
183
184 #define rdtscl(low) \
185 ((low) = (u32)__native_read_tsc())
186
187 #define rdtscll(val) \
188 ((val) = __native_read_tsc())
189
190 #define rdpmc(counter, low, high) \
191 do { \
192 u64 _l = native_read_pmc((counter)); \
193 (low) = (u32)_l; \
194 (high) = (u32)(_l >> 32); \
195 } while (0)
196
197 #define rdtscp(low, high, aux) \
198 do { \
199 unsigned long long _val = native_read_tscp(&(aux)); \
200 (low) = (u32)_val; \
201 (high) = (u32)(_val >> 32); \
202 } while (0)
203
204 #define rdtscpll(val, aux) (val) = native_read_tscp(&(aux))
205
206 #endif /* !CONFIG_PARAVIRT */
207
208
209 #define checking_wrmsrl(msr, val) wrmsr_safe((msr), (u32)(val), \
210 (u32)((val) >> 32))
211
212 #define write_tsc(val1, val2) wrmsr(0x10, (val1), (val2))
213
214 #define write_rdtscp_aux(val) wrmsr(0xc0000103, (val), 0)
215
216 #ifdef CONFIG_SMP
217 int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
218 int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
219 int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
220 int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
221 #else /* CONFIG_SMP */
rdmsr_on_cpu(unsigned int cpu,u32 msr_no,u32 * l,u32 * h)222 static inline int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h)
223 {
224 rdmsr(msr_no, *l, *h);
225 return 0;
226 }
wrmsr_on_cpu(unsigned int cpu,u32 msr_no,u32 l,u32 h)227 static inline int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
228 {
229 wrmsr(msr_no, l, h);
230 return 0;
231 }
rdmsr_safe_on_cpu(unsigned int cpu,u32 msr_no,u32 * l,u32 * h)232 static inline int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no,
233 u32 *l, u32 *h)
234 {
235 return rdmsr_safe(msr_no, l, h);
236 }
wrmsr_safe_on_cpu(unsigned int cpu,u32 msr_no,u32 l,u32 h)237 static inline int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
238 {
239 return wrmsr_safe(msr_no, l, h);
240 }
241 #endif /* CONFIG_SMP */
242 #endif /* __ASSEMBLY__ */
243 #endif /* __KERNEL__ */
244
245
246 #endif /* _ASM_X86_MSR_H */
247