1 /*
2 * Copyright (C) 2005 Intel Corporation
3 * Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
4 * - Added _PDC for SMP C-states on Intel CPUs
5 */
6
7 #include <linux/kernel.h>
8 #include <linux/module.h>
9 #include <linux/init.h>
10 #include <linux/acpi.h>
11 #include <linux/cpu.h>
12 #include <linux/sched.h>
13
14 #include <acpi/processor.h>
15 #include <asm/acpi.h>
16
17 /*
18 * Initialize bm_flags based on the CPU cache properties
19 * On SMP it depends on cache configuration
20 * - When cache is not shared among all CPUs, we flush cache
21 * before entering C3.
22 * - When cache is shared among all CPUs, we use bm_check
23 * mechanism as in UP case
24 *
25 * This routine is called only after all the CPUs are online
26 */
acpi_processor_power_init_bm_check(struct acpi_processor_flags * flags,unsigned int cpu)27 void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags,
28 unsigned int cpu)
29 {
30 struct cpuinfo_x86 *c = &cpu_data(cpu);
31
32 flags->bm_check = 0;
33 if (num_online_cpus() == 1)
34 flags->bm_check = 1;
35 else if (c->x86_vendor == X86_VENDOR_INTEL) {
36 /*
37 * Today all CPUs that support C3 share cache.
38 * TBD: This needs to look at cache shared map, once
39 * multi-core detection patch makes to the base.
40 */
41 flags->bm_check = 1;
42 }
43 }
44 EXPORT_SYMBOL(acpi_processor_power_init_bm_check);
45
46 /* The code below handles cstate entry with monitor-mwait pair on Intel*/
47
48 struct cstate_entry {
49 struct {
50 unsigned int eax;
51 unsigned int ecx;
52 } states[ACPI_PROCESSOR_MAX_POWER];
53 };
54 static struct cstate_entry *cpu_cstate_entry; /* per CPU ptr */
55
56 static short mwait_supported[ACPI_PROCESSOR_MAX_POWER];
57
58 #define MWAIT_SUBSTATE_MASK (0xf)
59 #define MWAIT_CSTATE_MASK (0xf)
60 #define MWAIT_SUBSTATE_SIZE (4)
61
62 #define CPUID_MWAIT_LEAF (5)
63 #define CPUID5_ECX_EXTENSIONS_SUPPORTED (0x1)
64 #define CPUID5_ECX_INTERRUPT_BREAK (0x2)
65
66 #define MWAIT_ECX_INTERRUPT_BREAK (0x1)
67
68 #define NATIVE_CSTATE_BEYOND_HALT (2)
69
acpi_processor_ffh_cstate_probe_cpu(void * _cx)70 static long acpi_processor_ffh_cstate_probe_cpu(void *_cx)
71 {
72 struct acpi_processor_cx *cx = _cx;
73 long retval;
74 unsigned int eax, ebx, ecx, edx;
75 unsigned int edx_part;
76 unsigned int cstate_type; /* C-state type and not ACPI C-state type */
77 unsigned int num_cstate_subtype;
78
79 cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &edx);
80
81 /* Check whether this particular cx_type (in CST) is supported or not */
82 cstate_type = ((cx->address >> MWAIT_SUBSTATE_SIZE) &
83 MWAIT_CSTATE_MASK) + 1;
84 edx_part = edx >> (cstate_type * MWAIT_SUBSTATE_SIZE);
85 num_cstate_subtype = edx_part & MWAIT_SUBSTATE_MASK;
86
87 retval = 0;
88 if (num_cstate_subtype < (cx->address & MWAIT_SUBSTATE_MASK)) {
89 retval = -1;
90 goto out;
91 }
92
93 /* mwait ecx extensions INTERRUPT_BREAK should be supported for C2/C3 */
94 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) ||
95 !(ecx & CPUID5_ECX_INTERRUPT_BREAK)) {
96 retval = -1;
97 goto out;
98 }
99
100 if (!mwait_supported[cstate_type]) {
101 mwait_supported[cstate_type] = 1;
102 printk(KERN_DEBUG
103 "Monitor-Mwait will be used to enter C-%d "
104 "state\n", cx->type);
105 }
106 snprintf(cx->desc,
107 ACPI_CX_DESC_LEN, "ACPI FFH INTEL MWAIT 0x%x",
108 cx->address);
109 out:
110 return retval;
111 }
112
acpi_processor_ffh_cstate_probe(unsigned int cpu,struct acpi_processor_cx * cx,struct acpi_power_register * reg)113 int acpi_processor_ffh_cstate_probe(unsigned int cpu,
114 struct acpi_processor_cx *cx, struct acpi_power_register *reg)
115 {
116 struct cstate_entry *percpu_entry;
117 struct cpuinfo_x86 *c = &cpu_data(cpu);
118 long retval;
119
120 if (!cpu_cstate_entry || c->cpuid_level < CPUID_MWAIT_LEAF)
121 return -1;
122
123 if (reg->bit_offset != NATIVE_CSTATE_BEYOND_HALT)
124 return -1;
125
126 percpu_entry = per_cpu_ptr(cpu_cstate_entry, cpu);
127 percpu_entry->states[cx->index].eax = 0;
128 percpu_entry->states[cx->index].ecx = 0;
129
130 /* Make sure we are running on right CPU */
131
132 retval = work_on_cpu(cpu, acpi_processor_ffh_cstate_probe_cpu, cx);
133 if (retval == 0) {
134 /* Use the hint in CST */
135 percpu_entry->states[cx->index].eax = cx->address;
136 percpu_entry->states[cx->index].ecx = MWAIT_ECX_INTERRUPT_BREAK;
137 }
138 return retval;
139 }
140 EXPORT_SYMBOL_GPL(acpi_processor_ffh_cstate_probe);
141
acpi_processor_ffh_cstate_enter(struct acpi_processor_cx * cx)142 void acpi_processor_ffh_cstate_enter(struct acpi_processor_cx *cx)
143 {
144 unsigned int cpu = smp_processor_id();
145 struct cstate_entry *percpu_entry;
146
147 percpu_entry = per_cpu_ptr(cpu_cstate_entry, cpu);
148 mwait_idle_with_hints(percpu_entry->states[cx->index].eax,
149 percpu_entry->states[cx->index].ecx);
150 }
151 EXPORT_SYMBOL_GPL(acpi_processor_ffh_cstate_enter);
152
ffh_cstate_init(void)153 static int __init ffh_cstate_init(void)
154 {
155 struct cpuinfo_x86 *c = &boot_cpu_data;
156 if (c->x86_vendor != X86_VENDOR_INTEL)
157 return -1;
158
159 cpu_cstate_entry = alloc_percpu(struct cstate_entry);
160 return 0;
161 }
162
ffh_cstate_exit(void)163 static void __exit ffh_cstate_exit(void)
164 {
165 free_percpu(cpu_cstate_entry);
166 cpu_cstate_entry = NULL;
167 }
168
169 arch_initcall(ffh_cstate_init);
170 __exitcall(ffh_cstate_exit);
171