1 #include <linux/init.h>
2 #include <linux/kernel.h>
3
4 #include <linux/string.h>
5 #include <linux/bitops.h>
6 #include <linux/smp.h>
7 #include <linux/thread_info.h>
8 #include <linux/module.h>
9
10 #include <asm/processor.h>
11 #include <asm/pgtable.h>
12 #include <asm/msr.h>
13 #include <asm/uaccess.h>
14 #include <asm/ds.h>
15 #include <asm/bugs.h>
16
17 #ifdef CONFIG_X86_64
18 #include <asm/topology.h>
19 #include <asm/numa_64.h>
20 #endif
21
22 #include "cpu.h"
23
24 #ifdef CONFIG_X86_LOCAL_APIC
25 #include <asm/mpspec.h>
26 #include <asm/apic.h>
27 #include <mach_apic.h>
28 #endif
29
early_init_intel(struct cpuinfo_x86 * c)30 static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
31 {
32 /* Unmask CPUID levels if masked: */
33 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
34 u64 misc_enable;
35
36 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
37
38 if (misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID) {
39 misc_enable &= ~MSR_IA32_MISC_ENABLE_LIMIT_CPUID;
40 wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
41 c->cpuid_level = cpuid_eax(0);
42 }
43 }
44
45 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
46 (c->x86 == 0x6 && c->x86_model >= 0x0e))
47 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
48
49 #ifdef CONFIG_X86_64
50 set_cpu_cap(c, X86_FEATURE_SYSENTER32);
51 #else
52 /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
53 if (c->x86 == 15 && c->x86_cache_alignment == 64)
54 c->x86_cache_alignment = 128;
55 #endif
56
57 /*
58 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
59 * with P/T states and does not stop in deep C-states
60 */
61 if (c->x86_power & (1 << 8)) {
62 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
63 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
64 }
65
66 }
67
68 #ifdef CONFIG_X86_32
69 /*
70 * Early probe support logic for ppro memory erratum #50
71 *
72 * This is called before we do cpu ident work
73 */
74
ppro_with_ram_bug(void)75 int __cpuinit ppro_with_ram_bug(void)
76 {
77 /* Uses data from early_cpu_detect now */
78 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
79 boot_cpu_data.x86 == 6 &&
80 boot_cpu_data.x86_model == 1 &&
81 boot_cpu_data.x86_mask < 8) {
82 printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n");
83 return 1;
84 }
85 return 0;
86 }
87
88 #ifdef CONFIG_X86_F00F_BUG
trap_init_f00f_bug(void)89 static void __cpuinit trap_init_f00f_bug(void)
90 {
91 __set_fixmap(FIX_F00F_IDT, __pa(&idt_table), PAGE_KERNEL_RO);
92
93 /*
94 * Update the IDT descriptor and reload the IDT so that
95 * it uses the read-only mapped virtual address.
96 */
97 idt_descr.address = fix_to_virt(FIX_F00F_IDT);
98 load_idt(&idt_descr);
99 }
100 #endif
101
intel_workarounds(struct cpuinfo_x86 * c)102 static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
103 {
104 unsigned long lo, hi;
105
106 #ifdef CONFIG_X86_F00F_BUG
107 /*
108 * All current models of Pentium and Pentium with MMX technology CPUs
109 * have the F0 0F bug, which lets nonprivileged users lock up the system.
110 * Note that the workaround only should be initialized once...
111 */
112 c->f00f_bug = 0;
113 if (!paravirt_enabled() && c->x86 == 5) {
114 static int f00f_workaround_enabled;
115
116 c->f00f_bug = 1;
117 if (!f00f_workaround_enabled) {
118 trap_init_f00f_bug();
119 printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n");
120 f00f_workaround_enabled = 1;
121 }
122 }
123 #endif
124
125 /*
126 * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
127 * model 3 mask 3
128 */
129 if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
130 clear_cpu_cap(c, X86_FEATURE_SEP);
131
132 /*
133 * P4 Xeon errata 037 workaround.
134 * Hardware prefetcher may cause stale data to be loaded into the cache.
135 */
136 if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
137 rdmsr(MSR_IA32_MISC_ENABLE, lo, hi);
138 if ((lo & (1<<9)) == 0) {
139 printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
140 printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
141 lo |= (1<<9); /* Disable hw prefetching */
142 wrmsr (MSR_IA32_MISC_ENABLE, lo, hi);
143 }
144 }
145
146 /*
147 * See if we have a good local APIC by checking for buggy Pentia,
148 * i.e. all B steppings and the C2 stepping of P54C when using their
149 * integrated APIC (see 11AP erratum in "Pentium Processor
150 * Specification Update").
151 */
152 if (cpu_has_apic && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
153 (c->x86_mask < 0x6 || c->x86_mask == 0xb))
154 set_cpu_cap(c, X86_FEATURE_11AP);
155
156
157 #ifdef CONFIG_X86_INTEL_USERCOPY
158 /*
159 * Set up the preferred alignment for movsl bulk memory moves
160 */
161 switch (c->x86) {
162 case 4: /* 486: untested */
163 break;
164 case 5: /* Old Pentia: untested */
165 break;
166 case 6: /* PII/PIII only like movsl with 8-byte alignment */
167 movsl_mask.mask = 7;
168 break;
169 case 15: /* P4 is OK down to 8-byte alignment */
170 movsl_mask.mask = 7;
171 break;
172 }
173 #endif
174
175 #ifdef CONFIG_X86_NUMAQ
176 numaq_tsc_disable();
177 #endif
178 }
179 #else
intel_workarounds(struct cpuinfo_x86 * c)180 static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
181 {
182 }
183 #endif
184
srat_detect_node(void)185 static void __cpuinit srat_detect_node(void)
186 {
187 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64)
188 unsigned node;
189 int cpu = smp_processor_id();
190 int apicid = hard_smp_processor_id();
191
192 /* Don't do the funky fallback heuristics the AMD version employs
193 for now. */
194 node = apicid_to_node[apicid];
195 if (node == NUMA_NO_NODE || !node_online(node))
196 node = first_node(node_online_map);
197 numa_set_node(cpu, node);
198
199 printk(KERN_INFO "CPU %d/0x%x -> Node %d\n", cpu, apicid, node);
200 #endif
201 }
202
203 /*
204 * find out the number of processor cores on the die
205 */
intel_num_cpu_cores(struct cpuinfo_x86 * c)206 static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
207 {
208 unsigned int eax, ebx, ecx, edx;
209
210 if (c->cpuid_level < 4)
211 return 1;
212
213 /* Intel has a non-standard dependency on %ecx for this CPUID level. */
214 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
215 if (eax & 0x1f)
216 return ((eax >> 26) + 1);
217 else
218 return 1;
219 }
220
detect_vmx_virtcap(struct cpuinfo_x86 * c)221 static void __cpuinit detect_vmx_virtcap(struct cpuinfo_x86 *c)
222 {
223 /* Intel VMX MSR indicated features */
224 #define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW 0x00200000
225 #define X86_VMX_FEATURE_PROC_CTLS_VNMI 0x00400000
226 #define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS 0x80000000
227 #define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC 0x00000001
228 #define X86_VMX_FEATURE_PROC_CTLS2_EPT 0x00000002
229 #define X86_VMX_FEATURE_PROC_CTLS2_VPID 0x00000020
230
231 u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;
232
233 clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
234 clear_cpu_cap(c, X86_FEATURE_VNMI);
235 clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
236 clear_cpu_cap(c, X86_FEATURE_EPT);
237 clear_cpu_cap(c, X86_FEATURE_VPID);
238
239 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);
240 msr_ctl = vmx_msr_high | vmx_msr_low;
241 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)
242 set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
243 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI)
244 set_cpu_cap(c, X86_FEATURE_VNMI);
245 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) {
246 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
247 vmx_msr_low, vmx_msr_high);
248 msr_ctl2 = vmx_msr_high | vmx_msr_low;
249 if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) &&
250 (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW))
251 set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
252 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT)
253 set_cpu_cap(c, X86_FEATURE_EPT);
254 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID)
255 set_cpu_cap(c, X86_FEATURE_VPID);
256 }
257 }
258
init_intel(struct cpuinfo_x86 * c)259 static void __cpuinit init_intel(struct cpuinfo_x86 *c)
260 {
261 unsigned int l2 = 0;
262
263 early_init_intel(c);
264
265 intel_workarounds(c);
266
267 /*
268 * Detect the extended topology information if available. This
269 * will reinitialise the initial_apicid which will be used
270 * in init_intel_cacheinfo()
271 */
272 detect_extended_topology(c);
273
274 l2 = init_intel_cacheinfo(c);
275 if (c->cpuid_level > 9) {
276 unsigned eax = cpuid_eax(10);
277 /* Check for version and the number of counters */
278 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
279 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
280 }
281
282 if (cpu_has_xmm2)
283 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
284 if (cpu_has_ds) {
285 unsigned int l1;
286 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
287 if (!(l1 & (1<<11)))
288 set_cpu_cap(c, X86_FEATURE_BTS);
289 if (!(l1 & (1<<12)))
290 set_cpu_cap(c, X86_FEATURE_PEBS);
291 ds_init_intel(c);
292 }
293
294 if (c->x86 == 6 && c->x86_model == 29 && cpu_has_clflush)
295 set_cpu_cap(c, X86_FEATURE_CLFLUSH_MONITOR);
296
297 #ifdef CONFIG_X86_64
298 if (c->x86 == 15)
299 c->x86_cache_alignment = c->x86_clflush_size * 2;
300 if (c->x86 == 6)
301 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
302 #else
303 /*
304 * Names for the Pentium II/Celeron processors
305 * detectable only by also checking the cache size.
306 * Dixon is NOT a Celeron.
307 */
308 if (c->x86 == 6) {
309 char *p = NULL;
310
311 switch (c->x86_model) {
312 case 5:
313 if (c->x86_mask == 0) {
314 if (l2 == 0)
315 p = "Celeron (Covington)";
316 else if (l2 == 256)
317 p = "Mobile Pentium II (Dixon)";
318 }
319 break;
320
321 case 6:
322 if (l2 == 128)
323 p = "Celeron (Mendocino)";
324 else if (c->x86_mask == 0 || c->x86_mask == 5)
325 p = "Celeron-A";
326 break;
327
328 case 8:
329 if (l2 == 128)
330 p = "Celeron (Coppermine)";
331 break;
332 }
333
334 if (p)
335 strcpy(c->x86_model_id, p);
336 }
337
338 if (c->x86 == 15)
339 set_cpu_cap(c, X86_FEATURE_P4);
340 if (c->x86 == 6)
341 set_cpu_cap(c, X86_FEATURE_P3);
342 #endif
343
344 if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
345 /*
346 * let's use the legacy cpuid vector 0x1 and 0x4 for topology
347 * detection.
348 */
349 c->x86_max_cores = intel_num_cpu_cores(c);
350 #ifdef CONFIG_X86_32
351 detect_ht(c);
352 #endif
353 }
354
355 /* Work around errata */
356 srat_detect_node();
357
358 if (cpu_has(c, X86_FEATURE_VMX))
359 detect_vmx_virtcap(c);
360 }
361
362 #ifdef CONFIG_X86_32
intel_size_cache(struct cpuinfo_x86 * c,unsigned int size)363 static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
364 {
365 /*
366 * Intel PIII Tualatin. This comes in two flavours.
367 * One has 256kb of cache, the other 512. We have no way
368 * to determine which, so we use a boottime override
369 * for the 512kb model, and assume 256 otherwise.
370 */
371 if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
372 size = 256;
373 return size;
374 }
375 #endif
376
377 static struct cpu_dev intel_cpu_dev __cpuinitdata = {
378 .c_vendor = "Intel",
379 .c_ident = { "GenuineIntel" },
380 #ifdef CONFIG_X86_32
381 .c_models = {
382 { .vendor = X86_VENDOR_INTEL, .family = 4, .model_names =
383 {
384 [0] = "486 DX-25/33",
385 [1] = "486 DX-50",
386 [2] = "486 SX",
387 [3] = "486 DX/2",
388 [4] = "486 SL",
389 [5] = "486 SX/2",
390 [7] = "486 DX/2-WB",
391 [8] = "486 DX/4",
392 [9] = "486 DX/4-WB"
393 }
394 },
395 { .vendor = X86_VENDOR_INTEL, .family = 5, .model_names =
396 {
397 [0] = "Pentium 60/66 A-step",
398 [1] = "Pentium 60/66",
399 [2] = "Pentium 75 - 200",
400 [3] = "OverDrive PODP5V83",
401 [4] = "Pentium MMX",
402 [7] = "Mobile Pentium 75 - 200",
403 [8] = "Mobile Pentium MMX"
404 }
405 },
406 { .vendor = X86_VENDOR_INTEL, .family = 6, .model_names =
407 {
408 [0] = "Pentium Pro A-step",
409 [1] = "Pentium Pro",
410 [3] = "Pentium II (Klamath)",
411 [4] = "Pentium II (Deschutes)",
412 [5] = "Pentium II (Deschutes)",
413 [6] = "Mobile Pentium II",
414 [7] = "Pentium III (Katmai)",
415 [8] = "Pentium III (Coppermine)",
416 [10] = "Pentium III (Cascades)",
417 [11] = "Pentium III (Tualatin)",
418 }
419 },
420 { .vendor = X86_VENDOR_INTEL, .family = 15, .model_names =
421 {
422 [0] = "Pentium 4 (Unknown)",
423 [1] = "Pentium 4 (Willamette)",
424 [2] = "Pentium 4 (Northwood)",
425 [4] = "Pentium 4 (Foster)",
426 [5] = "Pentium 4 (Foster)",
427 }
428 },
429 },
430 .c_size_cache = intel_size_cache,
431 #endif
432 .c_early_init = early_init_intel,
433 .c_init = init_intel,
434 .c_x86_vendor = X86_VENDOR_INTEL,
435 };
436
437 cpu_dev_register(intel_cpu_dev);
438
439