1 /*
2 * SGI Visual Workstation support and quirks, unmaintained.
3 *
4 * Split out from setup.c by davej@suse.de
5 *
6 * Copyright (C) 1999 Bent Hagemark, Ingo Molnar
7 *
8 * SGI Visual Workstation interrupt controller
9 *
10 * The Cobalt system ASIC in the Visual Workstation contains a "Cobalt" APIC
11 * which serves as the main interrupt controller in the system. Non-legacy
12 * hardware in the system uses this controller directly. Legacy devices
13 * are connected to the PIIX4 which in turn has its 8259(s) connected to
14 * a of the Cobalt APIC entry.
15 *
16 * 09/02/2000 - Updated for 2.4 by jbarnes@sgi.com
17 *
18 * 25/11/2002 - Updated for 2.5 by Andrey Panin <pazke@orbita1.ru>
19 */
20 #include <linux/interrupt.h>
21 #include <linux/module.h>
22 #include <linux/init.h>
23 #include <linux/smp.h>
24
25 #include <asm/visws/cobalt.h>
26 #include <asm/visws/piix4.h>
27 #include <asm/arch_hooks.h>
28 #include <asm/io_apic.h>
29 #include <asm/fixmap.h>
30 #include <asm/reboot.h>
31 #include <asm/setup.h>
32 #include <asm/e820.h>
33 #include <asm/io.h>
34
35 #include <mach_ipi.h>
36
37 #include "mach_apic.h"
38
39 #include <linux/kernel_stat.h>
40
41 #include <asm/i8259.h>
42 #include <asm/irq_vectors.h>
43 #include <asm/visws/lithium.h>
44
45 #include <linux/sched.h>
46 #include <linux/kernel.h>
47 #include <linux/pci.h>
48 #include <linux/pci_ids.h>
49
50 extern int no_broadcast;
51
52 #include <asm/apic.h>
53
54 char visws_board_type = -1;
55 char visws_board_rev = -1;
56
is_visws_box(void)57 int is_visws_box(void)
58 {
59 return visws_board_type >= 0;
60 }
61
visws_time_init(void)62 static int __init visws_time_init(void)
63 {
64 printk(KERN_INFO "Starting Cobalt Timer system clock\n");
65
66 /* Set the countdown value */
67 co_cpu_write(CO_CPU_TIMEVAL, CO_TIME_HZ/HZ);
68
69 /* Start the timer */
70 co_cpu_write(CO_CPU_CTRL, co_cpu_read(CO_CPU_CTRL) | CO_CTRL_TIMERUN);
71
72 /* Enable (unmask) the timer interrupt */
73 co_cpu_write(CO_CPU_CTRL, co_cpu_read(CO_CPU_CTRL) & ~CO_CTRL_TIMEMASK);
74
75 /*
76 * Zero return means the generic timer setup code will set up
77 * the standard vector:
78 */
79 return 0;
80 }
81
visws_pre_intr_init(void)82 static int __init visws_pre_intr_init(void)
83 {
84 init_VISWS_APIC_irqs();
85
86 /*
87 * We dont want ISA irqs to be set up by the generic code:
88 */
89 return 1;
90 }
91
92 /* Quirk for machine specific memory setup. */
93
94 #define MB (1024 * 1024)
95
96 unsigned long sgivwfb_mem_phys;
97 unsigned long sgivwfb_mem_size;
98 EXPORT_SYMBOL(sgivwfb_mem_phys);
99 EXPORT_SYMBOL(sgivwfb_mem_size);
100
101 long long mem_size __initdata = 0;
102
visws_memory_setup(void)103 static char * __init visws_memory_setup(void)
104 {
105 long long gfx_mem_size = 8 * MB;
106
107 mem_size = boot_params.alt_mem_k;
108
109 if (!mem_size) {
110 printk(KERN_WARNING "Bootloader didn't set memory size, upgrade it !\n");
111 mem_size = 128 * MB;
112 }
113
114 /*
115 * this hardcodes the graphics memory to 8 MB
116 * it really should be sized dynamically (or at least
117 * set as a boot param)
118 */
119 if (!sgivwfb_mem_size) {
120 printk(KERN_WARNING "Defaulting to 8 MB framebuffer size\n");
121 sgivwfb_mem_size = 8 * MB;
122 }
123
124 /*
125 * Trim to nearest MB
126 */
127 sgivwfb_mem_size &= ~((1 << 20) - 1);
128 sgivwfb_mem_phys = mem_size - gfx_mem_size;
129
130 e820_add_region(0, LOWMEMSIZE(), E820_RAM);
131 e820_add_region(HIGH_MEMORY, mem_size - sgivwfb_mem_size - HIGH_MEMORY, E820_RAM);
132 e820_add_region(sgivwfb_mem_phys, sgivwfb_mem_size, E820_RESERVED);
133
134 return "PROM";
135 }
136
visws_machine_emergency_restart(void)137 static void visws_machine_emergency_restart(void)
138 {
139 /*
140 * Visual Workstations restart after this
141 * register is poked on the PIIX4
142 */
143 outb(PIIX4_RESET_VAL, PIIX4_RESET_PORT);
144 }
145
visws_machine_power_off(void)146 static void visws_machine_power_off(void)
147 {
148 unsigned short pm_status;
149 /* extern unsigned int pci_bus0; */
150
151 while ((pm_status = inw(PMSTS_PORT)) & 0x100)
152 outw(pm_status, PMSTS_PORT);
153
154 outw(PM_SUSPEND_ENABLE, PMCNTRL_PORT);
155
156 mdelay(10);
157
158 #define PCI_CONF1_ADDRESS(bus, devfn, reg) \
159 (0x80000000 | (bus << 16) | (devfn << 8) | (reg & ~3))
160
161 /* outl(PCI_CONF1_ADDRESS(pci_bus0, SPECIAL_DEV, SPECIAL_REG), 0xCF8); */
162 outl(PIIX_SPECIAL_STOP, 0xCFC);
163 }
164
visws_get_smp_config(unsigned int early)165 static int __init visws_get_smp_config(unsigned int early)
166 {
167 /*
168 * Prevent MP-table parsing by the generic code:
169 */
170 return 1;
171 }
172
173 /*
174 * The Visual Workstation is Intel MP compliant in the hardware
175 * sense, but it doesn't have a BIOS(-configuration table).
176 * No problem for Linux.
177 */
178
MP_processor_info(struct mpc_cpu * m)179 static void __init MP_processor_info(struct mpc_cpu *m)
180 {
181 int ver, logical_apicid;
182 physid_mask_t apic_cpus;
183
184 if (!(m->cpuflag & CPU_ENABLED))
185 return;
186
187 logical_apicid = m->apicid;
188 printk(KERN_INFO "%sCPU #%d %u:%u APIC version %d\n",
189 m->cpuflag & CPU_BOOTPROCESSOR ? "Bootup " : "",
190 m->apicid, (m->cpufeature & CPU_FAMILY_MASK) >> 8,
191 (m->cpufeature & CPU_MODEL_MASK) >> 4, m->apicver);
192
193 if (m->cpuflag & CPU_BOOTPROCESSOR)
194 boot_cpu_physical_apicid = m->apicid;
195
196 ver = m->apicver;
197 if ((ver >= 0x14 && m->apicid >= 0xff) || m->apicid >= 0xf) {
198 printk(KERN_ERR "Processor #%d INVALID. (Max ID: %d).\n",
199 m->apicid, MAX_APICS);
200 return;
201 }
202
203 apic_cpus = apicid_to_cpu_present(m->apicid);
204 physids_or(phys_cpu_present_map, phys_cpu_present_map, apic_cpus);
205 /*
206 * Validate version
207 */
208 if (ver == 0x0) {
209 printk(KERN_ERR "BIOS bug, APIC version is 0 for CPU#%d! "
210 "fixing up to 0x10. (tell your hw vendor)\n",
211 m->apicid);
212 ver = 0x10;
213 }
214 apic_version[m->apicid] = ver;
215 }
216
visws_find_smp_config(unsigned int reserve)217 static int __init visws_find_smp_config(unsigned int reserve)
218 {
219 struct mpc_cpu *mp = phys_to_virt(CO_CPU_TAB_PHYS);
220 unsigned short ncpus = readw(phys_to_virt(CO_CPU_NUM_PHYS));
221
222 if (ncpus > CO_CPU_MAX) {
223 printk(KERN_WARNING "find_visws_smp: got cpu count of %d at %p\n",
224 ncpus, mp);
225
226 ncpus = CO_CPU_MAX;
227 }
228
229 if (ncpus > setup_max_cpus)
230 ncpus = setup_max_cpus;
231
232 #ifdef CONFIG_X86_LOCAL_APIC
233 smp_found_config = 1;
234 #endif
235 while (ncpus--)
236 MP_processor_info(mp++);
237
238 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
239
240 return 1;
241 }
242
243 static int visws_trap_init(void);
244
245 static struct x86_quirks visws_x86_quirks __initdata = {
246 .arch_time_init = visws_time_init,
247 .arch_pre_intr_init = visws_pre_intr_init,
248 .arch_memory_setup = visws_memory_setup,
249 .arch_intr_init = NULL,
250 .arch_trap_init = visws_trap_init,
251 .mach_get_smp_config = visws_get_smp_config,
252 .mach_find_smp_config = visws_find_smp_config,
253 };
254
visws_early_detect(void)255 void __init visws_early_detect(void)
256 {
257 int raw;
258
259 visws_board_type = (char)(inb_p(PIIX_GPI_BD_REG) & PIIX_GPI_BD_REG)
260 >> PIIX_GPI_BD_SHIFT;
261
262 if (visws_board_type < 0)
263 return;
264
265 /*
266 * Install special quirks for timer, interrupt and memory setup:
267 * Fall back to generic behavior for traps:
268 * Override generic MP-table parsing:
269 */
270 x86_quirks = &visws_x86_quirks;
271
272 /*
273 * Install reboot quirks:
274 */
275 pm_power_off = visws_machine_power_off;
276 machine_ops.emergency_restart = visws_machine_emergency_restart;
277
278 /*
279 * Do not use broadcast IPIs:
280 */
281 no_broadcast = 0;
282
283 #ifdef CONFIG_X86_IO_APIC
284 /*
285 * Turn off IO-APIC detection and initialization:
286 */
287 skip_ioapic_setup = 1;
288 #endif
289
290 /*
291 * Get Board rev.
292 * First, we have to initialize the 307 part to allow us access
293 * to the GPIO registers. Let's map them at 0x0fc0 which is right
294 * after the PIIX4 PM section.
295 */
296 outb_p(SIO_DEV_SEL, SIO_INDEX);
297 outb_p(SIO_GP_DEV, SIO_DATA); /* Talk to GPIO regs. */
298
299 outb_p(SIO_DEV_MSB, SIO_INDEX);
300 outb_p(SIO_GP_MSB, SIO_DATA); /* MSB of GPIO base address */
301
302 outb_p(SIO_DEV_LSB, SIO_INDEX);
303 outb_p(SIO_GP_LSB, SIO_DATA); /* LSB of GPIO base address */
304
305 outb_p(SIO_DEV_ENB, SIO_INDEX);
306 outb_p(1, SIO_DATA); /* Enable GPIO registers. */
307
308 /*
309 * Now, we have to map the power management section to write
310 * a bit which enables access to the GPIO registers.
311 * What lunatic came up with this shit?
312 */
313 outb_p(SIO_DEV_SEL, SIO_INDEX);
314 outb_p(SIO_PM_DEV, SIO_DATA); /* Talk to GPIO regs. */
315
316 outb_p(SIO_DEV_MSB, SIO_INDEX);
317 outb_p(SIO_PM_MSB, SIO_DATA); /* MSB of PM base address */
318
319 outb_p(SIO_DEV_LSB, SIO_INDEX);
320 outb_p(SIO_PM_LSB, SIO_DATA); /* LSB of PM base address */
321
322 outb_p(SIO_DEV_ENB, SIO_INDEX);
323 outb_p(1, SIO_DATA); /* Enable PM registers. */
324
325 /*
326 * Now, write the PM register which enables the GPIO registers.
327 */
328 outb_p(SIO_PM_FER2, SIO_PM_INDEX);
329 outb_p(SIO_PM_GP_EN, SIO_PM_DATA);
330
331 /*
332 * Now, initialize the GPIO registers.
333 * We want them all to be inputs which is the
334 * power on default, so let's leave them alone.
335 * So, let's just read the board rev!
336 */
337 raw = inb_p(SIO_GP_DATA1);
338 raw &= 0x7f; /* 7 bits of valid board revision ID. */
339
340 if (visws_board_type == VISWS_320) {
341 if (raw < 0x6) {
342 visws_board_rev = 4;
343 } else if (raw < 0xc) {
344 visws_board_rev = 5;
345 } else {
346 visws_board_rev = 6;
347 }
348 } else if (visws_board_type == VISWS_540) {
349 visws_board_rev = 2;
350 } else {
351 visws_board_rev = raw;
352 }
353
354 printk(KERN_INFO "Silicon Graphics Visual Workstation %s (rev %d) detected\n",
355 (visws_board_type == VISWS_320 ? "320" :
356 (visws_board_type == VISWS_540 ? "540" :
357 "unknown")), visws_board_rev);
358 }
359
360 #define A01234 (LI_INTA_0 | LI_INTA_1 | LI_INTA_2 | LI_INTA_3 | LI_INTA_4)
361 #define BCD (LI_INTB | LI_INTC | LI_INTD)
362 #define ALLDEVS (A01234 | BCD)
363
lithium_init(void)364 static __init void lithium_init(void)
365 {
366 set_fixmap(FIX_LI_PCIA, LI_PCI_A_PHYS);
367 set_fixmap(FIX_LI_PCIB, LI_PCI_B_PHYS);
368
369 if ((li_pcia_read16(PCI_VENDOR_ID) != PCI_VENDOR_ID_SGI) ||
370 (li_pcia_read16(PCI_DEVICE_ID) != PCI_DEVICE_ID_SGI_LITHIUM)) {
371 printk(KERN_EMERG "Lithium hostbridge %c not found\n", 'A');
372 /* panic("This machine is not SGI Visual Workstation 320/540"); */
373 }
374
375 if ((li_pcib_read16(PCI_VENDOR_ID) != PCI_VENDOR_ID_SGI) ||
376 (li_pcib_read16(PCI_DEVICE_ID) != PCI_DEVICE_ID_SGI_LITHIUM)) {
377 printk(KERN_EMERG "Lithium hostbridge %c not found\n", 'B');
378 /* panic("This machine is not SGI Visual Workstation 320/540"); */
379 }
380
381 li_pcia_write16(LI_PCI_INTEN, ALLDEVS);
382 li_pcib_write16(LI_PCI_INTEN, ALLDEVS);
383 }
384
cobalt_init(void)385 static __init void cobalt_init(void)
386 {
387 /*
388 * On normal SMP PC this is used only with SMP, but we have to
389 * use it and set it up here to start the Cobalt clock
390 */
391 set_fixmap(FIX_APIC_BASE, APIC_DEFAULT_PHYS_BASE);
392 setup_local_APIC();
393 printk(KERN_INFO "Local APIC Version %#x, ID %#x\n",
394 (unsigned int)apic_read(APIC_LVR),
395 (unsigned int)apic_read(APIC_ID));
396
397 set_fixmap(FIX_CO_CPU, CO_CPU_PHYS);
398 set_fixmap(FIX_CO_APIC, CO_APIC_PHYS);
399 printk(KERN_INFO "Cobalt Revision %#lx, APIC ID %#lx\n",
400 co_cpu_read(CO_CPU_REV), co_apic_read(CO_APIC_ID));
401
402 /* Enable Cobalt APIC being careful to NOT change the ID! */
403 co_apic_write(CO_APIC_ID, co_apic_read(CO_APIC_ID) | CO_APIC_ENABLE);
404
405 printk(KERN_INFO "Cobalt APIC enabled: ID reg %#lx\n",
406 co_apic_read(CO_APIC_ID));
407 }
408
visws_trap_init(void)409 static int __init visws_trap_init(void)
410 {
411 lithium_init();
412 cobalt_init();
413
414 return 1;
415 }
416
417 /*
418 * IRQ controller / APIC support:
419 */
420
421 static DEFINE_SPINLOCK(cobalt_lock);
422
423 /*
424 * Set the given Cobalt APIC Redirection Table entry to point
425 * to the given IDT vector/index.
426 */
co_apic_set(int entry,int irq)427 static inline void co_apic_set(int entry, int irq)
428 {
429 co_apic_write(CO_APIC_LO(entry), CO_APIC_LEVEL | (irq + FIRST_EXTERNAL_VECTOR));
430 co_apic_write(CO_APIC_HI(entry), 0);
431 }
432
433 /*
434 * Cobalt (IO)-APIC functions to handle PCI devices.
435 */
co_apic_ide0_hack(void)436 static inline int co_apic_ide0_hack(void)
437 {
438 extern char visws_board_type;
439 extern char visws_board_rev;
440
441 if (visws_board_type == VISWS_320 && visws_board_rev == 5)
442 return 5;
443 return CO_APIC_IDE0;
444 }
445
is_co_apic(unsigned int irq)446 static int is_co_apic(unsigned int irq)
447 {
448 if (IS_CO_APIC(irq))
449 return CO_APIC(irq);
450
451 switch (irq) {
452 case 0: return CO_APIC_CPU;
453 case CO_IRQ_IDE0: return co_apic_ide0_hack();
454 case CO_IRQ_IDE1: return CO_APIC_IDE1;
455 default: return -1;
456 }
457 }
458
459
460 /*
461 * This is the SGI Cobalt (IO-)APIC:
462 */
463
enable_cobalt_irq(unsigned int irq)464 static void enable_cobalt_irq(unsigned int irq)
465 {
466 co_apic_set(is_co_apic(irq), irq);
467 }
468
disable_cobalt_irq(unsigned int irq)469 static void disable_cobalt_irq(unsigned int irq)
470 {
471 int entry = is_co_apic(irq);
472
473 co_apic_write(CO_APIC_LO(entry), CO_APIC_MASK);
474 co_apic_read(CO_APIC_LO(entry));
475 }
476
477 /*
478 * "irq" really just serves to identify the device. Here is where we
479 * map this to the Cobalt APIC entry where it's physically wired.
480 * This is called via request_irq -> setup_irq -> irq_desc->startup()
481 */
startup_cobalt_irq(unsigned int irq)482 static unsigned int startup_cobalt_irq(unsigned int irq)
483 {
484 unsigned long flags;
485 struct irq_desc *desc = irq_to_desc(irq);
486
487 spin_lock_irqsave(&cobalt_lock, flags);
488 if ((desc->status & (IRQ_DISABLED | IRQ_INPROGRESS | IRQ_WAITING)))
489 desc->status &= ~(IRQ_DISABLED | IRQ_INPROGRESS | IRQ_WAITING);
490 enable_cobalt_irq(irq);
491 spin_unlock_irqrestore(&cobalt_lock, flags);
492 return 0;
493 }
494
ack_cobalt_irq(unsigned int irq)495 static void ack_cobalt_irq(unsigned int irq)
496 {
497 unsigned long flags;
498
499 spin_lock_irqsave(&cobalt_lock, flags);
500 disable_cobalt_irq(irq);
501 apic_write(APIC_EOI, APIC_EIO_ACK);
502 spin_unlock_irqrestore(&cobalt_lock, flags);
503 }
504
end_cobalt_irq(unsigned int irq)505 static void end_cobalt_irq(unsigned int irq)
506 {
507 unsigned long flags;
508 struct irq_desc *desc = irq_to_desc(irq);
509
510 spin_lock_irqsave(&cobalt_lock, flags);
511 if (!(desc->status & (IRQ_DISABLED | IRQ_INPROGRESS)))
512 enable_cobalt_irq(irq);
513 spin_unlock_irqrestore(&cobalt_lock, flags);
514 }
515
516 static struct irq_chip cobalt_irq_type = {
517 .typename = "Cobalt-APIC",
518 .startup = startup_cobalt_irq,
519 .shutdown = disable_cobalt_irq,
520 .enable = enable_cobalt_irq,
521 .disable = disable_cobalt_irq,
522 .ack = ack_cobalt_irq,
523 .end = end_cobalt_irq,
524 };
525
526
527 /*
528 * This is the PIIX4-based 8259 that is wired up indirectly to Cobalt
529 * -- not the manner expected by the code in i8259.c.
530 *
531 * there is a 'master' physical interrupt source that gets sent to
532 * the CPU. But in the chipset there are various 'virtual' interrupts
533 * waiting to be handled. We represent this to Linux through a 'master'
534 * interrupt controller type, and through a special virtual interrupt-
535 * controller. Device drivers only see the virtual interrupt sources.
536 */
startup_piix4_master_irq(unsigned int irq)537 static unsigned int startup_piix4_master_irq(unsigned int irq)
538 {
539 init_8259A(0);
540
541 return startup_cobalt_irq(irq);
542 }
543
end_piix4_master_irq(unsigned int irq)544 static void end_piix4_master_irq(unsigned int irq)
545 {
546 unsigned long flags;
547
548 spin_lock_irqsave(&cobalt_lock, flags);
549 enable_cobalt_irq(irq);
550 spin_unlock_irqrestore(&cobalt_lock, flags);
551 }
552
553 static struct irq_chip piix4_master_irq_type = {
554 .typename = "PIIX4-master",
555 .startup = startup_piix4_master_irq,
556 .ack = ack_cobalt_irq,
557 .end = end_piix4_master_irq,
558 };
559
560
561 static struct irq_chip piix4_virtual_irq_type = {
562 .typename = "PIIX4-virtual",
563 .shutdown = disable_8259A_irq,
564 .enable = enable_8259A_irq,
565 .disable = disable_8259A_irq,
566 };
567
568
569 /*
570 * PIIX4-8259 master/virtual functions to handle interrupt requests
571 * from legacy devices: floppy, parallel, serial, rtc.
572 *
573 * None of these get Cobalt APIC entries, neither do they have IDT
574 * entries. These interrupts are purely virtual and distributed from
575 * the 'master' interrupt source: CO_IRQ_8259.
576 *
577 * When the 8259 interrupts its handler figures out which of these
578 * devices is interrupting and dispatches to its handler.
579 *
580 * CAREFUL: devices see the 'virtual' interrupt only. Thus disable/
581 * enable_irq gets the right irq. This 'master' irq is never directly
582 * manipulated by any driver.
583 */
piix4_master_intr(int irq,void * dev_id)584 static irqreturn_t piix4_master_intr(int irq, void *dev_id)
585 {
586 int realirq;
587 irq_desc_t *desc;
588 unsigned long flags;
589
590 spin_lock_irqsave(&i8259A_lock, flags);
591
592 /* Find out what's interrupting in the PIIX4 master 8259 */
593 outb(0x0c, 0x20); /* OCW3 Poll command */
594 realirq = inb(0x20);
595
596 /*
597 * Bit 7 == 0 means invalid/spurious
598 */
599 if (unlikely(!(realirq & 0x80)))
600 goto out_unlock;
601
602 realirq &= 7;
603
604 if (unlikely(realirq == 2)) {
605 outb(0x0c, 0xa0);
606 realirq = inb(0xa0);
607
608 if (unlikely(!(realirq & 0x80)))
609 goto out_unlock;
610
611 realirq = (realirq & 7) + 8;
612 }
613
614 /* mask and ack interrupt */
615 cached_irq_mask |= 1 << realirq;
616 if (unlikely(realirq > 7)) {
617 inb(0xa1);
618 outb(cached_slave_mask, 0xa1);
619 outb(0x60 + (realirq & 7), 0xa0);
620 outb(0x60 + 2, 0x20);
621 } else {
622 inb(0x21);
623 outb(cached_master_mask, 0x21);
624 outb(0x60 + realirq, 0x20);
625 }
626
627 spin_unlock_irqrestore(&i8259A_lock, flags);
628
629 desc = irq_to_desc(realirq);
630
631 /*
632 * handle this 'virtual interrupt' as a Cobalt one now.
633 */
634 kstat_incr_irqs_this_cpu(realirq, desc);
635
636 if (likely(desc->action != NULL))
637 handle_IRQ_event(realirq, desc->action);
638
639 if (!(desc->status & IRQ_DISABLED))
640 enable_8259A_irq(realirq);
641
642 return IRQ_HANDLED;
643
644 out_unlock:
645 spin_unlock_irqrestore(&i8259A_lock, flags);
646 return IRQ_NONE;
647 }
648
649 static struct irqaction master_action = {
650 .handler = piix4_master_intr,
651 .name = "PIIX4-8259",
652 };
653
654 static struct irqaction cascade_action = {
655 .handler = no_action,
656 .name = "cascade",
657 };
658
659
init_VISWS_APIC_irqs(void)660 void init_VISWS_APIC_irqs(void)
661 {
662 int i;
663
664 for (i = 0; i < CO_IRQ_APIC0 + CO_APIC_LAST + 1; i++) {
665 struct irq_desc *desc = irq_to_desc(i);
666
667 desc->status = IRQ_DISABLED;
668 desc->action = 0;
669 desc->depth = 1;
670
671 if (i == 0) {
672 desc->chip = &cobalt_irq_type;
673 }
674 else if (i == CO_IRQ_IDE0) {
675 desc->chip = &cobalt_irq_type;
676 }
677 else if (i == CO_IRQ_IDE1) {
678 desc->chip = &cobalt_irq_type;
679 }
680 else if (i == CO_IRQ_8259) {
681 desc->chip = &piix4_master_irq_type;
682 }
683 else if (i < CO_IRQ_APIC0) {
684 desc->chip = &piix4_virtual_irq_type;
685 }
686 else if (IS_CO_APIC(i)) {
687 desc->chip = &cobalt_irq_type;
688 }
689 }
690
691 setup_irq(CO_IRQ_8259, &master_action);
692 setup_irq(2, &cascade_action);
693 }
694